As we cannot wait upon an object to be released by the GPU once we have
disabled pagefaults, process any pending retirements first in the hope
that we move any potential relocations off the active list.
References: https://bugs.freedesktop.org/show_bug.cgi?id=35733
Signed-off-by: Chris Wilson ch
Toggle the Software Clear Interrupt bit which resets the controller to
clear any prior BUS_ERROR condition before we begin to use the
controller in earnest.
Suggested-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_i2c.c
... as they only had a single PCI-ID each, and so using the pci-id is
easier than using a capability bit.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c |2 --
drivers/gpu/drm/i915/i915_drv.c |9 +++--
drivers/gpu/drm/i915/i915_drv.h
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index afdbbd9..b92e8ea 100644
--- a/drivers/gpu/drm/i915
Keith complained that GMBUSx + reg_offset was ugly. An alternative
naming scheme which is more consistent with the reset of the code base
is to store the address of the GMBUS0 and then reference each of the
GMBUSx registers as an offset from GMBUS0.
Signed-off-by: Chris Wilson ch...@chris
of the optimisations, it turns out they are not so
micro after all. Running x11perf -aa10text on PineView:
before 1.28 Mglyph/sec
after 1.45 Mglyph/sec
(Glyphs, in general and on PineView in particular, are one of the very
few pwrite rate-limited workloads.)
Signed-off-by: Chris Wilson ch...@chris
The read back of the available FIFO entries is vital for system
stability, but extremely costly. However, we only need a guide so as to
avoid eating into the reserved entries and since we are the only
consumer we can cache the read of the count from the last write.
Signed-off-by: Chris Wilson ch
-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mathew McKernan matmcker...@rauland.com.au
---
drivers/gpu/drm/i915/intel_tv.c | 118 ---
1 files changed, 48 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
On Thu, 12 May 2011 17:40:42 -0700, Keith Packard kei...@keithp.com wrote:
On Thu, 12 May 2011 22:17:16 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Keith complained that GMBUSx + reg_offset was ugly. An alternative
naming scheme which is more consistent with the reset of the code
On Thu, 12 May 2011 18:16:00 -0700, Keith Packard kei...@keithp.com wrote:
On Thu, 12 May 2011 22:17:22 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
... as they only had a single PCI-ID each, and so using the pci-id is
easier than using a capability bit.
This doesn't seem useful
On Fri, 13 May 2011 08:01:51 -0700, Keith Packard kei...@keithp.com wrote:
On Fri, 13 May 2011 10:32:25 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
It has been booting daily on several machines for a month. I agree it
wouldn't have worked, but the since we automatically fallback
On Thu, 12 May 2011 17:21:50 -0700, Keith Packard kei...@keithp.com wrote:
On Thu, 12 May 2011 22:17:10 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
+ pages = kmalloc(n*sizeof(struct page *),
+ GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
+ if (pages == NULL
then hopefully
reproduce it and capture the error.
Thanks,
-Chris
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On Fri, 20 May 2011 11:08:56 -0700, Ray Lee ray...@madrabbit.org wrote:
[ Adding Chris Wilson (author of the problematic patch) and Rafael Wysocki
to the message ]
On Fri, May 20, 2011 at 10:06 AM, Luke-Jr l...@dashjr.org wrote:
I submitted https://bugzilla.kernel.org/show_bug.cgi?id
On Sat, 21 May 2011 11:23:53 -0400, Luke-Jr l...@dashjr.org wrote:
On Saturday, May 21, 2011 4:41:45 AM Chris Wilson wrote:
On Fri, 20 May 2011 11:08:56 -0700, Ray Lee ray...@madrabbit.org wrote:
[ Adding Chris Wilson (author of the problematic patch) and Rafael
Wysocki to the message
...@gentoo.org
Thanks,
-Chris
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...
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h| 21
drivers/gpu/drm/i915/i915_gem.c|7 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 139
On Sat, 04 Jun 2011 10:38:07 -0700, Keith Packard kei...@keithp.com wrote:
On Sat, 4 Jun 2011 09:55:43 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
I'm afraid you've completely lost me here. Can you provide a small
example (libdrm?) program which exhibits the failure so I can follow
On Sat, 04 Jun 2011 10:38:07 -0700, Keith Packard kei...@keithp.com wrote:
On Sat, 4 Jun 2011 09:55:43 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
I'm afraid you've completely lost me here. Can you provide a small
example (libdrm?) program which exhibits the failure so I can follow
.
However as a short-term feature addition, it looks fine.
-Chris
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-gnome and midori-zoomed on
gen3.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h| 21
drivers/gpu/drm/i915/i915_gem.c|7 +-
drivers/gpu
.
Reported-and-tested-by: Sitosfe Wheeler sits...@yahoo.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36326
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: sta...@kernel.org
---
drivers/gpu/drm/i915/i915_dma.c|2 +-
drivers/gpu/drm/i915/i915_drv.h|3
On Mon, 06 Jun 2011 09:03:30 -0700, Keith Packard kei...@keithp.com wrote:
On Mon, 6 Jun 2011 15:18:44 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
case I915_PARAM_HAS_RELAXED_FENCING:
- value = 1;
+ value = 2;
This looks like a change in ABI to me. I
On Mon, 06 Jun 2011 11:09:30 -0700, Keith Packard kei...@keithp.com wrote:
On Mon, 06 Jun 2011 18:50:16 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Hah. Anyway it is actually irrelevant as it turns out, the kernel is broken
with any per-surface tiling on gen2/gen3.
Right, seems
tables be reused by projects external to
mesa?
-Chris
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On Tue, 7 Jun 2011 15:54:40 -0700, Kenneth Graunke kenn...@whitecape.org
wrote:
Ivybridge has BLT and BSD rings, so there's no need to check.
Right, I've been trying to move this code into the ring init...
-Chris
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is applicable to IVB, but as I said it is an ancient
copy.
-Chris
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, so shrink the command and add a trailing nop.
-Chris
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From: Jesper Juhl j...@chaosbits.net
It seems to me that we are leaking 'user_pages' in
drivers/gpu/drm/i915/i915_gem.c::i915_gem_shmem_pread_slow() if
read_cache_page_gfp() fails.
Signed-off-by: Jesper Juhl j...@chaosbits.net
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu
the render or blt ring on gen7, right? That
will be useful to avoid a synchronisation point.
-Chris
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On Mon, 13 Jun 2011 16:00:53 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Yeah, it's just an ugly hack.
Let's also put a default: return -ENODEV in there for future sanity.
-Chris
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mask register addresses the root cause. Out of reset it's h,
so we don't need to read it here.
It would be good to get this into -rc4. -stable probably needs some additional
tweaks.
Signed-off-by: Daniel J Blueman daniel.blue...@gmail.com
Tested-by: Chris Wilson ch...@chris
-ENODEV which both removes lines of code from this complicated routine
and optimises the common case. I agree with him. :)
-Chris
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(dev_priv-ring[BCS], (MI_DISPLAY_FLIP_I915 |
(intel_crtc-plane 19)) | (1 17));
What's the magic number? 80 column limit?
-Chris
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On Wed, 15 Jun 2011 08:08:59 -0700, Eric Anholt e...@anholt.net wrote:
On Wed, 15 Jun 2011 10:39:06 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
For the record, on my SugarBay, this patch on top of drm-intel-fixes and
mesa.git + your instruction streaming, regresses cairo-xlib 4.5s
85345517fe6d4de27b0d6ca19fef9d28ac947c4a
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Sat Nov 13 09:49:11 2010 +
drm/i915: Retire any pending operations on the old scanout when switching
Handles the case were we are changing modes. Unfortunately, disabling an
output takes a different path. Though
messages about a time out are harmless ;)
It's harmless in this case. Just a warning that the new hw driven method
failed and we are now using the old CPU driven method.
-Chris
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with CONFIG_DEBUGFS and at runtime
mount -tdebugfs debug /sys/kernel/debug.
The /sys/kernel/debug/dri/0/i915_error_state will only be populated
after a hang is detected.
-Chris
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On Thu, 16 Jun 2011 16:36:25 -0400, Adam Jackson a...@redhat.com wrote:
This is general TMDS detect, not HDMI specifically.
Signed-off-by: Adam Jackson a...@redhat.com
Reviewed-by: Chris Wilson ch...@chris-wilson.cuk
-Chris
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on another bus, presume that is the correct DDC bus
and keep using that bus for future queries. Otherwise, restore the
original value.
if (edid == NULL)
intel_sdvo-ddc_bus = saved_ddc;
}
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On Thu, 16 Jun 2011 16:36:28 -0400, Adam Jackson a...@redhat.com wrote:
Signed-off-by: Adam Jackson a...@redhat.com
A GMBUS_RATE_MASK would complete the job.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
-Chris
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On Thu, 16 Jun 2011 15:46:29 -0700, Bryce Harrington br...@canonical.com
wrote:
On Thu, Jun 16, 2011 at 12:37:00PM +0100, Chris Wilson wrote:
On Wed, 15 Jun 2011 18:10:29 -0700, Bryce Harrington br...@canonical.com
wrote:
Hi Max,
I currently am tracking 6 bug reports
On Fri, 17 Jun 2011 12:06:54 -0700, Eric Anholt e...@anholt.net wrote:
On Wed, 15 Jun 2011 17:03:58 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Moving back to LLC+semaphores (2.6.39-rc2+), firefox-talos-gfx:
xlib: 4.473
gl: 20.753
applying the patch:
xlib: 4.472
gl
On Sat, 18 Jun 2011 13:20:05 -0700, Eric Anholt e...@anholt.net wrote:
On Sat, 18 Jun 2011 12:43:58 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Fri, 17 Jun 2011 12:06:54 -0700, Eric Anholt e...@anholt.net wrote:
On Wed, 15 Jun 2011 17:03:58 +0100, Chris Wilson
ch...@chris
On Sun, 19 Jun 2011 14:20:14 -0700, Eric Anholt e...@anholt.net wrote:
On Sun, 19 Jun 2011 18:14:11 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Sun, 19 Jun 2011 10:01:23 -0700, Eric Anholt e...@anholt.net wrote:
On Sun, 19 Jun 2011 17:28:11 +0100, Chris Wilson
ch...@chris
.
Fixes the detection of the secondary SDVO LVDS panel on the Libretto
W105.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_sdvo.c | 28
1 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
Poking around in x86,pat I found one way of avoiding the linear walk for
pat_pagerange_is_ram() which appears to nullify the regression. I would
appreciate confirmation and some review before I go poking dragons.
-Chris
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Presuming that we lookup the memtype of an address far more often than
we modify the PAT ranges, favour the reader.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
arch/x86/mm/pat.c | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/x86/mm
resource name, we can reduce this strcmp to a direct
pointer comparison and so eliminate the largest single overhead for
vma_insert_pfn().
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
arch/arm/kernel/setup.c |8
arch/arm/plat-samsung/pm-check.c |2 +-
arch
(spinlock)
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
%%Cc: Robin Holt h...@sgi.com
%%Cc: Suresh Siddha suresh.b.sid...@intel.com
%%Cc: H. Peter Anvin h...@zytor.com
---
arch/x86/mm/pat.c | 24 +---
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/x86
://bugs.freedesktop.org/show_bug.cgi?id=38529
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c |1 +
drivers/gpu/drm/i915/i915_reg.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
switch will
reset it.
-Chris
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. :-p
-Chris
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page on gen3. [The trace currently spends 35% of its time
in clflush which can be entirely eliminated by such tracking.] There's
also the secondary benefit that shmemfs is quite slow for our purposes.
-Chris
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have a single debug message and
not an additional one for every inlined read/write?
-Chris
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On Wed, 22 Jun 2011 10:07:50 -0700, Ben Widawsky bwida...@gmail.com wrote:
On Wed, Jun 22, 2011 at 10:00 AM, Chris Wilson
ch...@chris-wilson.co.ukwrote:
On Wed, 22 Jun 2011 09:55:00 -0700, Ben Widawsky b...@bwidawsk.net wrote:
Get some more useful info for debugging backtraces
. (Not so far fetched, as the user
may be snooping on the results whilst debugging in another process?)
-Chris
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declare it as a
work-in-progress...
I'm not that worried about such just yet, we are a long way from having a
mature enough hw and gfx stack to support a ptrace-like interface for
generic GPU debugging.
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ended up using a very simple UDP reader instead.
-Chris
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to userspace if they try to create a zero length
object.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bceb8ec
10000 - 1800
10500 - 1900
11000 - 2000
I'll give the tyres another kick and see if I can spot any differences.
-Chris
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...
What scenario are you trying to fix?
-Chris
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On Thu, 23 Jun 2011 19:02:32 -0700, Ben Widawsky b...@bwidawsk.net wrote:
On Thu, Jun 23, 2011 at 07:00:50PM -0700, Ben Widawsky wrote:
On Fri, Jun 24, 2011 at 12:45:27AM +0100, Chris Wilson wrote:
On Thu, 23 Jun 2011 16:06:22 -0700, Ben Widawsky b...@bwidawsk.net
wrote:
Signed
, pixmap-per-crtc model
changing depths on the fly is possible and clients can choose to take
advantage of the deep-color support, or not.
So here goes -depth 30...
-Chris
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= dev-dev_private;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+ unsigned int display_bpc = UINT_MAX, fb_bpc, bpc;
+
+ fb_bpc = crtc-fb-depth / 3;
Very misleading. Set but never used.
-Chris
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On Fri, 24 Jun 2011 10:32:16 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
So here goes -depth 30...
So other than a couple of rendering paths where we write 8bpc data into
the depth-30 fb (go flash, go!), X looks good. Textured XVideo should just
work, GLX doesn't advertise a 10-bpc
On Fri, 24 Jun 2011 11:24:08 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Fri, 24 Jun 2011 10:32:16 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
So here goes -depth 30...
So other than a couple of rendering paths where we write 8bpc data into
the depth-30 fb (go flash
. There is a period of time where userspace reads/writes may
occur after the reset, before the GT has been forcewaked. The interface
was never designed to be a perfect solution for userspace reads/writes,
and the kernel portion is fixed by this patch.
Suggested-by: Chris Wilson ch...@chris
On Fri, 24 Jun 2011 08:46:53 -0700, Ben Widawsky b...@bwidawsk.net wrote:
On Fri, Jun 24, 2011 at 12:48:22AM +0100, Chris Wilson wrote:
On Thu, 23 Jun 2011 15:49:14 -0700, Ben Widawsky b...@bwidawsk.net wrote:
Provide a user accessible way to change the hangcheck timer. This is
useful
them there.
;-)
So please give the check for extinction of the timer in hangcheck a whirl.
-Chris
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/x86/kvm/x86.c::kvm_timer_init().
-Chris
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@10x7 nopatch - 3000 - 3300 [tsc_khz]
uncached: 43.2 44.444.8
llc: 51.3 52.3
At max_freq=3000, a cpu busy loop was still able to nudge it up to the
same speed as using the max_freq=3300 value.
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rearrange for the lock to be held for the entire function.
For extra pedagogy, test that we only call init once.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_overlay.c | 17 ++---
1 files changed, 10 insertions(+), 7 deletions(-)
diff --git
the calls
i915_driver_irq_preinstall(ring-dev);
i915_driver_irq_postinstall(ring-dev);
be replaced with
ring-dev-driver-irq_preinstall(ring-dev);
ring-dev-driver-irq_postinstall(ring-dev);
?
Yes.
-Chris
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Konstantin Belousov pointed out that 4697995b98417 replaced the generic
i915_driver_irq_*install() functions with chipset specific routines
accessible only through driver-irq_*install(). So update the sanity
check in i915_request_wait() to match.
Signed-off-by: Chris Wilson ch...@chris
the irq_handlers on the driver vfunc table and so prevent the
possibility of any further confusion like Konstantin pointed out.
-Chris
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into
the init paths for simplicity.
-Chris
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as a predicate function with a separate fixup
routine this would be more useful, but more so is idiomatic programming...
Feel free to supplement the code with more error checking! :)
-Chris
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the
medium setting. Now, the only reference I have is the register dump with
no explanation of what the resource that is actually being controlled...
-Chris
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On Sat, 02 Jul 2011 18:45:39 +0200, Martin Bergström ma...@bredband.net
wrote:
On 2011-07-02 18:08, Chris Wilson wrote:
On Sat, 02 Jul 2011 17:37:39 +0200, Martin Bergström
ma...@bredband.net wrote:
Thought I'd send this to the mailing list before submitting to the
freedesktop.org
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being loaded. Gah.
So I think we can live with it for a while longer. Please do move it out
of the main block and earmark it as being unused.
Also can you mark the parameters as __read_mostly?
-Chris
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Chris Wilson, Intel Open Source Technology Centre
,
I915_READ(ILK_DPFC_CONTROL) | DPFC_CTL_PERSISTENT_MODE);
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 11 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
On Mon, 4 Jul 2011 13:35:57 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Persistent mode is intended for use with front-buffer rendering, such as
X, where it is necessary to detect writes to the scanout either by the
GPU or through the CPU's fence, and recompress the dirty regions
On Wed, 6 Jul 2011 15:14:52 -0700, Ben Widawsky b...@bwidawsk.net wrote:
And programmer hints too. They serve as useful documentation on the
expected usage of the variable as well. But maybe that's just me...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
that could just be one. Can you try
aligning the start of the description with the bracket on a new line?
i.e. set cino=:0,(0
-Chris
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FBC is currently disabled upstream due a few conflicting requirements
and questionable benefit. It is also buggy...
https://bugs.freedesktop.org/show_bug.cgi?id=33487 is the current open
SNB bug where FBC prevents the screen from being redrawn under a
compositing WM. At last it appears that we
, the enablement is cancelled and we are saved from blocking on
the wait.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_display.c | 80 +-
drivers/gpu/drm/i915/intel_drv.h |7 +++
3
As the enable/disable routines will be gain additional complexity in
future patches, it is necessary that all callers do not bypass the
generic interface by calling into the chipset routines directly. to do
this we make the chipset routines static, so there is no choice.
Signed-off-by: Chris
...and this requirement is enforced by intel_update_fbc() so we can
remove the later check from g4x_enable_fbc() and ironlake_enable_fbc().
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 16
1 files changed, 4 insertions(+), 12
of vsync'ed games) and
power (with needless recompression) whilst the page-flipping application
is still running.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33487
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c |2 ++
1 files changed, 2
recompressed after a page-flip.)
References: https://bugs.freedesktop.org/show_bug.cgi?id=33487
References: https://bugs.freedesktop.org/show_bug.cgi?id=31742
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_reg.h |1
The cfb_pitch was only used for 8xx_enable_fbc(), every later routine
was just overwriting the value with itself thanks to a copy'n'paste
error.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c |8 ++--
1 files changed, 2 insertions(+), 6
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