[Intel-gfx] [PATCH] drm/i915/gvt: set ring buffer size to default for guc submission

[Chuanxiao Dong]

When not using GuC submission, the ring buffer size for GVT context is
512KB which is the max size. When switching to GuC submission, the ring
buffer size is required to be less than 16KB. So use the GVT context
default ring buffer size if GuC submission is enabled.

Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index c73bf02..26f0b65 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -431,7 +431,8 @@ i915_gem_context_create_gvt(struct drm_device *dev)
i915_gem_context_set_closed(ctx); /* not user accessible */
i915_gem_context_clear_bannable(ctx);
i915_gem_context_set_force_single_submission(ctx);
-   ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
+   if (!i915.enable_guc_submission)
+   ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
 
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
 out:
-- 
2.7.4

___
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[Intel-gfx] [PATCH v4] drm/i915/scheduler: add gvt notification for guc submission

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

v2: use context_status_change instead of execlists_context_status_change
for better understanding (ZhengXiao)
v3: remove the comment as it is obvious and not friendly to
the caller (Kevin)
v4: fix indent issues (Joonas)
rename the context_status_change to intel_gvt_notify_context_status (Chris)

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 
 drivers/gpu/drm/i915/intel_lrc.c   | 27 ++-
 drivers/gpu/drm/i915/intel_lrc.h   | 14 ++
 3 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 055467a..91a567d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -520,6 +520,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -634,6 +636,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index eec1e71..8b0c937 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,16 +335,16 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
-   INTEL_CONTEXT_SCHEDULE_IN);
+   intel_gvt_notify_context_status(port[0].request,
+   INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
port[0].count++;
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
-   INTEL_CONTEXT_SCHEDULE_IN);
+   intel_gvt_notify_context_status(port[1].request,
+   INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
port[1].count = 1;
@@ -581,8 +566,8 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);

GEM_BUG_ON(!i915_gem_request_completed(port[0].request));
-   execlists_context_status_change(port[0].request,
-   
INTEL_CONTEXT_SCHEDULE_OUT);
+   intel_gvt_notify_context_status(port[0].request,
+   INTEL_CONTEXT_SCHEDULE_OUT);
 
trace_i915_gem_request_out(port[0].request);
i915_gem_request_put(port[0].request);
diff --git a/drivers/gpu/drm/

[Intel-gfx] [PATCH v2 2/2] drm/i915/scheduler: add gvt notification for guc

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 
 drivers/gpu/drm/i915/intel_gvt.h   | 12 
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 58087630..d8a5942 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -725,6 +727,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index c0dcd66..813d0f8 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -38,6 +38,13 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return i915_gem_context_force_single_submission(ctx);
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -51,6 +58,11 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return false;
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 951540f..2333ffb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   intel_gvt_notify_context_status(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -574,7 +559,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED)

[Intel-gfx] [PATCH v2 1/2] drm/i915/scheduler: add gvt force-single-submission for guc

[Chuanxiao Dong]

GVT needs single submission and cannot allow merge. So when GuC submitting
a GVT request, the next one should be submitted to guc later until the
previous one is completed. This is following the usage when using execlist
mode submission.

v2: make force-single-submission specific to gvt (Chris)

Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  7 ++-
 drivers/gpu/drm/i915/intel_gvt.h   | 11 +++
 drivers/gpu/drm/i915/intel_lrc.c   | 25 -
 3 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 991e76e..58087630 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -680,10 +680,15 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
struct drm_i915_gem_request *rq =
rb_entry(rb, typeof(*rq), priotree.node);
 
-   if (last && rq->ctx != last->ctx) {
+   if (last && ((last->ctx != rq->ctx) ||
+   intel_gvt_context_single_port_submit(last->ctx))) {
if (port != engine->execlist_port)
break;
 
+   if (intel_gvt_context_single_port_submit(last->ctx) ||
+   intel_gvt_context_single_port_submit(rq->ctx))
+   break;
+
i915_gem_request_assign(>request, last);
nested_enable_signaling(last);
port++;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..c0dcd66 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,12 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return i915_gem_context_force_single_submission(ctx);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +46,11 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return false;
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dd0e9d587..951540f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -377,24 +377,6 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
writel(lower_32_bits(desc[0]), elsp);
 }
 
-static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
-{
-   return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
-   i915_gem_context_force_single_submission(ctx));
-}
-
-static bool can_merge_ctx(const struct i915_gem_context *prev,
- const struct i915_gem_context *next)
-{
-   if (prev != next)
-   return false;
-
-   if (ctx_single_port_submission(prev))
-   return false;
-
-   return true;
-}
-
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *last;
@@ -462,7 +444,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * request, and so we never need to tell the hardware about
 * the first.
 */
-   if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
+   if (last && ((last->ctx != cursor->ctx) ||
+   intel_gvt_context_single_port_submit(last->ctx))) {
/* If we are on the second port and cannot combine
 * this request with the last, then we are done.
 */
@@ -475,8 +458,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * context (even though a different request) to
 * the second port.
 */
-   if (ctx_single_port_submission(last->ctx) ||
-   ctx_single_port_submission(cursor->ctx))
+   if (intel_gvt_context_single_port_submit(last->ctx) ||
+   intel_gvt_context_single_port_submit(cursor->ctx))
break;
 
GEM_BUG_ON(last->ctx == cursor->ctx);
-- 
2.7.4

__

[Intel-gfx] [PATCH v2 0/2] drm/i915/scheduler: add gvt force-single-submission and notification for guc

[Chuanxiao Dong]

GVT requires force-single-submission and notification when i915
using execlist submit, and these should be extended to GuC when
i915 using GuC submit. Below two patches are used to implement this

Chuanxiao Dong (2):
  drm/i915/scheduler: add gvt force-single-submission for guc
  drm/i915/scheduler: add gvt notification for guc

 drivers/gpu/drm/i915/i915_guc_submission.c | 11 ++-
 drivers/gpu/drm/i915/intel_gvt.h   | 23 +++
 drivers/gpu/drm/i915/intel_lrc.c   | 46 +-
 3 files changed, 40 insertions(+), 40 deletions(-)

-- 
2.7.4

___
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[Intel-gfx] [PATCH 1/2] drm/i915/scheduler: add gvt force-single-submission for guc

[Chuanxiao Dong]

GVT needs single submission and cannot allow merge. So when GuC submitting
a GVT request, the next one should be submitted to guc later until the
previous one is completed. This is following the usage when using execlist
mode submission.

Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.h| 20 
 drivers/gpu/drm/i915/i915_guc_submission.c |  6 +-
 drivers/gpu/drm/i915/intel_lrc.c   | 25 -
 3 files changed, 29 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94..025eba2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -246,6 +246,26 @@ static inline bool i915_gem_context_is_kernel(struct 
i915_gem_context *ctx)
return !ctx->file_priv;
 }
 
+static inline bool
+i915_gem_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
+   i915_gem_context_force_single_submission(ctx));
+}
+
+static inline bool
+i915_gem_context_can_merge(const struct i915_gem_context *prev,
+   const struct i915_gem_context *next)
+{
+   if (prev != next)
+   return false;
+
+   if (i915_gem_context_single_port_submit(prev))
+   return false;
+
+   return true;
+}
+
 /* i915_gem_context.c */
 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 991e76e..ad90de1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -680,10 +680,14 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
struct drm_i915_gem_request *rq =
rb_entry(rb, typeof(*rq), priotree.node);
 
-   if (last && rq->ctx != last->ctx) {
+   if (last && !i915_gem_context_can_merge(last->ctx, rq->ctx)) {
if (port != engine->execlist_port)
break;
 
+   if (i915_gem_context_single_port_submit(last->ctx) ||
+   i915_gem_context_single_port_submit(rq->ctx))
+   break;
+
i915_gem_request_assign(>request, last);
nested_enable_signaling(last);
port++;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dd0e9d587..a49801e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -377,24 +377,6 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
writel(lower_32_bits(desc[0]), elsp);
 }
 
-static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
-{
-   return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
-   i915_gem_context_force_single_submission(ctx));
-}
-
-static bool can_merge_ctx(const struct i915_gem_context *prev,
- const struct i915_gem_context *next)
-{
-   if (prev != next)
-   return false;
-
-   if (ctx_single_port_submission(prev))
-   return false;
-
-   return true;
-}
-
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *last;
@@ -462,7 +444,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * request, and so we never need to tell the hardware about
 * the first.
 */
-   if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
+   if (last &&
+   !i915_gem_context_can_merge(last->ctx, cursor->ctx)) {
/* If we are on the second port and cannot combine
 * this request with the last, then we are done.
 */
@@ -475,8 +458,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * context (even though a different request) to
 * the second port.
 */
-   if (ctx_single_port_submission(last->ctx) ||
-   ctx_single_port_submission(cursor->ctx))
+   if (i915_gem_context_single_port_submit(last->ctx) ||
+   i915_gem_context_single_port_submit(cursor->ctx))
break;
 
GEM_BUG_ON(last->ctx == cursor->ctx);
-- 
2.7.4

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 0/2] drm/i915/scheduler: add gvt force-single-submission and notification for guc

[Chuanxiao Dong]

GVT requires force-single-submission and notification when i915
using execlist submit, and these should be extended to GuC when
i915 using GuC submit. Below two patches are used to implement this

Chuanxiao Dong (2):
  drm/i915/scheduler: add gvt force-single-submission for guc
  drm/i915/scheduler: add gvt notification for guc

 drivers/gpu/drm/i915/i915_gem_context.h| 20 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 10 ++-
 drivers/gpu/drm/i915/intel_gvt.h   | 13 +
 drivers/gpu/drm/i915/intel_lrc.c   | 46 +-
 4 files changed, 49 insertions(+), 40 deletions(-)

-- 
2.7.4

___
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[Intel-gfx] [PATCH 2/2] drm/i915/scheduler: add gvt notification for guc

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 
 drivers/gpu/drm/i915/intel_gvt.h   | 13 +
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 3 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ad90de1..a1e83e6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -724,6 +726,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..9175018 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,14 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +48,11 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a49801e..dd9bd7a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   intel_gvt_notify_context_status(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -574,7 +559,7 @@ static void intel_lrc_irq_handler(unsigned long data)
   

[Intel-gfx] [PATCH v5] drm/i915/scheduler: add gvt notification for guc submission

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

v2: use context_status_change instead of execlists_context_status_change
for better understanding (ZhengXiao)
v3: remove the comment as it is obvious and not friendly to
the caller (Kevin)
v4: fix indent issues (Joonas)
rename the context_status_change to intel_gvt_notify_context_status (Chris)
v5: move intel_gvt_notify_context_status to intel_gvt.h (Joonas)

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 
 drivers/gpu/drm/i915/intel_gvt.h   | 13 +
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 3 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 991e76e..1223169 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -720,6 +722,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..9175018 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,14 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +48,11 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dd0e9d587..8708515 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+  

[Intel-gfx] [PATCH] drm/i915/scheduler: add gvt notification for guc submission

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 13 +
 drivers/gpu/drm/i915/intel_lrc.c   | 15 ---
 drivers/gpu/drm/i915/intel_lrc.h   | 14 ++
 3 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a3636b3..328b11c 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -520,6 +520,12 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   /* Notify for the context status change schedule in
+* Currently only GVT care this notification for manually
+* context switch, like when using execlist mode submission
+*/
+   execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -623,6 +629,13 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   /* Notify for the context status change schedule
+* out. Currently only GVT care this notification
+* for manually context switch, like when using
+* execlist mode submission
+*/
+   execlists_context_status_change(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index becde55..4f5906b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..d3aa108 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -87,5 +87,19 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context 
*ctx,
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
int enable_execlists);
+static inline void
+execlists_context_status_change(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   /*
+* Only used when GVT-g is enabled now. When GVT-g is disabled,
+* The compiler should eliminate this function as dead-code.
+*/
+   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+   return;
+
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 
 #endif /* _INTEL_LRC_H_ */
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915/scheduler: add gvt notification for guc submission

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

v2: use context_status_change instead of execlists_context_status_change
for better understanding (ZhengXiao)

Cc: xiao.zh...@intel.com
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 12 
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 drivers/gpu/drm/i915/intel_lrc.h   | 13 +
 3 files changed, 28 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a3636b3..68c1e70 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -520,6 +520,12 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   /* Notify for the context status change schedule in
+* Currently only GVT care this notification for manually
+* context switch, like when using execlist mode submission
+*/
+   context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -623,6 +629,12 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   /* Notify for the context status change schedule
+* out. Currently only GVT care this notification
+* for manually context switch, like when using
+* execlist mode submission
+*/
+   context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index becde55..3a5ed5c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   context_status_change(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   context_status_change(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -565,7 +550,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);

GEM_BUG_ON(!i915_gem_request_completed(port[0].request));
-   execlists_context_status_change(port[0].request,
+   context_status_change(port[0].request,

INTEL_CONTEXT_SCHEDULE_OUT);
 
trace_i915_gem_request_out(port[0].request);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..51e1be9 100644
--- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3] drm/i915/scheduler: add gvt notification for guc submission

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

v2: use context_status_change instead of execlists_context_status_change
for better understanding (ZhengXiao)
v3: remove the comment as it is obvious and not friendly to
the caller (Kevin)

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 drivers/gpu/drm/i915/intel_lrc.h   | 13 +
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 055467a..0195547 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -520,6 +520,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -634,6 +636,7 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index eec1e71..24c69b5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   context_status_change(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   context_status_change(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -581,7 +566,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);

GEM_BUG_ON(!i915_gem_request_completed(port[0].request));
-   execlists_context_status_change(port[0].request,
+   context_status_change(port[0].request,

INTEL_CONTEXT_SCHEDULE_OUT);
 
trace_i915_gem_request_out(port[0].request);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..51e1be9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -87,5 +87,18 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context 
*ctx,
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
int enable_execlists);
+static inline void
+context_status_change(struct drm_i915_gem_request *rq, unsigned long status)
+{
+   /*
+* On

[Intel-gfx] [PATCH v3 2/2] drm/i915/scheduler: add gvt notification for guc

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 
 drivers/gpu/drm/i915/intel_gvt.h   | 12 
 drivers/gpu/drm/i915/intel_lrc.c   | 21 +++--
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 862f4fd..2f3bb16 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -712,6 +714,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index c0dcd66..813d0f8 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -38,6 +38,13 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return i915_gem_context_force_single_submission(ctx);
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -51,6 +58,11 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return false;
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 61291e9..81f9a3b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   intel_gvt_notify_context_status(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -560,7 +545,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED)

[Intel-gfx] [PATCH v3 1/2] drm/i915/scheduler: add gvt force-single-submission for guc

[Chuanxiao Dong]

GVT needs single submission and cannot allow merge. So when GuC submitting
a GVT request, the next one should be submitted to guc later until the
previous one is completed. This is following the usage when using execlist
mode submission.

v2: make force-single-submission specific to gvt (Chris)
v3: keep the original code implementation (Chris)

Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.h| 13 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  6 +-
 drivers/gpu/drm/i915/intel_gvt.h   | 11 +++
 drivers/gpu/drm/i915/intel_lrc.c   | 25 -
 4 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94..2c3afec 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -246,6 +246,19 @@ static inline bool i915_gem_context_is_kernel(struct 
i915_gem_context *ctx)
return !ctx->file_priv;
 }
 
+static inline bool
+i915_gem_context_can_merge(const struct i915_gem_context *prev,
+   const struct i915_gem_context *next)
+{
+   if (prev != next)
+   return false;
+
+   if (i915_gem_context_force_single_submission(prev))
+   return false;
+
+   return true;
+}
+
 /* i915_gem_context.c */
 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 1642fff..862f4fd 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -668,10 +668,14 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
struct drm_i915_gem_request *rq =
rb_entry(rb, typeof(*rq), priotree.node);
 
-   if (last && rq->ctx != last->ctx) {
+   if (last && !i915_gem_context_can_merge(last->ctx, rq->ctx)) {
if (port != engine->execlist_port)
break;
 
+   if (intel_gvt_context_single_port_submit(last->ctx) ||
+   intel_gvt_context_single_port_submit(rq->ctx))
+   break;
+
i915_gem_request_assign(>request, last);
nested_enable_signaling(last);
port++;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..c0dcd66 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,12 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return i915_gem_context_force_single_submission(ctx);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +46,11 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return false;
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..61291e9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -377,24 +377,6 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
writel(lower_32_bits(desc[0]), elsp);
 }
 
-static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
-{
-   return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
-   i915_gem_context_force_single_submission(ctx));
-}
-
-static bool can_merge_ctx(const struct i915_gem_context *prev,
- const struct i915_gem_context *next)
-{
-   if (prev != next)
-   return false;
-
-   if (ctx_single_port_submission(prev))
-   return false;
-
-   return true;
-}
-
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *last;
@@ -450,7 +432,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * request, and so we never need to tell the hardware about
 * the first.
 */
-   if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
+   if (last &&
+   !i915_gem_context_can_merge(last->ctx, cursor-&

[Intel-gfx] [PATCH v3 0/2] drm/i915/scheduler: add gvt force-single-submission and notification for guc

[Chuanxiao Dong]

GVT requires force-single-submission and notification when i915
using execlist submit, and these should be extended to GuC when
i915 using GuC submit. Below two patches are used to implement this

Chuanxiao Dong (2):
  drm/i915/scheduler: add gvt force-single-submission for guc
  drm/i915/scheduler: add gvt notification for guc

 drivers/gpu/drm/i915/i915_gem_context.h| 13 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 10 ++-
 drivers/gpu/drm/i915/intel_gvt.h   | 23 +++
 drivers/gpu/drm/i915/intel_lrc.c   | 46 +-
 4 files changed, 52 insertions(+), 40 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 3/4] drm/i915/scheduler: add gvt force-single-submission for guc

[Chuanxiao Dong]

GVT needs single submission and cannot allow merge. So when GuC submitting
a GVT request, the next one should be submitted to guc later until the
previous one is completed. This is following the usage when using execlist
mode submission.

Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 1642fff..862f4fd 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -668,10 +668,14 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
struct drm_i915_gem_request *rq =
rb_entry(rb, typeof(*rq), priotree.node);
 
-   if (last && rq->ctx != last->ctx) {
+   if (last && !i915_gem_context_can_merge(last->ctx, rq->ctx)) {
if (port != engine->execlist_port)
break;
 
+   if (intel_gvt_context_single_port_submit(last->ctx) ||
+   intel_gvt_context_single_port_submit(rq->ctx))
+   break;
+
i915_gem_request_assign(>request, last);
nested_enable_signaling(last);
port++;
-- 
2.7.4

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[Intel-gfx] [PATCH 4/4] drm/i915/scheduler: add gvt notification for guc

[Chuanxiao Dong]

GVT request needs a manual mmio load/restore. Before GuC submit
a request, send notification to gvt for mmio loading. And after
the GuC finished this GVT request, notify gvt again for mmio
restore. This follows the usage when using execlists submission.

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 862f4fd..2f3bb16 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -606,6 +606,8 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned long flags;
int b_ret;
 
+   intel_gvt_notify_context_status(rq, INTEL_CONTEXT_SCHEDULE_IN);
+
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
@@ -712,6 +714,8 @@ static void i915_guc_irq_handler(unsigned long data)
rq = port[0].request;
while (rq && i915_gem_request_completed(rq)) {
trace_i915_gem_request_out(rq);
+   intel_gvt_notify_context_status(rq,
+   INTEL_CONTEXT_SCHEDULE_OUT);
i915_gem_request_put(rq);
port[0].request = port[1].request;
port[1].request = NULL;
-- 
2.7.4

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[Intel-gfx] [PATCH 2/4] drm/i915: refactor gvt context notification

[Chuanxiao Dong]

refactor gvt context notification to proper files

v1:
use context_status_change instead of execlists_context_status_change
for better understanding(ZhengXiao)
remove the comment as it is obvious and not friendly to the caller(Kevin)
fix indent issues(Joonas)
rename the context_status_change to intel_gvt_notify_context_status(Chris)
move intel_gvt_notify_context_status to intel_gvt.h(Joonas)

Cc: xiao.zh...@intel.com
Cc: kevin.t...@intel.com
Cc: joonas.lahti...@linux.intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.h | 12 
 drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index c0dcd66..813d0f8 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -38,6 +38,13 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return i915_gem_context_force_single_submission(ctx);
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   atomic_notifier_call_chain(>engine->context_status_notifier,
+  status, rq);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -51,6 +58,11 @@ intel_gvt_context_single_port_submit(const struct 
i915_gem_context *ctx)
 {
return false;
 }
+static inline void
+intel_gvt_notify_context_status(struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 61291e9..81f9a3b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -295,21 +295,6 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
-static inline void
-execlists_context_status_change(struct drm_i915_gem_request *rq,
-   unsigned long status)
-{
-   /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
-   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
-   return;
-
-   atomic_notifier_call_chain(>engine->context_status_notifier,
-  status, rq);
-}
-
 static void
 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 {
@@ -350,7 +335,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
GEM_BUG_ON(port[0].count > 1);
if (!port[0].count)
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[0] = execlists_update_context(port[0].request);
GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
@@ -358,7 +343,7 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
 
if (port[1].request) {
GEM_BUG_ON(port[1].count);
-   execlists_context_status_change(port[1].request,
+   intel_gvt_notify_context_status(port[1].request,
INTEL_CONTEXT_SCHEDULE_IN);
desc[1] = execlists_update_context(port[1].request);
GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
@@ -560,7 +545,7 @@ static void intel_lrc_irq_handler(unsigned long data)
if (--port[0].count == 0) {
GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);

GEM_BUG_ON(!i915_gem_request_completed(port[0].request));
-   execlists_context_status_change(port[0].request,
+   intel_gvt_notify_context_status(port[0].request,

INTEL_CONTEXT_SCHEDULE_OUT);
 
trace_i915_gem_request_out(port[0].request);
-- 
2.7.4

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[Intel-gfx] [PATCH 1/4] drm/i915: refactor gvt force-single-submission

[Chuanxiao Dong]

refactor gvt force-single-submission to proper files

v1:
make force-single-submission specific to gvt (Chris)
keep the original code implementation (Chris)

Cc: ch...@chris-wilson.co.uk
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.h | 13 +
 drivers/gpu/drm/i915/intel_gvt.h| 11 +++
 drivers/gpu/drm/i915/intel_lrc.c| 25 -
 3 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94..2c3afec 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -246,6 +246,19 @@ static inline bool i915_gem_context_is_kernel(struct 
i915_gem_context *ctx)
return !ctx->file_priv;
 }
 
+static inline bool
+i915_gem_context_can_merge(const struct i915_gem_context *prev,
+   const struct i915_gem_context *next)
+{
+   if (prev != next)
+   return false;
+
+   if (i915_gem_context_force_single_submission(prev))
+   return false;
+
+   return true;
+}
+
 /* i915_gem_context.c */
 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..c0dcd66 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,12 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return i915_gem_context_force_single_submission(ctx);
+}
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +46,11 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+static inline bool
+intel_gvt_context_single_port_submit(const struct i915_gem_context *ctx)
+{
+   return false;
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..61291e9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -377,24 +377,6 @@ static void execlists_submit_ports(struct intel_engine_cs 
*engine)
writel(lower_32_bits(desc[0]), elsp);
 }
 
-static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
-{
-   return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
-   i915_gem_context_force_single_submission(ctx));
-}
-
-static bool can_merge_ctx(const struct i915_gem_context *prev,
- const struct i915_gem_context *next)
-{
-   if (prev != next)
-   return false;
-
-   if (ctx_single_port_submission(prev))
-   return false;
-
-   return true;
-}
-
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *last;
@@ -450,7 +432,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * request, and so we never need to tell the hardware about
 * the first.
 */
-   if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
+   if (last &&
+   !i915_gem_context_can_merge(last->ctx, cursor->ctx)) {
/* If we are on the second port and cannot combine
 * this request with the last, then we are done.
 */
@@ -463,8 +446,8 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * context (even though a different request) to
 * the second port.
 */
-   if (ctx_single_port_submission(last->ctx) ||
-   ctx_single_port_submission(cursor->ctx))
+   if (intel_gvt_context_single_port_submit(last->ctx) ||
+   intel_gvt_context_single_port_submit(cursor->ctx))
break;
 
GEM_BUG_ON(last->ctx == cursor->ctx);
-- 
2.7.4

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[Intel-gfx] [PATCH v2] drm/i915/gvt: add enable_execlists check before enable gvt

[Chuanxiao Dong]

The GVT-g needs execlists to be enabled otherwise gvt should be
disabled. Add a check for enable_execlists before enabling gvt.

v2: use DRM_INFO in response to the user action

Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index d23c0fc..8c04eca 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -77,6 +77,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
goto bail;
}
 
+   if (!i915.enable_execlists) {
+   DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
disabled execlist submission [i915.enable_execlists module parameter]\n");
+   goto bail;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915/gvt: add enable_execlists check before enable gvt

[Chuanxiao Dong]

The GVT-g needs execlists to be enabled otherwise gvt should be
disabled. Add a check for enable_execlists before enabling gvt.

Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index d23c0fc..3799cb3 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -77,6 +77,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
goto bail;
}
 
+   if (!i915.enable_execlists) {
+   DRM_DEBUG_DRIVER("Execlists unsupported, GVT-g is disabled\n");
+   goto bail;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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[Intel-gfx] [PATCH v2] drm/i915: Fix the kernel panic when using aliasing ppgtt

[Chuanxiao Dong]

The ppgtt should be get directly from i915_address_space *vm instead of
vma->vm.

v2:
- add one more fix for bxt. (Chris)

Fixes: 4a234c5fae16 ("drm/i915: pass the vma to insert_entries")
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=101713
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
Reviewed-by: Matthew Auld <matthew.a...@intel.com> v1
Cc: Matthew Auld <matthew.a...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhen...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index de67084..10aa776 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -910,7 +910,7 @@ static void gen8_ppgtt_insert_3lvl(struct 
i915_address_space *vm,
   enum i915_cache_level cache_level,
   u32 unused)
 {
-   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
+   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = {
.sg = vma->pages->sgl,
.dma = sg_dma_address(iter.sg),
@@ -2242,7 +2242,7 @@ static void bxt_vtd_ggtt_insert_entries__BKL(struct 
i915_address_space *vm,
 enum i915_cache_level level,
 u32 unused)
 {
-   struct insert_entries arg = { vma->vm, vma, level };
+   struct insert_entries arg = { vm, vma, level };
 
stop_machine(bxt_vtd_ggtt_insert_entries__cb, , NULL);
 }
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915: Fix the port submission race during engine reset in execlists mode

[Chuanxiao Dong]

During the engine reset, there is a race condition which can make the
request submitted to HW twice. This is due to the irq tasklet function
enabled too earliy which is just before init_hw callback. This patch
will move the irq tasklet enabling after init_hw to resolve this race.

Fixes: a1ef70e14453 ("drm/i915: Add support for per engine reset recovery")
Cc: Michel Thierry <michel.thie...@intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d310d82..e2f0222 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1963,9 +1963,6 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 
/* Finally, reset just this engine. */
ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
-
-   i915_gem_reset_finish_engine(engine);
-
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
@@ -1984,6 +1981,8 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 
error->reset_engine_count[engine->id]++;
 out:
+   i915_gem_reset_finish_engine(engine);
+
return ret;
 }
 
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915: Fix the kernel panic when using aliasing ppgtt

[Chuanxiao Dong]

The ppgtt should be get directly from i915_address_space *vm instead of
vma->vm as in alias ppgtt case the vma->vm is not same with vm.

Fixes: 4a234c5fae16 ("drm/i915: pass the vma to insert_entries")
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=101713
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
Cc: Matthew Auld <matthew.a...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhen...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index de67084..867dcdc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -910,7 +910,7 @@ static void gen8_ppgtt_insert_3lvl(struct 
i915_address_space *vm,
   enum i915_cache_level cache_level,
   u32 unused)
 {
-   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
+   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = {
.sg = vma->pages->sgl,
.dma = sg_dma_address(iter.sg),
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915: set initialised only when init_context callback is NULL

[Chuanxiao Dong]

initialised is fixup by the GVT shadow context as true to avoid the init
from the host because it cannot take the settings from the host. Add a
check to let host driver only overwrite it when the init callback is NULL

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 319d9a8..d0e9b61 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1956,7 +1956,8 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
 
ce->ring = ring;
ce->state = vma;
-   ce->initialised = engine->init_context == NULL;
+   if (!engine->init_context)
+   ce->initialised = true;
 
return 0;
 
-- 
2.7.4

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[Intel-gfx] [PATCH v2] drm/i915/gvt: disable GVT-g if host GuC submission is enabled

[Chuanxiao Dong]

Currently GVT-g cannot work properly when host GuC submission
is enabled, so disable GVT in this case.

v2: update the user message (Joonas)

Cc: Zhenyu Wang <zhen...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index e1ab643..d85742c 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -84,6 +84,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
goto bail;
}
 
+   if (i915.enable_guc_submission) {
+   DRM_INFO("GPU guest virtualisation [GVT-g] disabled as Graphics 
virtualization is not yet supported with GuC submission 
[i915.enable_guc_submission module parameter]\n");
+   goto bail;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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[Intel-gfx] [PATCH v2 1/3] drm/i915/gvt: Add gvt options sanitize function

[Chuanxiao Dong]

The intel_gvt_sanitize_options will sanitize the GVT related
options before doing initialize the GVT.

Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c  |  2 ++
 drivers/gpu/drm/i915/intel_gvt.c | 36 ++--
 drivers/gpu/drm/i915/intel_gvt.h |  5 +
 3 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72fb47a..9c59b22 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -997,6 +997,8 @@ static void intel_sanitize_options(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
 
intel_uc_sanitize_options(dev_priv);
+
+   intel_gvt_sanitize_options(dev_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index e1ab643..dde9c78 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -51,6 +51,32 @@ static bool is_supported_device(struct drm_i915_private 
*dev_priv)
 }
 
 /**
+ * intel_gvt_sanitize_options - sanitize GVT related options
+ * @dev_priv: drm i915 private data
+ *
+ * This function is called at the i915 options sanitize stage.
+ */
+void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
+{
+   if (!i915.enable_gvt)
+   return;
+
+   if (intel_vgpu_active(dev_priv)) {
+   DRM_INFO("GVT-g is disabled for guest\n");
+   goto bail;
+   }
+
+   if (!is_supported_device(dev_priv)) {
+   DRM_INFO("Unsupported device. GVT-g is disabled\n");
+   goto bail;
+   }
+
+   return;
+bail:
+   i915.enable_gvt = 0;
+}
+
+/**
  * intel_gvt_init - initialize GVT components
  * @dev_priv: drm i915 private data
  *
@@ -69,16 +95,6 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
 
-   if (intel_vgpu_active(dev_priv)) {
-   DRM_DEBUG_DRIVER("GVT-g is disabled for guest\n");
-   goto bail;
-   }
-
-   if (!is_supported_device(dev_priv)) {
-   DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
-   goto bail;
-   }
-
if (!i915.enable_execlists) {
DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
disabled execlist submission [i915.enable_execlists module parameter]\n");
goto bail;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..61b2464 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,7 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +41,10 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+
+static inline void intel_gvt_sanitize_options(struct drm_i915_private 
*dev_priv)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
-- 
2.7.4

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[Intel-gfx] [PATCH v2 3/3] drm/i915/gvt: Return -EIO if host GuC submission is enabled when loading GVT-g

[Chuanxiao Dong]

Currently GVT-g cannot work properly when host GuC submission is
enabled, so make the driver loading failed in this case.

v2:
- use DRM_ERROR as it is a fatal message. (Chris)

Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhen...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index e2a3f0a..52d5b82 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -100,6 +100,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
 
+   if (i915.enable_guc_submission) {
+   DRM_ERROR("i915 GVT-g loading failed due to Graphics 
virtualization is not yet supported with GuC submission\n");
+   return -EIO;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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[Intel-gfx] [PATCH v2 2/3] drm/i915/gvt: Return -EIO if host enable_execlists not enabled when loading GVT-g

[Chuanxiao Dong]

GVT-g relies on the enable_execlists parameter in i915. If this option
is not enabled for GVT-g, should return -EIO to make i915 driver loading
failed.

v2:
- Use DMR_ERROR as it is a fatal message. (Chris)

Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index dde9c78..e2a3f0a 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -96,8 +96,8 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
}
 
if (!i915.enable_execlists) {
-   DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
disabled execlist submission [i915.enable_execlists module parameter]\n");
-   goto bail;
+   DRM_ERROR("i915 GVT-g loading failed due to disabled execlists 
mode\n");
+   return -EIO;
}
 
/*
-- 
2.7.4

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[Intel-gfx] [PATCH v2 0/3] drm/i915/gvt: GVT-g options sanitize series

[Chuanxiao Dong]

In this series, options sanitize API is added for GVT-g, and GVT-g init
will fail with -EIO if detected incompatible i915 parameters.

Chuanxiao Dong (3):
  drm/i915/gvt: Add gvt options sanitize function
  drm/i915/gvt: Return -EIO if host enable_execlists not enabled when
loading GVT-g
  drm/i915/gvt: Return -EIO if host GuC submission is enabled when
loading GVT-g

 drivers/gpu/drm/i915/i915_drv.c  |  2 ++
 drivers/gpu/drm/i915/intel_gvt.c | 43 ++--
 drivers/gpu/drm/i915/intel_gvt.h |  5 +
 3 files changed, 39 insertions(+), 11 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 0/3] drm/i915/gvt: GVT-g options sanitize series

[Chuanxiao Dong]

In this series, options sanitize API is added for GVT-g, and GVT-g init
will fail with -EIO if detected incompatible i915 parameters.

Chuanxiao Dong (3):
  drm/i915/gvt: Add gvt options sanitize function
  drm/i915/gvt: Return -EIO if host enable_execlists not enabled when
loading GVT-g
  drm/i915/gvt: Return -EIO if host GuC submission is enabled when
loading GVT-g

 drivers/gpu/drm/i915/i915_drv.c  |  2 ++
 drivers/gpu/drm/i915/intel_gvt.c | 43 ++--
 drivers/gpu/drm/i915/intel_gvt.h |  5 +
 3 files changed, 39 insertions(+), 11 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 3/3] drm/i915/gvt: Return -EIO if host GuC submission is enabled when loading GVT-g

[Chuanxiao Dong]

Currently GVT-g cannot work properly when host GuC submission is
enabled, so make i915 driver loading failed in this case.

Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhen...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index c90d476..63bff89 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -100,6 +100,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
 
+   if (i915.enable_guc_submission) {
+   DRM_INFO("Graphics virtualization is not yet supported with GuC 
submission");
+   return -EIO;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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[Intel-gfx] [PATCH 1/3] drm/i915/gvt: Add gvt options sanitize function

[Chuanxiao Dong]

The intel_gvt_sanitize_options will sanitize the GVT-g related
options before doing GVT-g init.

Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c  |  2 ++
 drivers/gpu/drm/i915/intel_gvt.c | 36 ++--
 drivers/gpu/drm/i915/intel_gvt.h |  5 +
 3 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72fb47a..9c59b22 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -997,6 +997,8 @@ static void intel_sanitize_options(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
 
intel_uc_sanitize_options(dev_priv);
+
+   intel_gvt_sanitize_options(dev_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index e1ab643..dde9c78 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -51,6 +51,32 @@ static bool is_supported_device(struct drm_i915_private 
*dev_priv)
 }
 
 /**
+ * intel_gvt_sanitize_options - sanitize GVT related options
+ * @dev_priv: drm i915 private data
+ *
+ * This function is called at the i915 options sanitize stage.
+ */
+void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
+{
+   if (!i915.enable_gvt)
+   return;
+
+   if (intel_vgpu_active(dev_priv)) {
+   DRM_INFO("GVT-g is disabled for guest\n");
+   goto bail;
+   }
+
+   if (!is_supported_device(dev_priv)) {
+   DRM_INFO("Unsupported device. GVT-g is disabled\n");
+   goto bail;
+   }
+
+   return;
+bail:
+   i915.enable_gvt = 0;
+}
+
+/**
  * intel_gvt_init - initialize GVT components
  * @dev_priv: drm i915 private data
  *
@@ -69,16 +95,6 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
 
-   if (intel_vgpu_active(dev_priv)) {
-   DRM_DEBUG_DRIVER("GVT-g is disabled for guest\n");
-   goto bail;
-   }
-
-   if (!is_supported_device(dev_priv)) {
-   DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
-   goto bail;
-   }
-
if (!i915.enable_execlists) {
DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
disabled execlist submission [i915.enable_execlists module parameter]\n");
goto bail;
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 25df2d6..61b2464 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -32,6 +32,7 @@ void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
 int intel_gvt_init_device(struct drm_i915_private *dev_priv);
 void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
 int intel_gvt_init_host(void);
+void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
 #else
 static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
@@ -40,6 +41,10 @@ static inline int intel_gvt_init(struct drm_i915_private 
*dev_priv)
 static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
 {
 }
+
+static inline void intel_gvt_sanitize_options(struct drm_i915_private 
*dev_priv)
+{
+}
 #endif
 
 #endif /* _INTEL_GVT_H_ */
-- 
2.7.4

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[Intel-gfx] [PATCH 2/3] drm/i915/gvt: Return -EIO if host enable_execlists not enabled when loading GVT-g

[Chuanxiao Dong]

GVT-g relies on the enable_execlists parameter in i915. If this option
is not enabled for GVT-g, should return -EIO to make i915 driver loading
failed.

Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index dde9c78..c90d476 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -97,7 +97,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
 
if (!i915.enable_execlists) {
DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
disabled execlist submission [i915.enable_execlists module parameter]\n");
-   goto bail;
+   return -EIO;
}
 
/*
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915/gvt: disable GVT-g if host GuC submission is enabled

[Chuanxiao Dong]

Currently GVT-g cannot work properly when host GuC submission
is enabled, so disable GVT in this case.

Cc: Zhenyu Wang <zhen...@linux.intel.com>
Signed-off-by: Chuanxiao Dong <chuanxiao.d...@intel.com>
---
 drivers/gpu/drm/i915/intel_gvt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index e1ab643..0e1ff48 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -84,6 +84,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
goto bail;
}
 
+   if (i915.enable_guc_submission) {
+   DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to 
enabled GuC submission [i915.enable_guc_submission module parameter]\n");
+   goto bail;
+   }
+
/*
 * We're not in host or fail to find a MPT module, disable GVT-g
 */
-- 
2.7.4

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