On 6/2/2021 9:20 AM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:59PM -0700, Daniele Ceraolo Spurio wrote:
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
session state migh
On 6/2/2021 11:14 AM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:58PM -0700, Daniele Ceraolo Spurio wrote:
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it
that right now, the default is for everything to be off
anyway. So this is not a change for current platforms.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Double checked the CI results and the 2 errors are unrelated.
Pushed to gt-next
#endif /* _ABI_GUC_COMMUNICATION_MMIO_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index f147cb389a20..b773567cb080 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -376,29 +376,27 @@
On 6/7/2021 11:03 AM, Matthew Brost wrote:
From: Michal Wajdeczko
Format of the CTB messages has changed:
- support for multiple formats
- message fence is now part of the header
- reuse of unified HXG message formats
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: P
On 6/7/2021 11:03 AM, Matthew Brost wrote:
From: Michal Wajdeczko
Definition of the CTB registration action has changed.
Add some ABI documentation and implement required changes.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Cc: Piotr Piórkowski #4
---
.../gpu/drm/i915/g
On 6/7/2021 11:03 AM, Matthew Brost wrote:
From: Michal Wajdeczko
Definition of the CTB descriptor has changed, leaving only
minimal shared fields like HEAD/TAIL/STATUS.
Both HEAD and TAIL are now in dwords.
Add some ABI documentation and implement required changes.
Signed-off-by: Michal
there are larger changes to the CTB flows which AFAICS are part of patch
8. If what you wanted to do here was a simple replacement of defines to
keep the later patch simpler, then, considering all patches are going to
be squashed anyway:
Reviewed-by: Daniele Ceraolo Spurio
One suggestion below
On 6/7/2021 11:03 AM, Matthew Brost wrote:
From: Michal Wajdeczko
The MMIO based Host-to-GuC communication protocol has been
updated to use unified HXG messages.
Update our intel_guc_send_mmio() function by correctly handle
BUSY, RETRY and FAILURE replies. Also update our documentation.
GuC
On 6/7/2021 11:03 AM, Matthew Brost wrote:
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc:
On 6/7/2021 11:03 AM, Matthew Brost wrote:
As part of enabling GuC submission [1] we need to update to the latest
and greatest firmware. This series does that. This is a destructive
change. e.g. Without all the patches in this series it will break the
i915 driver. As such, after we review all
New binaries for all platforms.
Cc: Matthew Brost
Cc: John Harrison
The following changes since commit f8462923ed8fc874f770b8c6dfad49d39b381f14:
nvidia: fix symlinks for tu104/tu106 acr unload firmware (2021-05-18 11:03:08
-0400)
are available in the Git repository at:
git://anongit.fre
On 6/1/2021 1:20 PM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
From: Chris Wilson
Allow internal clients to create a pinned context.
v2 (Daniele): export destructor as well, allow optional usage of custom
vm for maximum flexibility
On 5/25/2021 11:36 AM, Tang, CQ wrote:
-Original Message-
From: Intel-gfx On Behalf Of
Daniele Ceraolo Spurio
Sent: Monday, May 24, 2021 10:48 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vetter, Daniel ; Huang Sean Z
; dri-de...@lists.freedesktop.org; Chris Wilson
; Kondapally
On 5/25/2021 6:32 AM, Daniel Vetter wrote:
On Mon, May 24, 2021 at 10:48:00PM -0700, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow
: Rodrigo Vivi
CC: Tvrtko Ursulin
CC: Chris P Wilson
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 22
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
drivers/gpu/drm/i915
. [Ville]
v4 (Daniele): update pxp_is_borked check.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 13 +-
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm
state computation. [Ville]
removed pointless code. [Ville]
v8 (Daniele): update PXP check
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
ed to a context lut, only remove them once (Chris),
make protected context flag not mandatory in protected object execbuf
to avoid abuse (Lionel)
v4: rebase to new gem_create_ext
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Ka
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8
esson on
resume (delayed to first submission).
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 +++-
drivers/gpu/drm/i915/i915_drv.c
.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
context flag not mandatory in protected object execbuf to avoid
abuse (Lionel)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
: split export of pinned_context functions to a separate patch (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers
From: Chris Wilson
Allow internal clients to create a pinned context.
v2 (Daniele): export destructor as well, allow optional usage of custom
vm for maximum flexibility.
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine.h| 10
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
v4: move interface defs to separate header, set arb_is valid to false
on fini (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/
-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a
me
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile
alizes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
v4: improve comments, simplify wait logic (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Ch
: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi #v2
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 87 ++
drivers/g
: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
v2: flip kconfig default to N. Some machines have IFWIs that do not
support PXP, so we need it to be an opt-in until we add support to query
the caps from the mei device.
Signed-off-by: Daniele Ceraolo Spurio
/gt: Export the pinned context constructor and destructor
Daniele Ceraolo Spurio (7):
drm/i915/pxp: Define PXP component interface
drm/i915/pxp: define PXP device flag and kconfig
drm/i915/pxp: allocate a vcs context for pxp usage
drm/i915/pxp: set KCR reg init
drm/i915/pxp: interface for
On 4/28/2021 1:04 PM, Ville Syrjälä wrote:
On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
On Wed, Apr 28, 2021 at 11:25:23AM +, Gupta, Anshuman wrote:
-Original Message-
From: Ville Syrjälä
Sent: Wednesday
Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
drivers/gpu/drm/i915/display/intel_display.c | 5 +++
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm/i915/display/skl_universal_plane.c| 32 +--
.../drm
On 4/16/2021 10:02 AM, Daniel Vetter wrote:
On Fri, Apr 16, 2021 at 6:38 PM Jason Ekstrand wrote:
On Thu, Apr 15, 2021 at 11:04 AM Matthew Auld wrote:
Add an entry for the new uAPI needed for DG1.
v2(Daniel):
- include the overall upstreaming plan
- add a note for mmap, there are di
true, switch the register/bit we're
performing the lock on.(MattR)
Bspec: 52890, 53509
Co-developed-by: Matt Roper
Cc: Tvrtko Ursulin
Cc: Matt Roper
Cc: Daniele Ceraolo Spurio
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i9
On 4/1/2021 5:05 AM, Lionel Landwerlin wrote:
On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at
. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc:
me
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/
n logic
v3: fix spinlock definition and usage, only validate objects when
they're first added to a context lut, only remove them once (Chris),
make protected context flag not mandatory in protected object execbuf
to avoid abuse (Lionel)
Signed-off-by: Bommu Krishnaiah
Signed-off-by:
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled
display black pixels by using plane color CTM correction.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../drm/i915/display
ssions and cleanup all the software states after the power cycle.
v2: runtime suspend also invalidates the keys
v3: fix return codes, simplify rpm ops (Chris), use the new worker func
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i91
.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
context flag not mandatory in protected object execbuf to avoid
abuse (Lionel)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b
)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 +++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm
alizes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i91
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Sp
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1
-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a
: introduce drm_i915_gem_create_ext
drm/i915/pxp: User interface for Protected buffer
Daniele Ceraolo Spurio (6):
drm/i915/pxp: Define PXP component interface
drm/i915/pxp: define PXP device flag and kconfig
drm/i915/pxp: allocate a vcs context for pxp usage
drm/i915/pxp: set KCR reg init
On 3/3/2021 2:42 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the term
On 3/8/2021 1:01 PM, Lionel Landwerlin wrote:
On 08/03/2021 22:40, Rodrigo Vivi wrote:
On Wed, Mar 03, 2021 at 05:24:34PM -0800, Daniele Ceraolo Spurio wrote:
On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele
On 3/3/2021 1:18 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the term
On 3/3/2021 3:16 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:55)
Usage of protected objects, coming in a follow-up patch, will be
restricted to protected contexts. Contexts can only be marked as
protected at creation time and they must be both bannable and not
On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin
On 3/3/2021 2:04 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:52)
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys f
On 3/3/2021 2:08 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:51)
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_in_play;
+}
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gp
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled
display black pixels by using plane color CTM correction.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../drm/i915/display
. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
tion logic
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_create.c| 27 +++--
.../gpu/drm/i915/gem/i915_gem_execbuffer
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc:
doc (Chris), invalidate contexts
on teardown
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem
ssions and cleanup all the software states after the power cycle.
v2: runtime suspend also invalidates the keys
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c
.
v2: use struct completion instead of bool (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 1
me
v2: emit in the ring, use high prio request (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 166 +++
drivers/gpu/drm/i915/pxp/
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 +
drivers/gpu/drm/i915/pxp/inte
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Sp
Set the KCR init during the boot time, which is required by hardware,
to allow us doing further protection operation such as sending commands
to GPU or TEE.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1
-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm
i915/uapi: introduce drm_i915_gem_create_ext
drm/i915/pxp: User interface for Protected buffer
Daniele Ceraolo Spurio (6):
drm/i915/pxp: Define PXP component interface
drm/i915/pxp: define PXP device flag and kconfig
drm/i915/pxp: allocate a vcs context for pxp usage
drm/i915/pxp: set KCR reg init
On 2/12/2021 5:23 AM, Lionel Landwerlin wrote:
I just gave a try to this new iteration and it's apparently failing to
enable PXP on a machine with this pciID : 0x9a68.
What error are you seeing?
Daniele
-Lionel
On 06/02/2021 04:09, Daniele Ceraolo Spurio wrote:
PXP (Protected Xe
On 2/6/2021 4:59 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:19)
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys f
On 2/6/2021 4:49 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:15)
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp
On 2/6/2021 5:08 AM, Chris Wilson wrote:
Quoting Chris Wilson (2021-02-06 13:06:05)
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:21)
+ if (!ret) {
+ ret = wait_for(!pxp->termination_in_progress, 10);
This only works by chance. The compiler doesn't even
On 2/6/2021 4:25 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:23)
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Only contexts created with the flag set are allowed to operate on
protected buffers.
We only allow
On 2/5/2021 6:09 PM, Daniele Ceraolo Spurio wrote:
PXP (Protected Xe Path) is an i915 component, available on
GEN12+, that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
I'm taking over this series from
. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21
ssions and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
drivers/gpu/drm/i915/i915_drv.c| 4 +
drive
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gp
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc:
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile
unrecoverable.
This is a rework + squash of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks have not been modified.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuma
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_
ned-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +
drivers/gp
off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 82 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files
Set the KCR init during the boot time, which is required by hardware,
to allow us doing further protection operation such as sending commands
to GPU or TEE.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29
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