me
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile
: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm
ned-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drive
f the object has not been used in an
execbuf beforehand.
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo Vivi
Reviewed-by: Uma Shankar #v9
---
driver
invalidation (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Bommu Krishnaiah
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 98 ---
drivers/gpu/drm/i915/gem/i91
. [Ville]
v4 (Daniele): update pxp_is_borked check.
v5: rebase on top of v9 plane decryption moving the decrypt check
(Juston)
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo
esson on
resume (delayed to first submission).
v5: move irq changes back to irq patch (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/
2 debugfs files, one to query the current status of the pxp session and one
to trigger an invalidation for testing.
v2: rename debugfs, fix date (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by : Alan Previn
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915
Now that all the pieces are in place we can add a description of how the
feature works. Also modify the comments in struct intel_pxp into
kerneldoc.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Rodrigo Vivi
---
Documentation/gpu/i915.rst | 8
drivers/gpu
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
On 9/9/2021 2:07 PM, Rodrigo Vivi wrote:
On Thu, Sep 09, 2021 at 05:29:08AM -0700, Daniele Ceraolo Spurio wrote:
This api allow user mode to create protected buffers and to mark
contexts as making use of such objects. Only when using contexts
marked in such a way is the execution guaranteed
On 9/9/2021 2:25 PM, Rodrigo Vivi wrote:
On Thu, Sep 09, 2021 at 05:29:14AM -0700, Daniele Ceraolo Spurio wrote:
Now that all the pieces are in place we can add a description of how the
feature works. Also modify the comments in struct intel_pxp into
kerneldoc.
Signed-off-by: Daniele
n Ekstrand
Cc: Daniel Vetter
Anshuman Gupta (2):
drm/i915/pxp: Add plane decryption support
drm/i915/pxp: black pixels on pxp disabled
Daniele Ceraolo Spurio (9):
drm/i915/pxp: Define PXP component interface
drm/i915/pxp: define PXP device flag and kconfig
drm/i915/pxp: allocate a vcs c
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by
-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 42
2 files changed, 43 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a
: split export of pinned_context functions to a separate patch (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c
: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
v2: flip kconfig default to N. Some machines have IFWIs that do not
support PXP, so we need it to be an opt-in until we add support to query
the caps from the mei device.
Signed-off-by: Daniele Ceraolo Spurio
he wait, as the component might be bound after i915 load
completes. We'll instead check when sending a tee message.
v5: fix an issue with mei_pxp module removal
v6: don't use fetch_and_zero in fini (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
invalidation (Rodrigo)
v9: better comments, avoid wakeref put race between pxp_inval and
context_close, add usage examples (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Bommu Krishnaiah
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc
ned-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drive
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem
f the object has not been used in an
execbuf beforehand.
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo Vivi
Reviewed-by: Uma Shankar #v9
---
driver
Now that all the pieces are in place we can add a description of how the
feature works. Also modify the comments in struct intel_pxp into
kerneldoc.
v2: improve doc (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Rodrigo Vivi
---
Documentation/gpu/i915.rst
me
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
v4: move interface defs to separate header, set arb_is valid to false
on fini (Rodrigo)
v5: handle async component binding
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wil
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
2 debugfs files, one to query the current status of the pxp session and one
to trigger an invalidation for testing.
v2: rename debugfs, fix date (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by : Alan Previn
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915
. [Ville]
v4 (Daniele): update pxp_is_borked check.
v5: rebase on top of v9 plane decryption moving the decrypt check
(Juston)
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo
esson on
resume (delayed to first submission).
v5: move irq changes back to irq patch (Rodrigo)
v6: drop invalidation in runtime suspend (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1
Reviewed-by: Daniele Ceraolo Spurio
Daniele
On 6/25/2021 5:45 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A new HuC is available for TGL and compatible platforms, so switch to
using it.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 6 +++---
1
t a 3 letter acronym, but
I can see using just adl could be confusing given that ADL-S uses a
different firmware.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 62,
that of all the siblings.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 10 +
drivers/gpu/drm/i915/gt/intel_engine.h
On 6/24/2021 12:04 AM, Matthew Brost wrote:
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical
that of all the siblings.
v2: Update to work with proto-ctx
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 6
On 7/19/2021 4:27 PM, Matthew Brost wrote:
On Mon, Jul 19, 2021 at 04:33:56PM -0700, Daniele Ceraolo Spurio wrote:
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function
On 7/16/2021 1:16 PM, Matthew Brost wrote:
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
Signed-off-by:
On 3/3/2021 2:42 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the term
-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a
: introduce drm_i915_gem_create_ext
drm/i915/pxp: User interface for Protected buffer
Daniele Ceraolo Spurio (6):
drm/i915/pxp: Define PXP component interface
drm/i915/pxp: define PXP device flag and kconfig
drm/i915/pxp: allocate a vcs context for pxp usage
drm/i915/pxp: set KCR reg init
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Sp
alizes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i91
: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b
)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 +++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm
.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
context flag not mandatory in protected object execbuf to avoid
abuse (Lionel)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
ssions and cleanup all the software states after the power cycle.
v2: runtime suspend also invalidates the keys
v3: fix return codes, simplify rpm ops (Chris), use the new worker func
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i91
. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc:
me
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/
n logic
v3: fix spinlock definition and usage, only validate objects when
they're first added to a context lut, only remove them once (Chris),
make protected context flag not mandatory in protected object execbuf
to avoid abuse (Lionel)
Signed-off-by: Bommu Krishnaiah
Signed-off-by:
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled
display black pixels by using plane color CTM correction.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../drm/i915/display
On 4/1/2021 5:05 AM, Lionel Landwerlin wrote:
On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at
true, switch the register/bit we're
performing the lock on.(MattR)
Bspec: 52890, 53509
Co-developed-by: Matt Roper
Cc: Tvrtko Ursulin
Cc: Matt Roper
Cc: Daniele Ceraolo Spurio
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i9
On 4/16/2021 10:02 AM, Daniel Vetter wrote:
On Fri, Apr 16, 2021 at 6:38 PM Jason Ekstrand wrote:
On Thu, Apr 15, 2021 at 11:04 AM Matthew Auld wrote:
Add an entry for the new uAPI needed for DG1.
v2(Daniel):
- include the overall upstreaming plan
- add a note for mmap, there are di
Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
drivers/gpu/drm/i915/display/intel_display.c | 5 +++
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm/i915/display/skl_universal_plane.c| 32 +--
.../drm
On 4/28/2021 1:04 PM, Ville Syrjälä wrote:
On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
On Wed, Apr 28, 2021 at 11:25:23AM +, Gupta, Anshuman wrote:
-Original Message-
From: Ville Syrjälä
Sent: Wednesday
On 01/02/2019 01:41 AM, Chris Wilson wrote:
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here is verboten (as we must be able to reset from underneath any
of our mutexes). That makes recovering th
On 01/07/2019 10:50 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-01-07 18:31:52)
On 01/02/2019 01:41 AM, Chris Wilson wrote:
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here
On 01/07/2019 01:35 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-01-07 21:28:48)
On 01/07/2019 10:50 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-01-07 18:31:52)
Were you already
planning/working on something along the lines of the possible solution
do need to call
intel_engine_init_workarounds for non-RCS engines.
Note that whitelist is still RCS-only.
Fixes: 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds")
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_lrc.c | 10 +-
1 file changed, 9
asked/cared about that since BDW was
released so it is relatively safe to assume that even if we added the
message no one would look at it. Just drop the dead code from the
driver instead.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_irq.c | 3 ---
drivers/gpu/drm/i915/intel_
n
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_workarounds.c | 117 +-
.../drm/i915/selftests/intel_workarounds.c| 69 +--
2 files changed, 119 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarou
do need to call
intel_engine_init_workarounds for non-RCS engines.
Note that whitelist is still RCS-only.
v2: move the call to logical_ring_init (Chris)
Fixes: 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds")
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers
reset with guc (perma-pinning the firmware in the GuC
unaccessible range of the GGTT),
Acked-by: Daniele Ceraolo Spurio
Daniele
-Mika
---
drivers/gpu/drm/i915/i915_reset.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915
full interrupt setup is performed.
Cc: Mika Kuoppala
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fd5080c4ccb..7056ae2d1e0e 100644
--- a/drivers
On 1/22/2019 6:32 PM, Daniele Ceraolo Spurio wrote:
When reading GEN11_GT_INTR_DWx closely after enabling the interrupts
in gen11_irq_postinstall, the returned value is garbage. This can
To clarify, this only happens (or at least I've only seen it) during
runtime_resume.
Daniele
On 01/23/2019 03:40 AM, Mika Kuoppala wrote:
Daniele Ceraolo Spurio writes:
On 1/22/2019 6:32 PM, Daniele Ceraolo Spurio wrote:
When reading GEN11_GT_INTR_DWx closely after enabling the interrupts
in gen11_irq_postinstall, the returned value is garbage. This can
To clarify, this only
c: Michał Winiarski
Cc: "Bloomfield, Jon"
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/
On 5/1/19 8:34 AM, Stuart Summers wrote:
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Reviewed-by: Daniele Ceraolo Spurio
---
drivers
On 5/1/19 8:34 AM, Stuart Summers wrote:
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm
On 5/1/19 8:34 AM, Stuart Summers wrote:
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h
On 5/1/19 8:34 AM, Stuart Summers wrote:
v2: fix spacing from checkpatch warning
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions
Can you elaborate a bit more on what's the rationale for this? do you
just want to avoid having too many inlines since the paths they're used
in are not critical, or do you have some more functional reason? This is
not a critic to the patch, I just want to understand where you're coming
from ;)
On 5/1/19 2:04 PM, Summers, Stuart wrote:
On Wed, 2019-05-01 at 13:04 -0700, Daniele Ceraolo Spurio wrote:
Can you elaborate a bit more on what's the rationale for this? do
you
just want to avoid having too many inlines since the paths they're
used
in are not critical, or do you
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Can you also get an ack from Lionel, to make sure this all fits with the
expected reporting?
---
drivers/gpu/drm/i915
).
Reported-by: Daniele Ceraolo Spurio
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
And we now have a new failure to look at that we weren't seeing before
because the ex
into a single patch
break 80 character line to fix checkpatch warning
move get/set_eus helpers to intel_device_info.c
Acked-by: Jani Nikula
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 17
drivers/gpu/drm/i915/gt
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
v5: address review comments from Tvrtko and Daniele
Cc: Daniele Ceraolo Spurio
Cc: Lionel Landwerlin
Acked-by: Lionel Landwerlin
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const struct
intel_device_info *info,
#undef PRINT_FLAG
}
+#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1)
+
+static char *
Quite a few of the call points have already switched to the version
working directly on the runtime_pm structure, so let's switch over the
rest and kill the i915-based asserts.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gvt/aperture_gm.c| 2 +-
drivers/gpu/drm
As a first step towards updating the code to work on the runtime_pm
structure instead of i915, rework all the internals to use and pass
around that.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_drv.h| 10
With this all the rpm assert-related functions consistently work on
the i915_runtime_pm structure
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 44 +++--
drivers/gpu/drm/i915/i915_irq.c | 32 ++---
drivers/gpu/drm
eas in the display domain,
so I gave up for now.
Series very lightly tested.
Cc: Imre Deak
Cc: Chris Wilson
Daniele Ceraolo Spurio (7):
drm/i915: prefer i915_runtime_pm in intel_runtime function
drm/i915: Remove rpm asserts that use i915
drm/i915: make enable/disable rpm assert function u
Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 52 +
drivers/gpu/drm/i915/intel_drv.h| 97
drivers/gpu/drm/i915/intel_runtime_pm.c | 58
Matching the underlying get/put functions.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c
Focusing on the functions called in few places.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 17 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ---
drivers
The functions are internally already only using the structure, so we
need to just flip the interface.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +--
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -9,16 +9,18 @@
#include
#include
+#include
AFAICS this header is not needed anymore. With it removed:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
struct drm_i915_private;
#define
On 5/16/19 3:42 PM, Chris Wilson wrote:
Quoting Chris Wilson (2019-05-16 23:10:10)
Quoting Chris Wilson (2019-05-16 23:07:43)
Quoting Daniele Ceraolo Spurio (2019-05-16 22:56:31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
b/drivers/gpu/drm/i915/intel_runtime_pm.h
index
Now that all the uncore management is hidden under the uncore struct,
move the lock initialization under the uncore_init as well for better
encapsulation.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm
On 4/1/19 1:24 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-04-01 21:14:11)
Now that all the uncore management is hidden under the uncore struct,
move the lock initialization under the uncore_init as well for better
encapsulation.
Signed-off-by: Daniele Ceraolo Spurio
Cc
Encapsulate the uncore early init and be consistent with the
"_early" naming.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/intel_uncore.c | 4
drivers/gpu/drm/i915/intel_uncore.
Add "_mmio" postfix to be consistent from the init/fini phase they're
called from.
Signed-off-by: Daniele Ceraolo Spurio
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/intel_uncore.c | 6
Encapsulate the uncore early init and be consistent with the
"_early" naming.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/intel_uncore.c | 4
drivers/gp
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