From: Deepak S deepa...@linux.intel.com
Drop WaGsvBringDownFreq on CHV.
When in RC6 requesting the min freq should be fine to bring the
voltage down.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
From: Deepak S deepa...@linux.intel.com
Workaround fixed in Latest VLV revision. Forcing Gfx clk up not needed, and
Requesting the
min freq should bring bring the voltage Vnn.
v2: Drop WA for Latest VLV revision (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915
On Friday 13 June 2014 05:24 PM, Imre Deak wrote:
This functionality will be also needed by an upcoming patch, so factor
it out. As a bonus this also makes things a bit more uniform across
platforms. Note that this also changes the register read-modify-write
to a simple write during disabling.
On Friday 13 June 2014 05:24 PM, Imre Deak wrote:
Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.
Signed-off-by: Imre Deak imre.d...@intel.com
On Friday 13 June 2014 05:24 PM, Imre Deak wrote:
Blanking/unblanking the console in a loop on an Asus T100 sometimes
leaves the console blank. After some digging I found that applying
commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595
Author: Egbert Eich e...@suse.com
Date: Mon Mar 4 09:24:38
On Monday 07 July 2014 02:35 PM, Daniel Vetter wrote:
On Tue, Jun 24, 2014 at 05:22:17PM +0530, Deepak S wrote:
Hi Chris/Daniel,
The patch is helping in some of the side-effects due to gpu boost. I
still need to get more data. I will keep the thread updated.
Ping. Might as well review
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging the
increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_sysfs.c | 18 +++---
1 file changed, 15 insertions(+), 3
From: Deepak S deepa...@linux.intel.com
Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on
VLV and CHV
Deepak S (7):
drm/i915: Read guaranteed freq for valleyview
drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
drm/i915: keep freq/opcode
From: Deepak S deepa...@linux.intel.com
We need mem_freq or cz clock for freq/opcode conversion
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 29
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer platform freq/opcode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
From: Deepak S deepa...@linux.intel.com
Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same
for CHV.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions
From: Deepak S deepa...@linux.intel.com
Reading RP1 for valleyview to help us enable pm_rps i-g-t testcase
execution.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Deepak S deepa...@linux.intel.com
Adding chv specific fre/encode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 68 +++--
1 file changed, 59 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git
On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having
On Thursday 10 July 2014 11:58 AM, Daniel Vetter wrote:
On Fri, Jul 11, 2014 at 09:56:35AM +0530, Deepak S wrote:
On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Since
From: Deepak S deepa...@linux.intel.com
Adding chv specific fre/encode conversion.
v2: Remove generic function and platform check (Daniel)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 78 +++--
1 file changed, 76
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.
v2: Use vlv_gpu_freq to get freq (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 15 +++
1 file
On Saturday 28 June 2014 04:33 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
mem_freq is needed to decode the GPU freq opcodes.
FIXME: Punit reg seems to contain garbage so this isn't right
Signed-off-by: Ville Syrjälä
valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
+static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
{
return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) 0xff;
}
Looks good. Reviewed-by: Deepak S deepa...@linux.intel.com
);
+ if (WARN_ON_ONCE(dev_priv-rps.max_freq 1))
+ dev_priv-rps.max_freq = ~1;
Cannot we use ALIGN Here?
Other than this it looks fine
Reviewed-by: Deepak S deepa...@linux.intel.com
dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
DRM_DEBUG_DRIVER(max GPU freq: %d
;
}
Reviewed-by: Deepak S deepa...@linux.intel.com
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Saturday 28 June 2014 11:26 AM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Drop WaGsvBringDownFreq on CHV.
When in RC6 requesting the min freq should be fine to bring the
voltage down.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915
On Friday 20 June 2014 08:03 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high during the suspend.
Force gt to move to lowest freq while suspending.
v2: Fixed typo in commit message (Deepak)
v3: Force gt
On Monday 14 July 2014 08:47 PM, Jesse Barnes wrote:
On Tue, 15 Jul 2014 13:03:55 +0530
Deepak S deepa...@linux.intel.com wrote:
On Saturday 28 June 2014 11:26 AM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Drop WaGsvBringDownFreq on CHV.
When in RC6 requesting
On Monday 14 July 2014 08:47 PM, Jesse Barnes wrote:
On Tue, 15 Jul 2014 13:05:48 +0530
Deepak S deepa...@linux.intel.com wrote:
On Friday 20 June 2014 08:03 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Deepak S deepa...@intel.com
This was fumbled while trying to use the cached min/min/rpe values in the vlv
debugfs code.
This is a regression from
commit 03af20458a57a50735b12c1e3c23abc7ff70c6fa
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Sat
From: Deepak S deepa...@linux.intel.com
This was fumbled while trying to use the cached min/min/rpe values in
the vlv debugfs code.
This is a regression from
commit 03af20458a57a50735b12c1e3c23abc7ff70c6fa
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Sat Jun 28 02
On Thursday 17 July 2014 09:16 AM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm
On Monday 21 July 2014 10:42 PM, Ben Widawsky wrote:
On Tue, Jul 22, 2014 at 01:50:20PM +0530, Deepak S wrote:
On Thursday 17 July 2014 09:16 AM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode
for diverse scenarios beyond the author's imagination.
Chris Wilson (3):
drm/i915: Clearing buffer objects via blitter engine
drm/i915: Introduce a new create ioctl for user specified placement
drm/i915: Add support for stealing purgable stolen pages
Deepak S (1):
drm/i915: Clearing
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Sat Nov 2 21:07:09 2013 -0700
On Wednesday 20 August 2014 04:26 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 01:37:09PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
True, but...
This is a regression from
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Sat Nov 2 21:07:09 2013 -0700
) *
2);
return opcode;
Patch looks fine to me
Reviewed-by: Deepak S deepa...@linux.intel.com
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Monday 18 August 2014 05:12 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to
: Deepak S deepa...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a54870..6d5ae82 100644
On Friday 29 August 2014 04:51 PM, Chris Wilson wrote:
On Fri, Aug 29, 2014 at 02:14:07PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
WaGsvRC0ResidenncyMethod is for vlv, it doesn't deal with chv
appropriately (eg. doesn't limit rps values to
On Thursday 28 August 2014 11:00 AM, Daniel Vetter wrote:
On Fri, Aug 29, 2014 at 08:45:21AM +0530, Deepak S wrote:
On Tuesday 26 August 2014 07:24 PM, Daniel Vetter wrote:
On Fri, Aug 22, 2014 at 08:32:40AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
-uncore.funcs.force_wake_get =
__gen7_gt_force_wake_mt_get;
dev_priv-uncore.funcs.force_wake_put =
__gen7_gt_force_wake_mt_put;
} else if (IS_IVYBRIDGE(dev)) {
Yup I Agree :)
Reviewed-by: Deepak S deepa...@linux.intel.com
___
Intel-gfx
From: Deepak S deepa...@linux.intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf/power)
we can either enable/disable.
v2: Addressed rps default comment (Jani)
v3: Use bool to represent the boot parameter
From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
On Monday 28 April 2014 08:15 PM, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 05:29:46PM +0300, Imre Deak wrote:
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt
Thanks for the review. I will address the comments
On Saturday 26 April 2014 03:12 AM, Ben Widawsky wrote:
On Mon, Apr 21, 2014 at 01:34:07PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR
Thanks for the review. I will address the comments
On Monday 28 April 2014 07:59 PM, Imre Deak wrote:
On Mon, 2014-04-21 at 13:34 +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition
On Monday 28 April 2014 08:42 PM, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 4:47 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf
Thanks Ben. Apologies for delayed response.
I am incorporating the review comment changes next set of patch review.
On Saturday 26 April 2014 03:24 AM, Ben Widawsky wrote:
On Mon, Apr 21, 2014 at 01:34:08PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
, Unnecessary empty line and use right
IIR interrupt (Ville)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 75 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman
From: Deepak S deepa...@linux.intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (131) mask (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915
From: Deepak S deepa...@linux.intel.com
Squashed some of the patches and created a new patch series. Addressed review
comments on most of the patches.
Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler
Deepak S (7):
drm/i915: Enable PM Interrupts target via Display
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
Signed-off-by: Deepak S deepa
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu
From: Ville Syrjälä ville.syrj...@linux.intel.com
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Acked-by: Ben Widawsky b
From: Deepak S deepa...@linux.intel.com
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
On Tuesday 06 May 2014 03:20 AM, Daisy Sun wrote:
RP frequency request is affected by 2 modules: normal turbo
algorithm and RPS boost algorithm. By adding RPS boost algorithm
to the mix, the final frequency becomes relatively unpredictable.
Add a switch to enable/disable RPS boost
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers
From: Deepak S deepa...@linux.intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (131) mask (Ville)
v3: Add Gen check for the mask (ville)
Signed-off-by: Deepak S deepa
On Friday 09 May 2014 06:49 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg
Hi Mika,
On the PCBR check comment. I will create a separate patch to address both VLV
and CHV
Thanks
Deepak
On Thursday 15 May 2014 03:27 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers
From: Deepak S deepa...@linux.intel.com
Squashed some of the patches and rebased the patches on latest nightly.
Deepak S (5):
drm/i915/chv: Enable Render Standby (RC6) for Cherryview
drm/i915/chv: Added CHV specific register read and write and
Streamline CHV forcewake stuff
drm/i915
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S deepa
From: Ville Syrjälä ville.syrj...@linux.intel.com
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
Streamline the CHV forcewake functions
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Acked-by: Ben Widawsky b
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code
Thanks for the Review. I will address the comments
On Monday 26 May 2014 08:07 PM, Mika Kuoppala wrote:
Deepak S deepa...@linux.intel.com writes:
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2
On Monday 26 May 2014 08:02 PM, Ville Syrjälä wrote:
On Mon, May 26, 2014 at 07:24:21PM +0530, Deepak S wrote:
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec
On Tuesday 27 May 2014 05:29 PM, Ville Syrjälä wrote:
On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa
On Tuesday 27 May 2014 05:12 PM, Daniel Vetter wrote:
On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up
From: Deepak S deepa...@linux.intel.com
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq should bring bring the voltage Vnn.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 40 +---
1
On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Workaround fixed in BYT. Forcing Gfx clk up not needed
On Friday 13 June 2014 07:24 PM, Daniel Vetter wrote:
On Fri, Jun 13, 2014 at 05:56:41PM +0530, Deepak S wrote:
On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa
From: Deepak S deepa...@linux.intel.com
We might be leaving the PGU Frequency (and thus vnn) high during the suspend.
Flusing the delayed work queue should take care of this.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high during the suspend.
Flush the delayed work queue should take care of this.
v2: Fixed typo in commit message (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915
On Wednesday 18 June 2014 03:47 AM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 05:30:53AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high during the suspend.
Flush the delayed work queue should take
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high during the suspend.
Force gt to move to lowest freq while suspending.
v2: Fixed typo in commit message (Deepak)
v3: Force gt to lowest freq in suspend_gt_powersave (Daniel)
Signed-off-by: Deepak S
On Thursday 19 June 2014 06:04 PM, Daniel Vetter wrote:
On Fri, Jun 20, 2014 at 1:59 PM, deepa...@linux.intel.com wrote:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2043c4b..6bbb90b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++
From: Deepak S deepa...@linux.intel.com
We might be leaving the GPU Frequency (and thus vnn) high during the suspend.
Force gt to move to lowest freq while suspending.
v2: Fixed typo in commit message (Deepak)
v3: Force gt to lowest freq in suspend_gt_powersave (Daniel)
v4: Add GPU min freq
On Thursday 12 June 2014 03:02 PM, Daniel Vetter wrote:
Adding Deepak for testing, this hopefully alleviates the bad
side-effects of the gpu booster he's seeing.
-Daniel
On Thu, Jun 12, 2014 at 11:28 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
Make the assumption that media workloads are
Hi Chris/Daniel,
The patch is helping in some of the side-effects due to gpu boost. I still
need to get more data. I will keep the thread updated.
Thanks
Deepak
On Thursday 12 June 2014 03:02 PM, Daniel Vetter wrote:
Adding Deepak for testing, this hopefully alleviates the bad
side-effects
From: Deepak S deepa...@intel.com
Split vlv force wake routines to help individually control Media/Render
well based on the register access.
We've seen power savings in the lower sub-1W range on workloads that
only need on of the power wells, e.g. glbenchmark, media playback
Signed-off
From: Deepak S deepa...@intel.com
Added power well arguments to all the force wake routines
to help us individually control power well based on the
scenario.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++---
drivers/gpu/drm/i915/i915_drv.h
From: Deepak S deepa...@intel.com
Valleyview has power wells MEDIA RENDER and by spliting
vlv force wake routines and individually controling Media/Render well,
We have seen power savings in the lower sub-1W range on different
workloads, e.g. glbenchmark, media playback
Deepak S (3):
drm/i915
From: Deepak S deepa...@intel.com
For RC6 Timeout method, we need to set promotion timer to 1750 us ( 1367
* 1.28 us)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 6 ++
1
From: Deepak S deepa...@intel.com
Valleyview has power wells MEDIA RENDER and by spliting vlv force wake
routines and individually controling Media/Render well, We have seen power
savings in the lower sub-1W range on different workloads, e.g. glbenchmark,
media playback
v2: Addressed review
From: Deepak S deepa...@intel.com
Added power well arguments to all the force wake routines
to help us individually control power well based on the
scenario.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++---
drivers/gpu/drm/i915/i915_drv.h
From: Deepak S deepa...@intel.com
Forcewake counts for valleyview are not exposed throgh DebugFS.
Exposing with this change.
v2: Separate spurious warning fix from this patch. (Jesse/Daniel)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14
1 - 100 of 362 matches
Mail list logo
