Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout
On Wed, Dec 09, 2020 at 06:30:16PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout > URL : https://patchwork.freedesktop.org/series/84735/ > State : success Thanks for the review, pushed to din. > > == Summary == > > CI Bug Log - changes from CI_DRM_9464_full -> Patchwork_19093_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_19093_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_params@no-vebox: > - shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271]) +38 similar > issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl2/igt@gem_exec_par...@no-vebox.html > > * igt@gem_exec_reloc@basic-many-active@vcs1: > - shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389]) >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html > > * igt@i915_pm_rc6_residency@rc6-idle: > - shard-hsw: [PASS][3] -> [WARN][4] ([i915#1519]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-hsw2/igt@i915_pm_rc6_reside...@rc6-idle.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-hsw2/igt@i915_pm_rc6_reside...@rc6-idle.html > > * igt@kms_chamelium@dp-hpd-storm-disable: > - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) > +4 similar issues >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl2/igt@kms_chamel...@dp-hpd-storm-disable.html > > * igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen: > - shard-skl: [PASS][6] -> [FAIL][7] ([i915#54]) +1 similar issue >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-skl: [PASS][8] -> [FAIL][9] ([i915#2346] / [i915#533]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html > > * igt@kms_cursor_legacy@flip-vs-cursor-legacy: > - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2346]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-tglb5/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-tglb5/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html > > * igt@kms_cursor_legacy@pipe-d-single-bo: > - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl2/igt@kms_cursor_leg...@pipe-d-single-bo.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: > - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html > - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2598]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html > > * igt@kms_hdr@bpc-switch-dpms: > - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_...@bpc-switch-dpms.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl6/igt@kms_...@bpc-switch-dpms.html > > * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: > - shard-skl: NOTRUN -> [FAIL][19] ([fdo#108145] / [i915#265]) +1 > similar issue >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19093/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-alpha-7efc.html > > * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145] / > [i915#265]) +1 similar issue >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html >[21]: > https://intel-gfx-ci
Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
On Fri, Dec 11, 2020 at 09:04:02AM +0200, Chery, Nanley G wrote: > [...] > > > We probably don't have to update the header, but we noticed in our > > > testing that the clear color prefers an alignment greater than 64B. > > > Unfortunately, I can't find any bspec note about this. As long as the > > > buffer creators are aware though, I think we should be fine. I don't > > > know if this is the best forum to bring it up, but I thought I'd > > > share. > > > > Yes, would be good to clarify this and get it also to the spec. Then the > > driver should also check the alignment of the 3rd FB plane. > > I plan to run some more tests and file a bug in the spec. Ok, thanks. Note that this patch has a problem with synchornization and based on Chris' response I'm planning to update it once I figured out the proper way to map the CC plane. Until that you could still use it on TGL if you wait for the RT result explicitly after the fast clear and before flipping to it (that's what the IGT test does atm). > I see that the IGT test only clears the fb once. Just to confirm, is the > clear color offset read from on every frame? Userspace would like to be > able to pass different clear colors for an fb. Yes, every time you do a flip the kernel will re-read the CC value and program it to the display. --Imre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Missing DPPLL case on i7-1165G7
Hi, On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote: > > At boot, > > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon > [2.788001] i915 :00:02.0: [drm] *ERROR* LSPCON init failed on port E > [2.790752] [ cut here ] > [2.790753] Missing case (clock == 539440) > [2.790790] WARNING: CPU: 0 PID: 159 at > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2967 icl_get_dplls+0x53a/0xa50 > [i915] the above warn looks to be due to a missing workaround fixed by commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e Author: Imre Deak Date: Sat Oct 3 03:18:46 2020 +0300 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock in drm-tip. Could you give it a try? > In drivers/gpu/drm/i915/display/intel_dpll_mgr.c, I see an entry for 540,000. > Presumbly, this clock was supposed to be rounded up to that somewhere. > This is an HP Spectre x360 using the internal display. Here's the EDID > in case that's useful: > > $ edid-decode /sys/class/drm/card0-eDP-1/edid > edid-decode (hex): > > 00 ff ff ff ff ff ff 00 4c 83 49 41 00 00 00 00 > 13 1d 01 04 b5 1d 11 78 02 38 d1 ae 51 3b b8 23 > 0b 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 > 01 01 01 01 01 01 b9 d5 00 40 f1 70 20 80 30 20 > 88 00 26 a5 10 00 00 1b b9 d5 00 40 f1 70 20 80 > 30 20 88 00 26 a5 10 00 00 1b 00 00 00 0f 00 ff > 09 3c ff 09 3c 2c 80 00 00 00 00 00 00 00 00 10 > 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 af > > 02 03 0f 00 e3 05 80 00 e6 06 05 01 73 6d 07 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ab > > > > EDID version: 1.4 > Manufacturer: SDC Model 16713 Serial Number 0 > Made in week 19 of 2019 > Digital display > 10 bits per primary color channel > DisplayPort interface > Maximum image size: 29 cm x 17 cm > Gamma: 2.20 > Supported color formats: RGB 4:4:4 > First detailed timing includes the native pixel format and preferred refresh > rate > Color Characteristics > Red: 0.6796, 0.3193 > Green: 0.2324, 0.7187 > Blue: 0.1396, 0.0439 > White: 0.3125, 0.3291 > Established Timings I & II: none > Standard Timings: none > Detailed mode: Clock 547.130 MHz, 294 mm x 165 mm >3840 3888 3920 4160 ( 48 32 240) >2160 2168 2176 2192 ( 8 8 16) >+hsync -vsync >VertFreq: 60.001 Hz, HorFreq: 131.522 kHz > Detailed mode: Clock 547.130 MHz, 294 mm x 165 mm >3840 3888 3920 4160 ( 48 32 240) >2160 2168 2176 2192 ( 8 8 16) >+hsync -vsync >VertFreq: 60.001 Hz, HorFreq: 131.522 kHz > Manufacturer-Specified Display Descriptor (0x0f): 00 0f 00 ff 09 3c ff 09 3c > 2c 80 00 00 00 00 00 .<..<,.. > Dummy Descriptor > Has 1 extension block > Checksum: 0xaf > > > > CTA-861 Extension Block Revision 3 > 0 native detailed modes > 11 bytes of CTA data blocks > Extended tag: Colorimetry Data Block > BT2020RGB > Extended tag: HDR Static Metadata Data Block > Electro optical transfer functions: > Traditional gamma - SDR luminance range > SMPTE ST2084 > Supported static metadata descriptors: > Static metadata type 1 > Desired content max luminance: 115 (603.666 cd/m^2) > Desired content max frame-average luminance: 109 (530.095 cd/m^2) > Desired content min luminance: 7 (0.005 cd/m^2) > Checksum: 0xab > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c
intel_dp_set_signal_levels() is needed for link training, so move it to
intel_dp_link_training.c.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c| 18 --
drivers/gpu/drm/i915/display/intel_dp.h| 3 ---
.../drm/i915/display/intel_dp_link_training.c | 18 ++
.../drm/i915/display/intel_dp_link_training.h | 2 ++
4 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f0e8aaac413c..88a6033d6867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5003,24 +5003,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u8 train_set = intel_dp->train_set[0];
-
- drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
- train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
- train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
- drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
- (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
- DP_TRAIN_PRE_EMPHASIS_SHIFT,
- train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
- " (max)" : "");
-
- intel_dp->set_signal_levels(intel_dp, crtc_state);
-}
-
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 4280a09fd8fd..4ebda4e43003 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -96,9 +96,6 @@ void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
u8 dp_train_pat);
-void
-intel_dp_set_signal_levels(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 91d3979902d0..7876e781f698 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,6 +334,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
}
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u8 train_set = intel_dp->train_set[0];
+
+ drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
+ train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
+ train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
+ drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
+ (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT,
+ train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
+ " (max)" : "");
+
+ intel_dp->set_signal_levels(intel_dp, crtc_state);
+}
+
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 86905aa24db7..c3110c032bc2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -17,6 +17,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE]);
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
void intel_dp_start_link_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
void
[Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode
The DP PHY vswing/pre-emphasis level programming the driver does is
related to the DPTX -> first LTTPR link segment only. Accordingly it
should be only programmed when link training the first LTTPR and kept
as-is when training subsequent LTTPRs and the DPRX. For these latter
PHYs the vs/pe levels will be set in response to writing the
DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
The above is also described in DP Standard v2.0 under 3.6.6.1.
While at it simplify and add the LTTPR that is link trained to the debug
message in intel_dp_set_signal_levels().
Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link
training")
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 19 +++
.../drm/i915/display/intel_dp_link_training.h | 3 ++-
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 88a6033d6867..16c563f1a515 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6057,7 +6057,7 @@ static void intel_dp_process_phy_request(struct intel_dp
*intel_dp,
intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
- intel_dp_set_signal_levels(intel_dp, crtc_state);
+ intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
intel_dp_phy_pattern_update(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 7876e781f698..d8c6d7054d11 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
}
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ enum drm_dp_phy dp_phy)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 train_set = intel_dp->train_set[0];
+ char phy_name[10];
- drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
+ drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis
level %d%s, at %s\n",
train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
- train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
- drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
+ train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
DP_TRAIN_PRE_EMPHASIS_SHIFT,
train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
- " (max)" : "");
+ " (max)" : "",
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
- intel_dp->set_signal_levels(intel_dp, crtc_state);
+ if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
+ intel_dp->set_signal_levels(intel_dp, crtc_state);
}
static bool
@@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
{
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
- intel_dp_set_signal_levels(intel_dp, crtc_state);
+ intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
dp_train_pat);
}
@@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
int ret;
- intel_dp_set_signal_levels(intel_dp, crtc_state);
+ intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
intel_dp->train_set, crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index c3110c032bc2..6a1f76bd8c75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE]);
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
- const struct int
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Track pm_qos per connector
On Wed, Dec 30, 2020 at 10:48:34AM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a single global pm_qos, track the pm_qos request for
> each intel_dp.
>
> Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Imre Deak
Could intel_dp_aux_init/fini() be used?
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 16 +---
> drivers/gpu/drm/i915/i915_drv.c | 5 -
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 4 files changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b86ba1bdbaa3..1067bd073c95 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1463,6 +1463,9 @@ struct intel_dp {
> bool rgb_to_ycbcr;
> } dfp;
>
> + /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> + struct pm_qos_request pm_qos;
> +
> /* Display stream compression testing */
> bool force_dsc_en;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 357f7921e070..f08e5f1f463d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>* lowest possible wakeup latency and so prevent the cpu from going into
>* deep sleep states.
>*/
> - cpu_latency_qos_update_request(&i915->pm_qos, 0);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>
> intel_dp_check_edp(intel_dp);
>
> @@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>
> ret = recv_bytes;
> out:
> - cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
> @@ -7527,6 +7527,14 @@ static int intel_dp_connector_atomic_check(struct
> drm_connector *conn,
>
> return intel_modeset_synced_crtcs(state, conn);
> }
> +static void intel_dp_connector_destroy(struct drm_connector *connector)
> +{
> + struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> +
> + cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> +
> + intel_connector_destroy(connector);
> +}
>
> static const struct drm_connector_funcs intel_dp_connector_funcs = {
> .force = intel_dp_force,
> @@ -7535,7 +7543,7 @@ static const struct drm_connector_funcs
> intel_dp_connector_funcs = {
> .atomic_set_property = intel_digital_connector_atomic_set_property,
> .late_register = intel_dp_connector_register,
> .early_unregister = intel_dp_connector_unregister,
> - .destroy = intel_connector_destroy,
> + .destroy = intel_dp_connector_destroy,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> .atomic_duplicate_state = intel_digital_connector_duplicate_state,
> };
> @@ -8621,6 +8629,8 @@ intel_dp_init_connector(struct intel_digital_port
> *dig_port,
> intel_dp->frl.is_trained = false;
> intel_dp->frl.trained_rate_gbps = 0;
>
> + cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> +
> return true;
>
> fail:
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5708e11d917b..249f765993f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
>
> pci_set_master(pdev);
>
> - cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
> -
> intel_gt_init_workarounds(dev_priv);
>
> /* On the 945G/GM, the chipset reports the MSI capability on the
> @@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
> err_msi:
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> err_mem_regions:
> intel_memory
Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Track pm_qos per connector
On Wed, Dec 30, 2020 at 05:07:34PM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a single global pm_qos, track the pm_qos request for
> each intel_dp.
>
> v2: Move the pm_qos setup/teardown to intel_dp_aux_init/fini
>
> Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Imre Deak
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c| 6 --
> drivers/gpu/drm/i915/i915_drv.c| 5 -
> drivers/gpu/drm/i915/i915_drv.h| 3 ---
> 4 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b86ba1bdbaa3..1067bd073c95 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1463,6 +1463,9 @@ struct intel_dp {
> bool rgb_to_ycbcr;
> } dfp;
>
> + /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> + struct pm_qos_request pm_qos;
> +
> /* Display stream compression testing */
> bool force_dsc_en;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 357f7921e070..dafb1334f91a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>* lowest possible wakeup latency and so prevent the cpu from going into
>* deep sleep states.
>*/
> - cpu_latency_qos_update_request(&i915->pm_qos, 0);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>
> intel_dp_check_edp(intel_dp);
>
> @@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>
> ret = recv_bytes;
> out:
> - cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
> @@ -1919,6 +1919,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
> *intel_dp, int index)
> static void
> intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> + cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> kfree(intel_dp->aux.name);
> }
>
> @@ -1971,6 +1972,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> encoder->base.name);
>
> intel_dp->aux.transfer = intel_dp_aux_transfer;
> + cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> }
>
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5708e11d917b..249f765993f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
>
> pci_set_master(pdev);
>
> - cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
> -
> intel_gt_init_workarounds(dev_priv);
>
> /* On the 945G/GM, the chipset reports the MSI capability on the
> @@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
> err_msi:
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> err_mem_regions:
> intel_memory_regions_driver_release(dev_priv);
> err_ggtt:
> @@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
> *dev_priv)
>
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> -
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e38a10d5c128..5e5bcef20e33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -891,9 +891,6 @@ struct drm_i915_private {
>
> bool display_irqs_enabled;
>
> - /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> - struct pm_qos_request pm_qos;
> -
> /* Sideband mailbox protection */
> struct mutex sb_lock;
> struct pm_qos_request sb_qos;
> --
> 2.20.1
>
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Re: [Intel-gfx] [RFC v2] drm/i915/pps: Add PPS power domain
On Wed, Jan 06, 2021 at 10:04:38AM +0530, Anshuman Gupta wrote:
> It abstracts getting the AUX power domain in pps_lock under
> PPS power domain. This makes sure that the platforms which really
> requires AUX power in order to access PPS registers will get the
> reference to necessary power wells.
>
> PPS power domain requires only to track the AUX_A associated
> power wells as the platforms need AUX power in order to access PPS
> registers supports eDP only on PORT_A.
>
> v2:
> - Fixed missed POWER_DOMAIN_PPS in pps_unlock().
>
> Cc: Imre Deak
> Cc: Jani Nikula
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c| 7 ++-
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d52374f01316..1dc4ca9e5d1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -107,6 +107,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "VGA";
> case POWER_DOMAIN_AUDIO:
> return "AUDIO";
> + case POWER_DOMAIN_PPS:
> + return "PPS";
> case POWER_DOMAIN_AUX_A:
> return "AUX_A";
> case POWER_DOMAIN_AUX_B:
> @@ -2651,11 +2653,13 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_PPS) | \
> BIT_ULL(POWER_DOMAIN_GMBUS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |\
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_PPS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> @@ -2688,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |\
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_PPS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> @@ -2700,6 +2705,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> #define GLK_DISPLAY_AUX_A_POWER_DOMAINS (\
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
> + BIT_ULL(POWER_DOMAIN_PPS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_AUX_B_POWER_DOMAINS (\
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> @@ -2712,6 +2718,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_PPS) | \
> BIT_ULL(POWER_DOMAIN_GMBUS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index bc30c479be53..7642be3c8e2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -55,6 +55,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_OTHER,
> POWER_DOMAIN_VGA,
> POWER_DOMAIN_AUDIO,
> + POWER_DOMAIN_PPS,
> POWER_DOMAIN_AUX_A,
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8a00e609085f..99b4bec3c926 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -895,8 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
>* See intel_power_sequencer_reset() why we need
>* a power domain reference here.
>
Re: [Intel-gfx] Missing DPPLL case on i7-1165G7
On Tue, Jan 05, 2021 at 05:50:41AM +, Matthew Wilcox wrote: > On Tue, Dec 29, 2020 at 04:41:31PM +0200, Imre Deak wrote: > > Hi, > > > > On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote: > > > > > > At boot, > > > > > > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon > > > [2.788001] i915 :00:02.0: [drm] *ERROR* LSPCON init failed on > > > port E > > > [2.790752] [ cut here ] > > > [2.790753] Missing case (clock == 539440) > > > [2.790790] WARNING: CPU: 0 PID: 159 at > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2967 > > > icl_get_dplls+0x53a/0xa50 [i915] > > > > the above warn looks to be due to a missing workaround fixed by > > > > commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e > > Author: Imre Deak > > Date: Sat Oct 3 03:18:46 2020 +0300 > > > > drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref > > clock > > > > in drm-tip. Could you give it a try? > > I tried -rc2, which contains that commit, and the problem is gone. Thank > you! Thanks for testing it, I'll send a patch for the 5.10 stable tree as well. > There is a different problem, which is that the brightness buttons > (on F2 and F3 on this laptop) do not actually increase/decrease the > brightness. GNOME pops up a graphic that illustrates it is changing > the brightness, but nothing actually changes. > > xbacklight says "No outputs have backlight property" and using > xrandr --output XWAYLAND0 --brightness 0.0001 doesn't change anything > (for various different values, not just 0.0001). Using xrandr --prop > --verbose shows the reported value of "Brightness" changing, but nothing > has changed on the screen. > > I found > /sys/devices/pci:00/:00:02.0/drm/card0/card0-eDP-1/intel_backlight > and tried setting 'brightness' in there to a few different values (100, > 2000, 19200, 7000) and also nothing changed. > > Any thoughts? One possibility is that from the different backlight methods (DPCD, direct PWM on a CPU pin) the driver selects the incorrect one. Could you provide a log booting with drm.debug=0x1e adding it to a new ticket at https://gitlab.freedesktop.org/drm/intel/-/issues/new?issue or at least in a reply to this thread? Adding Jani for further ideas. --Imre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] v5.10 stable backport request
Stable team, please backport the upstream commit
8f329967d596 ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz
ref clock")
to the v5.10 stable kernel.
Thanks,
Imre
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Re: [Intel-gfx] v5.10 stable backport request
On Wed, Jan 06, 2021 at 07:04:42PM +0100, Greg KH wrote:
> On Wed, Jan 06, 2021 at 07:53:01PM +0200, Imre Deak wrote:
> > Stable team, please backport the upstream commit
> >
> > 8f329967d596 ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for
> > 38.4MHz ref clock")
> >
> > to the v5.10 stable kernel.
>
> I see no such commit id in Linus's kernel :(
Sorry, the commit id correctly is
0e2497e334de42dbaaee8e325241b5b5b34ede7e
--Imre
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout
On Thu, Jan 07, 2021 at 09:01:40AM +0200, Jani Nikula wrote: > On Wed, 09 Dec 2020, Imre Deak wrote: > > For an enabled DSC during HW readout the corresponding power reference > > is taken along the CRTC power domain references in > > get_crtc_power_domains(). Remove the incorrect get ref from the DSI > > encoder hook. > > Does this fix [1] which is v5.11-rc2 on TGL DSI? Yes, looks like it: <4> [199.269612] i915 :00:02.0: i915 raw-wakerefs=1 wakelocks=1 on cleanup ... <7> [199.277233] i915 Wakeref x1 taken at: intel_display_power_get+0x1f/0x60 [i915] intel_modeset_setup_hw_state+0xbcf/0x19b0 [i915] > Should we pick this up for fixes? Yes. Thanks, Imre > BR, > Jani. > > > [1] > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/CI_DIF_538/fi-tgl-dsi/igt@gem_exec_susp...@basic-s0.html > > > > > > > Cc: Vandita Kulkarni > > Cc: Jani Nikula > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/icl_dsi.c | 4 > > 1 file changed, 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > > b/drivers/gpu/drm/i915/display/icl_dsi.c > > index a9439b415603..b3533a32f8ba 100644 > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > > @@ -1616,10 +1616,6 @@ static void gen11_dsi_get_power_domains(struct > > intel_encoder *encoder, > > > > get_dsi_io_power_domains(i915, > > enc_to_intel_dsi(encoder)); > > - > > - if (crtc_state->dsc.compression_enable) > > - intel_display_power_get(i915, > > - intel_dsc_power_domain(crtc_state)); > > } > > > > static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}
On Fri, Jan 08, 2021 at 11:38:04AM +0200, Jani Nikula wrote:
> On Thu, 07 Jan 2021, Anshuman Gupta wrote:
> > We need a power_domain wakeref in pps_{lock,unlock} to prevent
> > a race while resetting pps state in intel_power_sequencer_reset().
> >
> > intel_power_sequencer_reset() need a pps_mutex to access pps_pipe
> > but it can't grab pps_mutex due to deadlock with power_well
> > functions are called while holding pps_mutex.
> > intel_power_sequencer_reset() is called by power_well function
> > associated with legacy platforms like vlv and chv therefore re-use
> > the POWER_DOMAIN_DISPLAY_CORE power domain, which only used
> > by vlv and chv display power domain.
> >
> > This will avoids the unnecessary noise of unrelated power wells
> > in pps_{lock,unlock}.
> >
> > Cc: Jani Nikula
> > Cc: Imre Deak
> > Signed-off-by: Anshuman Gupta
>
> Imre convinced me yesterday on irc that this should work.
>
> Reviewed-by: Jani Nikula
>
> On the surface, this reduces the need to enable/disable the aux power so
> much. It's unnecessary, so it stands to reason to optimize it. We should
> only grab the domain references we actually need.
>
> However, this *also* papers over an issue we've been seeing [1]. We need
> to be aware the root cause for that remains unknown, and needs to be
> figured out.
>
> I presume simply doing aux transfers won't reproduce the problem,
> because that disables the power asynchronously since commit f39194a7a8b9
> ("drm/i915: Disable power asynchronously during DP AUX
> transfers"). Perhaps we wouldn't have seen this at all if pps_unlock()
> also did that as suggested in the commit message.
>
> Anyway, I'd like to get acks or rb's from Imre and Ville before merging
> this.
Looks ok to me:
Acked-by: Imre Deak
>
>
> BR,
> Jani.
>
>
> [1] http://lore.kernel.org/r/20201204081845.26528-1-anshuman.gu...@intel.com
>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8a00e609085f..4f190a82d4ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -895,9 +895,7 @@ pps_lock(struct intel_dp *intel_dp)
> > * See intel_power_sequencer_reset() why we need
> > * a power domain reference here.
> > */
> > - wakeref = intel_display_power_get(dev_priv,
> > -
> > intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> > -
> > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
> > mutex_lock(&dev_priv->pps_mutex);
> >
> > return wakeref;
> > @@ -909,9 +907,7 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> > wakeref)
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > mutex_unlock(&dev_priv->pps_mutex);
> > - intel_display_power_put(dev_priv,
> > -
> > intel_aux_power_domain(dp_to_dig_port(intel_dp)),
> > - wakeref);
> > + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> > return 0;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode
On Tue, Jan 12, 2021 at 08:10:40PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 29, 2020 at 07:22:01PM +0200, Imre Deak wrote:
> > The DP PHY vswing/pre-emphasis level programming the driver does is
> > related to the DPTX -> first LTTPR link segment only. Accordingly it
> > should be only programmed when link training the first LTTPR and kept
> > as-is when training subsequent LTTPRs and the DPRX. For these latter
> > PHYs the vs/pe levels will be set in response to writing the
> > DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
> > TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
> > The above is also described in DP Standard v2.0 under 3.6.6.1.
> >
> > While at it simplify and add the LTTPR that is link trained to the debug
> > message in intel_dp_set_signal_levels().
> >
> > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link
> > training")
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > .../drm/i915/display/intel_dp_link_training.c | 19 +++
> > .../drm/i915/display/intel_dp_link_training.h | 3 ++-
> > 3 files changed, 14 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 88a6033d6867..16c563f1a515 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6057,7 +6057,7 @@ static void intel_dp_process_phy_request(struct
> > intel_dp *intel_dp,
> >
> > intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
> >
> > - intel_dp_set_signal_levels(intel_dp, crtc_state);
> > + intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
> >
> > intel_dp_phy_pattern_update(intel_dp, crtc_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 7876e781f698..d8c6d7054d11 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > }
> >
> > void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state)
> > + const struct intel_crtc_state *crtc_state,
> > + enum drm_dp_phy dp_phy)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u8 train_set = intel_dp->train_set[0];
> > + char phy_name[10];
> >
> > - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> > + drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis
> > level %d%s, at %s\n",
> > train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> > - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
> > - drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> > + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
> > (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> > DP_TRAIN_PRE_EMPHASIS_SHIFT,
> > train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> > - " (max)" : "");
> > + " (max)" : "",
> > + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> >
> > - intel_dp->set_signal_levels(intel_dp, crtc_state);
> > + if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
> > + intel_dp->set_signal_levels(intel_dp, crtc_state);
>
> The function name is a bit misleading now I guess since we're not
> actually setting the signal levels here for the LTTPRs. But since
> the debug print is here I guess we want to still call this. And as
> usual I can't think of a better name for this, so I'm willing
> to accept that slight inconsistency.
Agreed, will try to make that more consistent as a follow up.
Btw, checking again the callers of the above, looks like
intel_dp_process_phy_request() also misses the DPCD write for the vs/pe
settings.
> Reviewed-by: Ville Syrjälä
>
> > }
> >
> > static bool
> > @@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp
Re: [Intel-gfx] [PATCH V3] drm/i915/jsl: Add W/A 1409054076 for JSL
On Wed, May 19, 2021 at 07:48:21PM +0530, Tejas Upadhyay wrote:
> When pipe A is disabled and MIPI DSI is enabled on pipe B,
> the AMT KVMR feature will incorrectly see pipe A as enabled.
> Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
> it set while DSI is enabled on pipe B. No impact to setting it
> all the time.
>
> Changes since V2:
> - Used REG_BIT, ignored pipe A and used sw state check - Jani
> - Made function wrapper - Jani
> Changes since V1:
> - ./dim checkpatch errors addressed
>
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 21 +
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ce544e20f35c..799cacf4cf6e 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1236,15 +1236,34 @@ static void gen11_dsi_pre_enable(struct
> intel_atomic_state *state,
> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> }
>
> +/*
> + * WA 1409054076:JSL,EHL
It's also needed on ICL.
> + * When pipe A is disabled and MIPI DSI is enabled on pipe B,
> + * the AMT KVMR feature will incorrectly see pipe A as enabled.
> + * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
> + * it set while DSI is enabled on pipe B
> + */
> +static void wa_1409054076(struct intel_encoder *encoder,
The name should be more readable something like
icl_apply_kvmr_pipe_a_wa().
> + enum pipe pipe, bool enable)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (IS_JSL_EHL(dev_priv) && pipe == PIPE_B)
Based on the above the platform check should be DISPLAY_VER == 11.
> + intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> + enable ? 0 : IGNORE_KVMR_PIPE_A,
No need to make the clear (ie mask) param conditional.
> + enable ? IGNORE_KVMR_PIPE_A : 0);
> +}
> static void gen11_dsi_enable(struct intel_atomic_state *state,
>struct intel_encoder *encoder,
>const struct intel_crtc_state *crtc_state,
>const struct drm_connector_state *conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
>
> drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
>
> + wa_1409054076(encoder, crtc->pipe, true);
> /* step6d: enable dsi transcoder */
> gen11_dsi_enable_transcoder(encoder);
>
> @@ -1398,7 +1417,9 @@ static void gen11_dsi_disable(struct intel_atomic_state
> *state,
> const struct drm_connector_state *old_conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);
>
> + wa_1409054076(encoder, crtc->pipe, false);
The flag should be cleared after disabling the pipe ie after
gen11_dsi_disable_transcoder().
Would be good to print a debug message during driver loading/resume if
BIOS hasn't set the WA correctly on a DSI output enabled on pipe B
already.
> /* step1: turn off backlight */
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> intel_panel_disable_backlight(old_conn_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 089b5a59bed3..fe01c6e05a45 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8041,6 +8041,7 @@ enum {
> # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
>
> #define CHICKEN_PAR1_1 _MMIO(0x42080)
> +#define IGNORE_KVMR_PIPE_A REG_BIT(23)
> #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
> #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
> #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Fix incorrect assert about pending power domain async-put work
On Wed, Jun 02, 2021 at 02:35:28PM +0530, Anshuman Gupta wrote:
> On 2021-05-26 at 20:07:28 +0530, Imre Deak wrote:
> > It's possible that an already dequeued put_async_work() will release the
> > reference (*) that was put asynchronously after the dequeue happened.
> > This leaves an async-put work pending, without any reference to release.
> > A subsequent async-put may trigger the
> >
> > drm_WARN_ON(!queue_delayed_work(&power_domains->async_put_work));
> >
> > warn due to async_put_work() still pending. To avoid the warn, cancel
> > the pending async_put_work() when releasing the reference at (*) above.
>
> Not able to visulize the race here between __intel_display_power_put_async
> and intel_display_power_put_async_work() considering both are protected by
> power_domains->lock.
>
> queue_delayed_work_on() documentation says following about return value.
> "Return: %false if @work was already on a queue, %true otherwise."
> AFAIU from the doc, queue_delayed_work will return false only when
> work was in queue after dequeued put_async_work() it should return true ?
Yes, and so the WARN is triggered when __intel_display_power_put_async()
tries to queue a work when one is already pending in the queue:
1. get(A)
2. put_async(A) -> queues put_async_work()
3. put_async_work() dequeued, blocking on power_domains->lock
4. get(A) -> grab_async_put_ref(), reacquires the ref that was put in 2.
5. put_async(A) -> queues put_async_work()
6. put_async_work() dequeued in 3. unblocks, releases the ref that was put in
5., put_async_work() queued in 5. still pending in the queue, without
any reference to release.
7. get(A)
8. put_async(A) -> tries to queue put_async_work(), but it's already
pending -> WARN triggers.
The patch avoids the WARN in 8 by cancelling the queued work at 6.
> Thanks,
> Anshuman Gupta.
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/3421
> > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2289
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 2f7d1664c4738..a95bbf23e6b7c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -2263,6 +2263,12 @@ intel_display_power_put_async_work(struct
> > work_struct *work)
> > fetch_and_zero(&power_domains->async_put_domains[1]);
> > queue_async_put_domains_work(power_domains,
> > fetch_and_zero(&new_work_wakeref));
> > + } else {
> > + /*
> > +* Cancel the work that got queued after this one got dequeued,
> > +* since here we released the corresponding async-put reference.
> > +*/
> > + cancel_delayed_work(&power_domains->async_put_work);
> > }
> >
> > out_verify:
> > --
> > 2.27.0
> >
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ddi: Flush encoder power domain ref puts during driver unload
On Thu, May 27, 2021 at 06:40:00PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/3] drm/i915/ddi: Flush encoder power domain > ref puts during driver unload > URL : https://patchwork.freedesktop.org/series/90613/ > State : success Thanks for the review, pushed to drm-intel-next. > > == Summary == > > CI Bug Log - changes from CI_DRM_10138_full -> Patchwork_20207_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_20207_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@feature_discovery@display-3x: > - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb3/igt@feature_discov...@display-3x.html > > * igt@gem_ctx_persistence@legacy-engines-mixed: > - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +6 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html > > * igt@gem_eio@in-flight-contexts-1us: > - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-tglb7/igt@gem_...@in-flight-contexts-1us.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb5/igt@gem_...@in-flight-contexts-1us.html > > * igt@gem_exec_fair@basic-deadline: > - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-glk6/igt@gem_exec_f...@basic-deadline.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-glk9/igt@gem_exec_f...@basic-deadline.html > - shard-apl: NOTRUN -> [FAIL][7] ([i915#2846]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-apl7/igt@gem_exec_f...@basic-deadline.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar > issue >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_reloc@basic-wide-active@rcs0: > - shard-snb: NOTRUN -> [FAIL][10] ([i915#2389]) +2 similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-snb2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html > > * igt@gem_exec_suspend@basic-s3: > - shard-kbl: NOTRUN -> [DMESG-WARN][11] ([i915#180]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-kbl1/igt@gem_exec_susp...@basic-s3.html > > * igt@gem_mmap_gtt@cpuset-basic-small-copy: > - shard-apl: [PASS][12] -> [INCOMPLETE][13] ([i915#3468]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-apl6/igt@gem_mmap_...@cpuset-basic-small-copy.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-apl8/igt@gem_mmap_...@cpuset-basic-small-copy.html > - shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#198] / > [i915#3468]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-skl10/igt@gem_mmap_...@cpuset-basic-small-copy.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-skl3/igt@gem_mmap_...@cpuset-basic-small-copy.html > > * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: > - shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#3468]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-iclb6/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-iclb3/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html > > * igt@gem_mmap_gtt@cpuset-big-copy-odd: > - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#307]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-iclb5/igt@gem_mmap_...@cpuset-big-copy-odd.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-iclb5/igt@gem_mmap_...@cpuset-big-copy-odd.html > > * igt@gem_mmap_gtt@cpuset-medium-copy-xy: > - shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#3468] / > [i915#750]) >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-tglb7/igt@gem_mmap_...@cpuset-medium-copy-xy.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb1/igt@gem_mmap_...@cpuset-medium-copy-xy.html > > * igt@gem_mmap_gtt@fault-concurrent-x: > - shard-skl: NOTRUN -> [INCOMPLETE][22] ([i915#198] / > [i915#3468]) >[22]: > https://intel-gfx-ci.01.org/tree/d
Re: [Intel-gfx] [PATCH] drm/i915/display: remove duplicated argument
On Sat, Jun 05, 2021 at 11:22:07AM +0800, Wan Jiabing wrote: > Fix the following coccicheck warning: > > ./drivers/gpu/drm/i915/display/intel_display_power.c:3081:1-28: > duplicated argument to & or | > > This commit fixes duplicate argument. It might be a typo. > But what I can do is to remove it now. > > Signed-off-by: Wan Jiabing Thanks, pushed to drm-intel-next. > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index 3e1f6ec61514..4298ae684d7d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -3078,7 +3078,6 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\ > BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \ > BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \ > - BIT_ULL(POWER_DOMAIN_AUX_C) | \ > BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \ > BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \ > BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \ > -- > 2.20.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/adlp: Fix AUX power well -> PHY mapping
On Wed, Jun 09, 2021 at 02:42:04PM +0300, Jani Nikula wrote:
> On Wed, 26 May 2021, Imre Deak wrote:
> > On ADL_P the power well->PHY mapping doesn't follow the mapping on previous
> > platforms, fix this up.
> >
> > While at it remove the redundant dev_priv param from
> > icl_tc_phy_aux_ch().
> >
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_power.c| 34 ++-
> > 1 file changed, 18 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index a95bbf23e6b7c..7ddd63114b36b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -291,8 +291,7 @@ static void hsw_power_well_pre_disable(struct
> > drm_i915_private *dev_priv,
> > #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> > ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> >
> > -static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> > -struct i915_power_well *power_well)
> > +static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well
> > *power_well)
> > {
> > int pw_idx = power_well->desc->hsw.idx;
> >
> > @@ -327,6 +326,15 @@ aux_ch_to_digital_port(struct drm_i915_private
> > *dev_priv,
> > return dig_port;
> > }
> >
> > +static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
> > + const struct i915_power_well *power_well)
> > +{
> > + enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> > + struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915,
> > aux_ch);
>
> Replying to an already merged patch...
>
> aux_ch_to_digital_port() may return NULL but we don't really check this
> anywhere.
>
> Any thoughts how this should be handled?
It would be a bug in the driver and oops right after calling the
function. I wouldn't bother adding an extra check for this, but instead
the function could WARN() and return a default non-NULL SST DP
intel_digital_port.
>
> BR,
> Jani.
>
>
> > +
> > + return intel_port_to_phy(i915, dig_port->base.port);
> > +}
> > +
> > static void hsw_wait_for_power_well_enable(struct drm_i915_private
> > *dev_priv,
> >struct i915_power_well *power_well,
> >bool timeout_expected)
> > @@ -468,15 +476,13 @@ static void hsw_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > hsw_wait_for_power_well_disable(dev_priv, power_well);
> > }
> >
> > -#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> > -
> > static void
> > icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > int pw_idx = power_well->desc->hsw.idx;
> > - enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> > + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> > u32 val;
> >
> > drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> > @@ -508,7 +514,7 @@ icl_combo_phy_aux_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > {
> > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > int pw_idx = power_well->desc->hsw.idx;
> > - enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> > + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> > u32 val;
> >
> > drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> > @@ -595,7 +601,7 @@ static void
> > icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > - enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> > + enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> > struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv,
> > aux_ch);
> > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > bool is_tbt = power_well->desc->hsw.is_tc_tbt;
> > @@ -643,7 +649,7 @@ static void
> > icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
>
[Intel-gfx] [PATCH] drm/i915: Force a TypeC PHY disconnect during suspend/shutdown
Disconnect TypeC PHYs during system suspend and shutdown, even with the
corresponding TypeC sink still plugged to its connector, since leaving
the PHY connected causes havoc at least during system resume in the
presence of an Nvidia card.
Note that this will only make a difference in the TypeC DP alternate
mode, since in Thunderbolt alternate mode the PHY is never owned by the
display engine and there is no notion of PHY ownership in legacy mode
(the display engine being the only possible owner in that mode and the
TypeC subsystem not having anything to do with the port in that case).
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3500
Reported-and-tested-by: Chris Chiu
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++--
drivers/gpu/drm/i915/display/intel_tc.c | 34 +++-
drivers/gpu/drm/i915/display/intel_tc.h | 2 ++
3 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 390869bd6b633..7e25d0f80b78f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4496,6 +4496,36 @@ static bool intel_ddi_is_tc(struct drm_i915_private
*i915, enum port port)
return false;
}
+static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ intel_dp_encoder_suspend(encoder);
+
+ if (!intel_phy_is_tc(i915, phy))
+ return;
+
+ intel_tc_port_disconnect_phy(dig_port);
+}
+
+void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ intel_dp_encoder_shutdown(encoder);
+
+ if (!intel_phy_is_tc(i915, phy))
+ return;
+
+ intel_tc_port_disconnect_phy(dig_port);
+}
+
#define port_tc_name(port) ((port) - PORT_TC1 + '1')
#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
@@ -4605,8 +4635,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
- encoder->suspend = intel_dp_encoder_suspend;
- encoder->shutdown = intel_dp_encoder_shutdown;
+ encoder->suspend = intel_ddi_encoder_suspend;
+ encoder->shutdown = intel_ddi_encoder_shutdown;
encoder->get_power_domains = intel_ddi_get_power_domains;
encoder->type = INTEL_OUTPUT_DDI;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index c23c210a55f5c..3ffece568ed98 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -556,7 +556,7 @@ intel_tc_port_get_target_mode(struct intel_digital_port
*dig_port)
}
static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
-int required_lanes)
+int required_lanes, bool force_disconnect)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
@@ -572,7 +572,8 @@ static void intel_tc_port_reset_mode(struct
intel_digital_port *dig_port,
}
icl_tc_phy_disconnect(dig_port);
- icl_tc_phy_connect(dig_port, required_lanes);
+ if (!force_disconnect)
+ icl_tc_phy_connect(dig_port, required_lanes);
drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n",
dig_port->tc_port_name,
@@ -662,7 +663,7 @@ bool intel_tc_port_connected(struct intel_encoder *encoder)
}
static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
-int required_lanes)
+int required_lanes, bool force_disconnect)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t wakeref;
@@ -676,8 +677,9 @@ static void __intel_tc_port_lock(struct intel_digital_port
*dig_port,
tc_cold_wref = tc_cold_block(dig_port);
- if (intel_tc_port_needs_reset(dig_port))
- intel_tc_port_reset_mode(dig_port, required_lanes);
+ if (force_disconnect || intel_tc_port_needs_reset
Re: [Intel-gfx] [PATCH V5] drm/i915/jsl: Add W/A 1409054076 for JSL
On Mon, Jun 14, 2021 at 05:18:51PM +0530, Tejas Upadhyay wrote:
> When pipe A is disabled and MIPI DSI is enabled on pipe B,
> the AMT KVMR feature will incorrectly see pipe A as enabled.
> Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
> it set while DSI is enabled on pipe B. No impact to setting
> it all the time.
>
> Changes since V4:
> - Modified function comment Wa_:icl,jsl,ehl - Lucas
> - Modified debug message in sync state - Imre
> Changes since V3:
> - More meaningful name to workaround - Imre
> - Remove boolean check clear flag
> - Add WA_verify hook in dsi sync_state
> Changes since V2:
> - Used REG_BIT, ignored pipe A and used sw state check - Jani
> - Made function wrapper - Jani
> Changes since V1:
> - ./dim checkpatch errors addressed
>
> Cc: Imre Deak
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 44 ++
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> 2 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 16812488c5dd..17e318eb1ad0 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1253,15 +1253,37 @@ static void gen11_dsi_pre_enable(struct
> intel_atomic_state *state,
> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> }
>
> +/*
> + * Wa_1409054076:icl,jsl,ehl
> + * When pipe A is disabled and MIPI DSI is enabled on pipe B,
> + * the AMT KVMR feature will incorrectly see pipe A as enabled.
> + * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
> + * it set while DSI is enabled on pipe B
> + */
> +static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
> + enum pipe pipe, bool enable)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if ((DISPLAY_VER(dev_priv) == 11) && pipe == PIPE_B) {
Redundant braces around a single simple statement.
> + intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> + IGNORE_KVMR_PIPE_A,
> + enable ? IGNORE_KVMR_PIPE_A : 0);
> + }
> +}
> static void gen11_dsi_enable(struct intel_atomic_state *state,
>struct intel_encoder *encoder,
>const struct intel_crtc_state *crtc_state,
>const struct drm_connector_state *conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
>
> drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
>
> + /* Wa_1409054076:icl,jsl,ehl */
> + icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
> +
> /* step6d: enable dsi transcoder */
> gen11_dsi_enable_transcoder(encoder);
>
> @@ -1415,6 +1437,7 @@ static void gen11_dsi_disable(struct intel_atomic_state
> *state,
> const struct drm_connector_state *old_conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);
>
> /* step1: turn off backlight */
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> @@ -1423,6 +1446,9 @@ static void gen11_dsi_disable(struct intel_atomic_state
> *state,
> /* step2d,e: disable transcoder and wait */
> gen11_dsi_disable_transcoder(encoder);
>
> + /* Wa_1409054076:icl,jsl,ehl */
> + icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
> +
> /* step2f,g: powerdown panel */
> gen11_dsi_powerdown_panel(encoder);
>
> @@ -1548,6 +1574,23 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
> pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
> }
>
> +static void gen11_dsi_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum pipe pipe = intel_crtc->pipe;
> +
> + /* wa verify 1409054076:icl,jsl,ehl */
> + if ((DISPLAY_VER(dev_priv) == 11) && pipe == PIPE_B &&
> + !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_P
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Force a TypeC PHY disconnect during suspend/shutdown
On Thu, Jun 10, 2021 at 09:28:31PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Force a TypeC PHY disconnect during suspend/shutdown > URL : https://patchwork.freedesktop.org/series/91345/ > State : failure Thanks for the report, testing and review. Pushed to drm-intel-next with the missing static fn sparse error fixed. Lakshmi, could you look at the unrelated issues below? > > == Summary == > > CI Bug Log - changes from CI_DRM_10205_full -> Patchwork_20334_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_20334_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_20334_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_20334_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_exec_whisper@basic-forked: > - shard-tglb: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10205/shard-tglb2/igt@gem_exec_whis...@basic-forked.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-tglb7/igt@gem_exec_whis...@basic-forked.html No TypeC sinks connected to this system, nor any suspend tests ran before this failure: [21.819973] Initializing watchdogs [21.820092] /dev/watchdog0 [21.825864] [001/129] (960s left) gem_exec_schedule (deep) Starting subtest: deep Starting dynamic subtest: rcs0 Dynamic subtest rcs0: SUCCESS (7.361s) Starting dynamic subtest: bcs0 Dynamic subtest bcs0: SUCCESS (7.596s) Starting dynamic subtest: vcs0 Dynamic subtest vcs0: SUCCESS (7.442s) Starting dynamic subtest: vcs1 Dynamic subtest vcs1: SUCCESS (7.491s) Starting dynamic subtest: vecs0 Dynamic subtest vecs0: SUCCESS (7.501s) Subtest deep: SUCCESS (37.391s) [59.664849] [002/129] (922s left) gem_exec_whisper (basic-forked) No pstore logs available either, so just guessing that it may be related to one of: https://gitlab.freedesktop.org/drm/intel/-/issues/2263 https://gitlab.freedesktop.org/drm/intel/-/issues/3488 > Known issues > > > Here are the changes found in Patchwork_20334_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_ctx_persistence@clone: > - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 > similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-snb5/igt@gem_ctx_persiste...@clone.html > > * igt@gem_eio@in-flight-suspend: > - shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +2 > similar issues >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10205/shard-kbl1/igt@gem_...@in-flight-suspend.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-kbl7/igt@gem_...@in-flight-suspend.html > > * igt@gem_exec_fair@basic-deadline: > - shard-apl: NOTRUN -> [FAIL][6] ([i915#2846]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-apl8/igt@gem_exec_f...@basic-deadline.html > > * igt@gem_exec_fair@basic-flow@rcs0: > - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +51 similar > issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-skl1/igt@gem_exec_fair@basic-f...@rcs0.html > > * igt@gem_exec_fair@basic-none-share@rcs0: > - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10205/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html > > * igt@gem_exec_fair@basic-none@vecs0: > - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar > issue >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10205/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-kbl6/igt@gem_exec_fair@basic-n...@vecs0.html > > * igt@gem_exec_fair@basic-pace-solo@rcs0: > - shard-kbl: NOTRUN -> [FAIL][12] ([i915#2842]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10205/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20334/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html > > * igt@gem_ex
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request
On Mon, Oct 04, 2021 at 08:05:33PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print out each DP vswing adjustment request we got from the RX.
> Could help in diagnosing what's going on during link training.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> .../drm/i915/display/intel_dp_link_training.c | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 6bab097cafd2..5657be1461ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -343,14 +343,41 @@ static u8 intel_dp_get_lane_adjust_train(struct
> intel_dp *intel_dp,
> return v | p;
> }
>
> +#define TRAIN_REQ_FMT "%d/%d/%d/%d"
> +#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
> + (drm_dp_get_adjust_request_voltage((link_status), (lane)) >>
> DP_TRAIN_VOLTAGE_SWING_SHIFT)
> +#define TRAIN_REQ_VSWING_ARGS(link_status) \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 3)
> +#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
> + (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >>
> DP_TRAIN_PRE_EMPHASIS_SHIFT)
> +#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
> +
> void
> intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy,
> const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + char phy_name[10];
> int lane;
>
> + drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
> + "vswing request: " TRAIN_REQ_FMT ", "
> + "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
> + encoder->base.base.id, encoder->base.name,
> + crtc_state->lane_count,
> + TRAIN_REQ_VSWING_ARGS(link_status),
> + TRAIN_REQ_PREEMPH_ARGS(link_status),
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> +
> for (lane = 0; lane < 4; lane++)
> intel_dp->train_set[lane] =
> intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
> --
> 2.32.0
>
Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints
On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Unify all debug prints during link training to include information
> on both the encoder and the LTTPR. We unify the format to something
> like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
> sure if those brackets around the dp_phy just make it look like
> line noise? I'll accept suggestions on better formatting.
>
> I'm slightly on the fence about also including the connector,
> but technically only the DPRX is the SST connector (ie.
> intel_dp->attached_connector). I suppose you could think of it
> as the branch device/whatever in the topology, and we're training
> the link leading to it. So that could argue for its inclusion.
> But it's all getting a bit long alrady, so not going to do it
> I think.
Imo including the connector info eventually would be good to be able to
match these lines with those only showing the connector, or connectors
in i915_display_info etc.
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> .../drm/i915/display/intel_dp_link_training.c | 167 +++---
> 1 file changed, 106 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 5657be1461ec..18f4b469766e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -25,15 +25,6 @@
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
>
> -static void
> -intel_dp_dump_link_status(struct drm_device *drm,
> - const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - drm_dbg_kms(drm,
> - "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x
> adj_req2_3:0x%x\n",
> - link_status[0], link_status[1], link_status[2],
> - link_status[3], link_status[4], link_status[5]);
> -}
>
> static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
> {
> @@ -66,6 +57,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp
> *intel_dp,
> static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
>enum drm_dp_phy dp_phy)
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
> char phy_name[10];
>
> @@ -73,21 +65,22 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp
> *intel_dp,
>
> if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "failed to read the PHY caps for %s\n",
> - phy_name);
> + "[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
> + encoder->base.base.id, encoder->base.name,
> phy_name);
> return;
> }
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "%s PHY capabilities: %*ph\n",
> - phy_name,
> + "[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
> + encoder->base.base.id, encoder->base.name, phy_name,
> (int)sizeof(intel_dp->lttpr_phy_caps[0]),
> phy_caps);
> }
>
> static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> if (intel_dp_is_edp(intel_dp))
> return false;
> @@ -104,7 +97,8 @@ static bool intel_dp_read_lttpr_common_caps(struct
> intel_dp *intel_dp)
> goto reset_caps;
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "LTTPR common capabilities: %*ph\n",
> + "[ENCODER:%d:%s] LTTPR common capabilities: %*ph\n",
> + encoder->base.base.id, encoder->base.name,
> (int)sizeof(intel_dp->lttpr_common_caps),
> intel_dp->lttpr_common_caps);
>
> @@ -130,6 +124,8 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp
> *intel_dp, bool enable)
>
> static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures
On Mon, Oct 04, 2021 at 08:05:35PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I suppose intel_dp_dump_link_status() might be useful for diagnosing
> link training failures. Hoever we only call from the channel EQ phase
> currently. Let's call it from the CR phase as well.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 18f4b469766e..c92044710012 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -649,6 +649,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
> int voltage_tries, cr_tries, max_cr_tries;
> + u8 link_status[DP_LINK_STATUS_SIZE];
> bool max_vswing_reached = false;
> char phy_name[10];
>
> @@ -678,8 +679,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
>
> voltage_tries = 1;
> for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> - u8 link_status[DP_LINK_STATUS_SIZE];
> -
> intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
>
> if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> @@ -697,6 +696,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> }
>
> if (voltage_tries == 5) {
> + intel_dp_dump_link_status(intel_dp, dp_phy,
> link_status);
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s][%s] Same voltage tried 5
> times\n",
> encoder->base.base.id, encoder->base.name,
> phy_name);
> @@ -704,6 +704,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> }
>
> if (max_vswing_reached) {
> + intel_dp_dump_link_status(intel_dp, dp_phy,
> link_status);
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s][%s] Max Voltage Swing
> reached\n",
> encoder->base.base.id, encoder->base.name,
> phy_name);
> @@ -732,6 +733,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> max_vswing_reached = true;
> }
>
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_err(&i915->drm,
> "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving
> up!\n",
> encoder->base.base.id, encoder->base.name, phy_name,
> max_cr_tries);
> --
> 2.32.0
>
[Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers
This patchset adds a descriptor table for all modifiers used by i915, which deduplicates the listing of supported modifiers during plane initialization and during checking for a modifier support on a plane. This also simplifies getting some modifier attributes like checking if a plane is a CCS modifier. The motivation is to make it easier to add and maintain new CCS modifier sets, which will be needed for at least ADL-P and another upcoming platform. Tested with igt/kms_plane,kms_ccs on CHV,HSW,TGL,ADLP. The patches are also avaiable at: https://github.com/ideak/linux/commits/modifier-descriptors Imre Deak (11): drm/i915: Add a table with a descriptor for all i915 modifiers drm/i915: Move intel_get_format_info() to intel_fb.c drm/i915: Add tiling attribute to the modifier descriptor drm/i915: Simplify the modifier check for interlaced scanout support drm/i915: Unexport is_semiplanar_uv_plane() drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c drm/i915: Add a platform independent way to get the RC CCS CC plane drm/i915: Handle CCS CC planes separately from CCS control planes drm/i915: Add a platform independent way to check for CCS control planes drm/i915: Move is_ccs_modifier() to intel_fb.c drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 150 + drivers/gpu/drm/i915/display/intel_display.h | 4 - .../drm/i915/display/intel_display_types.h| 17 - drivers/gpu/drm/i915/display/intel_fb.c | 536 -- drivers/gpu/drm/i915/display/intel_fb.h | 25 +- drivers/gpu/drm/i915/display/intel_sprite.c | 35 +- drivers/gpu/drm/i915/display/skl_scaler.c | 1 + .../drm/i915/display/skl_universal_plane.c| 165 +- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/intel_pm.c | 1 + 12 files changed, 569 insertions(+), 388 deletions(-) -- 2.27.0
[Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 178 ++
drivers/gpu/drm/i915/display/intel_fb.h | 8 +
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 137 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
8 files changed, 218 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f64..bcd44ff30ce5b 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
};
-static const u64 cursor_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
@@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane,
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- return modifier == DRM_FORMAT_MOD_LINEAR &&
- format == DRM_FORMAT_ARGB;
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
+ return false;
+
+ return format == DRM_FORMAT_ARGB;
}
static int
@@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
{
struct intel_plane *cursor;
int ret, zpos;
+ u64 *modifiers;
cursor = intel_plane_alloc();
if (IS_ERR(cursor))
@@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
cursor->cursor.size = ~0;
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
+
ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
0, &intel_cursor_plane_funcs,
intel_cursor_formats,
ARRAY_SIZE(intel_cursor_formats),
- cursor_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_CURSOR,
"cursor %c", pipe_name(pipe));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 21ce8bccc645a..bb53b01f07aee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1336,7 +1336,6 @@ struct intel_plane {
enum plane_id id;
enum pipe pipe;
bool has_fbc;
- bool has_ccs;
bool need_async_flip_disable_wa;
u32 frontbuffer_bit;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index fa1f375e696bf..aefae988b620b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -13,6 +13,184 @@
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >=
ARRAY_SIZE(a))
+const struct intel_modifier_desc {
+ u64 id;
+ u64 display_versions;
+
+ struct {
+#define INTEL_CCS_RC BIT(0)
+#define INTEL_CCS_RC_CCBIT(1)
+#define INTEL_CCS_MC BIT(2)
+
+#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
+ u8 type:3;
+ } ccs;
+} intel_modifiers[] = {
+ {
+ .id = DRM_FORMAT_MOD_LINEAR,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ },
+ {
+ .id = I915_FORMAT_MOD_X_TILED,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 13),
+ },
+ {
+ .id = I915_FORMAT_MOD_Yf_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_CCS,
+
[Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +---
drivers/gpu/drm/i915/display/intel_fb.c | 155 +++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 159 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbba..90802d16fbf91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P012, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P016, .num_planes = 4,
-
[Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 2543232580885..ef3cd375c9942 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -115,6 +115,7 @@ const struct intel_modifier_desc {
u64 display_versions;
const struct drm_format_info *formats;
int format_count;
+ u8 tiling;
struct {
#define INTEL_CCS_RC BIT(0)
@@ -132,10 +133,12 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_X_TILED,
.display_versions = DISPLAY_VER_MASK_ALL,
+ .tiling = I915_TILING_X,
},
{
.id = I915_FORMAT_MOD_Y_TILED,
.display_versions = DISPLAY_VER_MASK(9, 13),
+ .tiling = I915_TILING_Y,
},
{
.id = I915_FORMAT_MOD_Yf_TILED,
@@ -144,6 +147,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -160,6 +164,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -168,6 +173,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -176,6 +182,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -556,18 +563,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
[Intel-gfx] [PATCH 04/11] drm/i915: Simplify the modifier check for interlaced scanout support
Checking the modifiers that support interlacing makes the condition
simpler and avoids us having to add new modifiers to the list (presuming
all/most of the new modifiers won't support interlacing).
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index cebd688ab1a22..4f0dbb00ea28c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1240,13 +1240,8 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
/* Y-tiling is not supported in IF-ID Interlace mode */
if (crtc_state->hw.enable &&
crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
- (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
+ fb->modifier != DRM_FORMAT_MOD_LINEAR &&
+ fb->modifier != I915_FORMAT_MOD_X_TILED) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
--
2.27.0
[Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane()
This function is only used by intel_fb.c, so unexport it.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index ef3cd375c9942..19aa99375502a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -372,7 +372,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer
*fb, int plane)
plane == 2;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 67c20451ae63f..a198914c0088b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -25,7 +25,6 @@ struct intel_plane_state;
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id);
--
2.27.0
[Intel-gfx] [PATCH 08/11] drm/i915: Handle CCS CC planes separately from CCS control planes
CCS CC planes are quite different from CCS control planes, even though
we regard the CC planes as a linear buffer having a 64 byte stride.
Thus it's clearer to check for either CCS plane types explicitly when we
need to handle them; add the required CCS CC planes check here, while
the next patch will change all is_ccs_plane()/is_gen12_ccs_plane()
checks to consider only the CCS control planes.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index f18fab9c3b941..e8fe198b1b6a1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -432,7 +432,8 @@ static bool is_semiplanar_uv_plane(const struct
drm_framebuffer *fb, int color_p
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
- is_gen12_ccs_plane(fb, color_plane);
+ is_gen12_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane);
}
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -525,7 +526,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (is_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane))
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
--
2.27.0
[Intel-gfx] [PATCH 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
Move intel_format_info_is_yuv_semiplanar() to intel_fb.c . The number of
planes for YUV semiplanar formats using CCS modifiers will change on
future platforms. We can use the modifier descriptors to simplify
getting the plane numbers for all modifiers, prepare for that here.
Signed-off-by: Imre Deak
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 8 -
drivers/gpu/drm/i915/display/intel_display.h | 4 ---
drivers/gpu/drm/i915/display/intel_fb.c | 30 +++
drivers/gpu/drm/i915/display/intel_fb.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 1 +
6 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 47234d8985490..0eb7323717d30 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_pm.h"
#include "intel_sprite.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 90802d16fbf91..8043a9fd665a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -821,14 +821,6 @@ void intel_disable_transcoder(const struct
intel_crtc_state *old_crtc_state)
intel_wait_for_pipe_off(old_crtc_state);
}
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier)
-{
- return info->is_yuv &&
- info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
-}
-
unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info)
{
unsigned int size = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 3028072c2cf35..84ae8b555ea0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -619,10 +619,6 @@ void ilk_pfit_disable(const struct intel_crtc_state
*old_crtc_state);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state);
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
struct intel_encoder *
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 19aa99375502a..f0d8c848b23e1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -353,6 +353,36 @@ bool intel_fb_plane_supports_modifier(struct intel_plane
*plane, u64 modifier)
return false;
}
+static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
+const struct drm_format_info *info)
+{
+ int yuv_planes;
+
+ if (!info->is_yuv)
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_ANY))
+ yuv_planes = 4;
+ else
+ yuv_planes = 2;
+
+ return info->num_planes == yuv_planes;
+}
+
+/**
+ * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV
semiplanar
+ * @info: format to check
+ * @modifier: modifier used with the format
+ *
+ * Returns:
+ * %true if @info / @modifier is YUV semiplanar.
+ */
+bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+u64 modifier)
+{
+ return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
+}
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index a198914c0088b..d9693fc767c54 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -33,6 +33,10 @@ bool intel_fb_plane_supports_modifier(struct intel_plane
*plane, u64 modifier);
const struct drm_format_info *
intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+bool
+intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+ u64 modifier);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8dbf8ec0d8905..bafcac58ac096 100644
--- a/drivers/gpu/drm/i915/in
[Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
Future platforms change the location of CCS control planes in CCS
framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in control planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 73 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c| 3 +-
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bb53b01f07aee..b4b6a31caf4e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index e8fe198b1b6a1..392f89e659eb6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -125,6 +125,8 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_ctrl_planes:4;
+ u8 planar_ctrl_planes:4;
} ccs;
} intel_modifiers[] = {
{
@@ -151,6 +153,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -159,6 +162,7 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -168,6 +172,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -177,6 +182,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_ctrl_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -187,6 +193,8 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_ctrl_planes = BIT(1),
+ .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -385,17 +393,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
+ const struct drm_format_info *format)
{
- if (!is_ccs_modifier(fb->modifier))
- return false;
+ if (format_is_yuv_semiplanar(md, format))
+ return md->ccs.planar_ctrl_planes;
+ else
+ return md->ccs.packed_ctrl_planes;
+}
+
+/**
+ * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS
control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a CCS control plane.
+ */
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
- return plane >= fb->format->num_planes / 2;
+ return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+/**
+ * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer
[Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane
On future platforms the index of the color-clear plane will change from
the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve
the index independently of the platform/modifier.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +---
drivers/gpu/drm/i915/display/intel_fb.c | 25 ++--
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8043a9fd665a5..bfb9120cb31ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10031,10 +10031,14 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct drm_framebuffer *fb = plane_state->hw.fb;
+ int cc_plane;
int ret;
- if (!fb ||
- fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (!fb)
+ continue;
+
+ cc_plane = intel_fb_rc_ccs_cc_plane(fb);
+ if (cc_plane < 0)
continue;
/*
@@ -10051,7 +10055,7 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
* GPU write on it.
*/
ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
-fb->offsets[2] + 16,
+fb->offsets[cc_plane] + 16,
&plane_state->ccval,
sizeof(plane_state->ccval));
/* The above could only fail if the FB obj has an unexpected
backing store type. */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index f0d8c848b23e1..f18fab9c3b941 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -124,6 +124,7 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
+ u8 cc_planes:3;
} ccs;
} intel_modifiers[] = {
{
@@ -176,6 +177,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
@@ -396,10 +398,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb,
int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+/**
+ * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
+ * @fb: Framebuffer
+ *
+ * Returns:
+ * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
+ * framebuffer using a render compression/color clear modifier.
+ */
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ if (!md->ccs.cc_planes)
+ return -1;
+
+ drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
+
+ return ilog2((int)md->ccs.cc_planes);
+}
+
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
- return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
- plane == 2;
+ return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index d9693fc767c54..5affcc834e045 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -26,6 +26,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int
plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
+
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
--
2.27.0
[Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c
Move the function to intel_fb.c and rename it adding the intel_fb_
prefix following the naming of exported functions.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 9 --
drivers/gpu/drm/i915/display/intel_fb.c | 29 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 12
4 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b4b6a31caf4e3..f38b70ef6afaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2041,13 +2041,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 392f89e659eb6..b68bda0845c56 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -251,6 +251,19 @@ static bool is_ccs_type_modifier(const struct
intel_modifier_desc *md, u8 ccs_ty
return md->ccs.type & ccs_type;
}
+/**
+ * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier.
+ */
+bool intel_fb_is_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
+}
+
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
@@ -473,7 +486,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb,
int color_plane)
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
(main_plane && main_plane >= fb->format->num_planes / 2));
return fb->format->num_planes / 2 + main_plane;
@@ -481,7 +494,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int
main_plane)
int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
if (is_gen12_ccs_cc_plane(fb, ccs_plane))
@@ -526,7 +539,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb,
int main_plane)
{
struct drm_i915_private *i915 = to_i915(fb->dev);
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
@@ -1090,7 +1103,7 @@ static bool intel_plane_can_remap(const struct
intel_plane_state *plane_state)
* The new CCS hash mode isn't compatible with remapping as
* the virtual address of the pages affects the compressed data.
*/
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return false;
/* Linear needs a page aligned stride for remapping */
@@ -1497,7 +1510,7 @@ static void intel_plane_remap_gtt(struct
intel_plane_state *plane_state)
src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier));
+ drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
drm_rect_translate(&plane_state->uapi.src,
@@ -1560,7 +1573,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
intel_modifier_uses_dpt(dev_priv, modifier))
return intel_plane_fb_max_stride(dev_priv, pixel_for
[Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
Instead of open-coding the checks add functions for this, simplifying
the handling of CCS modifiers on future platforms.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 4 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index b68bda0845c56..e8d37f0678741 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -264,6 +264,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
}
+/**
+ * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC
modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render with color clear modifier.
+ */
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC);
+}
+
+/**
+ * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a media compression modifier.
+ */
+bool intel_fb_is_mc_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC);
+}
+
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index af8097699dac5..cb5bc6304011a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -23,6 +23,8 @@ struct intel_plane;
struct intel_plane_state;
bool intel_fb_is_ccs_modifier(u64 modifier);
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
+bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d29ad180f8477..9cff6cc2bdf4f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1067,7 +1067,7 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
intel_uncore_write64_fw(&dev_priv->uncore,
PLANE_CC_VAL(pipe, plane_id),
plane_state->ccval);
@@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
- if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ if (intel_fb_is_mc_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
--
2.27.0
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h| 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++
> > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c| 137 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 8 files changed, 218 insertions(+), 164 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB,
> > };
> >
> > -static const u64 cursor_format_modifiers[] = {
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct
> > intel_plane *plane,
> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > - format == DRM_FORMAT_ARGB;
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > + return false;
> > +
> > + return format == DRM_FORMAT_ARGB;
> > }
> >
> > static int
> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private
> > *dev_priv,
> > {
> > struct intel_plane *cursor;
> > int ret, zpos;
> > + u64 *modifiers;
> >
> > cursor = intel_plane_alloc();
> > if (IS_ERR(cursor))
> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private
> > *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > cursor->cursor.size = ~0;
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> >0, &intel_cursor_plane_funcs,
> >intel_cursor_formats,
> >ARRAY_SIZE(intel_cursor_formats),
> > - cursor_format_modifiers,
> > + modifiers,
> >DRM_PLANE_TYPE_CURSOR,
> >"cursor %c", pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645a..bb53b01f07aee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > enum plane_id id;
> > enum pipe pipe;
> > bool has_fbc;
> > - bool has_ccs;
> > bool need_async_flip_disable_wa;
> > u32 frontbuffer_bit;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index fa1f375e696bf..aefae988b620b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,6 +13,184 @@
> >
> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >=
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Fri, Oct 08, 2021 at 12:32:57AM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 12:26:11AM +0300, Imre Deak wrote:
> > On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > > > Add a table describing all the framebuffer modifiers used by i915 at one
> > > > place. This has the benefit of deduplicating the listing of supported
> > > > modifiers for each platform and checking the support of these modifiers
> > > > on a given plane. This also simplifies in a similar way getting some
> > > > attribute for a modifier, for instance checking if the modifier is a
> > > > CCS modifier type.
> > > >
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > > > .../drm/i915/display/intel_display_types.h| 1 -
> > > > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++
> > > > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > > > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > > > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > > > .../drm/i915/display/skl_universal_plane.c| 137 +-
> > > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > > 8 files changed, 218 insertions(+), 164 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > > > DRM_FORMAT_ARGB,
> > > > };
> > > >
> > > > -static const u64 cursor_format_modifiers[] = {
> > > > - DRM_FORMAT_MOD_LINEAR,
> > > > - DRM_FORMAT_MOD_INVALID
> > > > -};
> > > > -
> > > > static u32 intel_cursor_base(const struct intel_plane_state
> > > > *plane_state)
> > > > {
> > > > struct drm_i915_private *dev_priv =
> > > > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct
> > > > intel_plane *plane,
> > > > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > > > u32 format, u64 modifier)
> > > > {
> > > > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > > > - format == DRM_FORMAT_ARGB;
> > > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane),
> > > > modifier))
> > > > + return false;
> > > > +
> > > > + return format == DRM_FORMAT_ARGB;
> > > > }
> > > >
> > > > static int
> > > > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private
> > > > *dev_priv,
> > > > {
> > > > struct intel_plane *cursor;
> > > > int ret, zpos;
> > > > + u64 *modifiers;
> > > >
> > > > cursor = intel_plane_alloc();
> > > > if (IS_ERR(cursor))
> > > > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private
> > > > *dev_priv,
> > > > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) ||
> > > > HAS_CUR_FBC(dev_priv))
> > > > cursor->cursor.size = ~0;
> > > >
> > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe,
> > > > cursor->id);
> > > > +
> > > > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > > >0, &intel_cursor_plane_funcs,
> > > >intel_cursor_formats,
> > > >ARRAY_SIZE(intel_cursor_formats),
> > > > - cursor_format_modifiers,
> > > > + modifiers,
> > > >DRM_PLANE_TYPE_CURSOR,
> > > >"cursor %c", pipe_name(pipe));
> > > > +
> > > &g
[Intel-gfx] [PATCH v2 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
userspace.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +--
drivers/gpu/drm/i915/display/intel_fb.c | 163 +++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 167 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbba..90802d16fbf91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P012, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2,
[Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
v2:
- Keep the plane caps calculation in the plane code and pass an enum
with these caps to intel_fb_get_modifiers(). (Ville)
- Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
well.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 143 ++
drivers/gpu/drm/i915/display/intel_fb.h | 16 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 181 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
9 files changed, 245 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67b..a939accff7ee2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
DRM_FORMAT_XBGR16161616F,
};
-static const u64 i9xx_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane,
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
+ const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->disable_flip_done = ilk_primary_disable_flip_done;
}
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
+
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"plane %c",
plane_name(plane->i9xx_plane));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f64..1f764c6d59583 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
};
-static const u64 cursor_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- D
[Intel-gfx] [PATCH v2 09/11] drm/i915: Add a platform independent way to check for CCS control planes
Future platforms change the location of CCS control planes in CCS
framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in control planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 73 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c| 3 +-
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bb53b01f07aee..b4b6a31caf4e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index d2491a73d255b..85a2eaaa7cad8 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -126,6 +126,8 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_ctrl_planes:4;
+ u8 planar_ctrl_planes:4;
} ccs;
} intel_modifiers[] = {
{
@@ -153,6 +155,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -161,6 +164,7 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -170,6 +174,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -179,6 +184,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_ctrl_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -189,6 +195,8 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_ctrl_planes = BIT(1),
+ .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -358,17 +366,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
+ const struct drm_format_info *format)
{
- if (!is_ccs_modifier(fb->modifier))
- return false;
+ if (format_is_yuv_semiplanar(md, format))
+ return md->ccs.planar_ctrl_planes;
+ else
+ return md->ccs.packed_ctrl_planes;
+}
+
+/**
+ * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS
control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a CCS control plane.
+ */
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
- return plane >= fb->format->num_planes / 2;
+ return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+/**
+ * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer
[Intel-gfx] [PATCH v2 05/11] drm/i915: Unexport is_semiplanar_uv_plane()
This function is only used by intel_fb.c, so unexport it.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index c15d17d2983d4..2523d5baf59ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -345,7 +345,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer
*fb, int plane)
plane == 2;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index a87c58a3219cd..65b5dd9468ff2 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -33,7 +33,6 @@ enum intel_plane_caps {
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
--
2.27.0
[Intel-gfx] [PATCH v2 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane
On future platforms the index of the color-clear plane will change from
the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve
the index independently of the platform/modifier.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +---
drivers/gpu/drm/i915/display/intel_fb.c | 25 ++--
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8043a9fd665a5..bfb9120cb31ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10031,10 +10031,14 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct drm_framebuffer *fb = plane_state->hw.fb;
+ int cc_plane;
int ret;
- if (!fb ||
- fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (!fb)
+ continue;
+
+ cc_plane = intel_fb_rc_ccs_cc_plane(fb);
+ if (cc_plane < 0)
continue;
/*
@@ -10051,7 +10055,7 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
* GPU write on it.
*/
ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
-fb->offsets[2] + 16,
+fb->offsets[cc_plane] + 16,
&plane_state->ccval,
sizeof(plane_state->ccval));
/* The above could only fail if the FB obj has an unexpected
backing store type. */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index bca9176e3e905..ead1f69a1873c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -125,6 +125,7 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
+ u8 cc_planes:3;
} ccs;
} intel_modifiers[] = {
{
@@ -178,6 +179,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
@@ -369,10 +371,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb,
int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+/**
+ * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
+ * @fb: Framebuffer
+ *
+ * Returns:
+ * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
+ * framebuffer using a render compression/color clear modifier.
+ */
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ if (!md->ccs.cc_planes)
+ return -1;
+
+ drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
+
+ return ilog2((int)md->ccs.cc_planes);
+}
+
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
- return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
- plane == 2;
+ return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 442d8d084f100..7bcfc5517a2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,6 +34,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int
plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
+
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
--
2.27.0
[Intel-gfx] [PATCH v2 03/11] drm/i915: Add tiling attribute to the modifier descriptor
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 920de857ffa28..c15d17d2983d4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -116,6 +116,7 @@ const struct intel_modifier_desc {
const struct drm_format_info *formats;
int format_count;
u8 is_linear:1;
+ u8 tiling;
struct {
#define INTEL_CCS_RC BIT(0)
@@ -134,10 +135,12 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_X_TILED,
.display_versions = DISPLAY_VER_MASK_ALL,
+ .tiling = I915_TILING_X,
},
{
.id = I915_FORMAT_MOD_Y_TILED,
.display_versions = DISPLAY_VER_MASK(9, 13),
+ .tiling = I915_TILING_Y,
},
{
.id = I915_FORMAT_MOD_Yf_TILED,
@@ -146,6 +149,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -162,6 +166,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -170,6 +175,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -178,6 +184,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -529,18 +536,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
[Intel-gfx] [PATCH v2 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c
Move the function to intel_fb.c and rename it adding the intel_fb_
prefix following the naming of exported functions.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 9 --
drivers/gpu/drm/i915/display/intel_fb.c | 29 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 12
4 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b4b6a31caf4e3..f38b70ef6afaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2041,13 +2041,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 85a2eaaa7cad8..cf84b1ce6a485 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -261,6 +261,19 @@ static bool is_ccs_type_modifier(const struct
intel_modifier_desc *md, u8 ccs_ty
return md->ccs.type & ccs_type;
}
+/**
+ * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier.
+ */
+bool intel_fb_is_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
@@ -446,7 +459,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb,
int color_plane)
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
(main_plane && main_plane >= fb->format->num_planes / 2));
return fb->format->num_planes / 2 + main_plane;
@@ -454,7 +467,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int
main_plane)
int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
if (is_gen12_ccs_cc_plane(fb, ccs_plane))
@@ -499,7 +512,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb,
int main_plane)
{
struct drm_i915_private *i915 = to_i915(fb->dev);
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
@@ -1063,7 +1076,7 @@ static bool intel_plane_can_remap(const struct
intel_plane_state *plane_state)
* The new CCS hash mode isn't compatible with remapping as
* the virtual address of the pages affects the compressed data.
*/
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return false;
/* Linear needs a page aligned stride for remapping */
@@ -1470,7 +1483,7 @@ static void intel_plane_remap_gtt(struct
intel_plane_state *plane_state)
src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier));
+ drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
drm_rect_translate(&plane_state->uapi.src,
@@ -1533,7 +1546,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
intel_modifier_uses_dpt(dev_priv, modifier))
r
[Intel-gfx] [PATCH v2 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
Instead of open-coding the checks add functions for this, simplifying
the handling of CCS modifiers on future platforms.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 4 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index cf84b1ce6a485..da8cc5e47aa1b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -274,6 +274,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
}
+/**
+ * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC
modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render with color clear modifier.
+ */
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC);
+}
+
+/**
+ * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a media compression modifier.
+ */
+bool intel_fb_is_mc_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC);
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index b05c3f64b6f0c..c39bf840edb2c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -31,6 +31,8 @@ enum intel_plane_caps {
};
bool intel_fb_is_ccs_modifier(u64 modifier);
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
+bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 82dd3c0cc49ea..e3346da4884d1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1067,7 +1067,7 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
intel_uncore_write64_fw(&dev_priv->uncore,
PLANE_CC_VAL(pipe, plane_id),
plane_state->ccval);
@@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
- if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ if (intel_fb_is_mc_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
--
2.27.0
Re: [Intel-gfx] [PATCH] drm/i915/display: Remove check for low voltage sku for max dp source rate
On Thu, Oct 07, 2021 at 01:19:25PM +0530, Nautiyal, Ankit K wrote: > > On 10/5/2021 9:01 PM, Imre Deak wrote: > > On Tue, Oct 05, 2021 at 01:34:21PM +0300, Jani Nikula wrote: > > > Cc: Imre, I think you were involved in adding the checks. > > About ADL-S the spec says: > > > > Bspec 53597: > > Combo Port Maximum Speed: > > OEM must use VBT to specify a maximum that is tolerated by the board design. > > > > Combo Port HBR3 support: > > May require retimer on motherboard. The OEM must use VBT to limit the link > > rate to HBR2 if HBR3 not supported by motherboard. > > > > Bspec/49201: > > Combo Port HBR3/6.48GHz support: > > Only supported on SKUs with higher I/O voltage > > > > I take the above meaning that only high voltage SKUs support HBR3 and > > on those SKUs the OEM must limit this to HBR2 if HBR3 would require a > > retimer on the board, but the board doesn't have this. > > > > If the above isn't correct and low voltage SKUs also in fact support > > HBR3 (with retimers if necessary) then this should imo clarified at > > Bspec/49201. The VBT limit could be used then if present, ignoring the > > low voltage SKU readout. > > Thanks Imre for the inputs. > > As you have mentioned note : rate >5.4 G supported only on High voltage I/O, > is mentioned for platforms like ICL, JSL and Display 12 platforms. > > I had again asked the HW team and VBT/GOP team whether we can safely rely on > VBT for the max rate for these platforms, without worrying about the SKU's > IO Voltage, and also requested them to update the Bspec page for the same. > > In response the Bspec pages 49201, 20598 are now updated with the note "OEM > must use VBT to specify a maximum that is tolerated by the board design" for > the rates above 5.4G. Ok, thanks for this, now the spec is closer to the proposed changes. On some platforms it's still unclear if the default max rate in the lack of a VBT limit is HBR2 or HBR3. The ADL-S overview at Bspec/53597 is clear now wrt. this: (*) "May require retimer on motherboard. The OEM must use VBT to limit the link rate to HBR2 if HBR3 not supported by motherboard." ideally it should still clarify if the potential retimer requirement applies to both eDP and DP or only to DP. I still see the followings to adjust in the spec so that it reflects the patch: - ICL - bspec/20584: "Increased IO voltage may be required to support HBR3 for the highest DisplayPort and eDP resolutions." should be changed to (*) above mentioning that HBR3 is only supported on eDP. - bspec/20598: "Combo HBR3: OEM must use VBT to specify a miximum that is tolerated by the board design." The DP/HBR3 support on ICL should be removed. For eDP/HBR3 on ICL the above comment should be changed to (*). - JSL - bspec/32247: "Increased IO voltage may be required to support HBR3 for the highest DisplayPort resolutions." should be removed/changed to (*). - bspec/20598: "OEM must use VBT to specify a miximum that is tolerated by the board design." should be changed to (*). - TGL: - bspec/49201: "Combo HBR3: OEM must use VBT to specify a miximum that is tolerated by the board design." The DP/HBR3 support should be removed, for eDP/HBR3 the above should be changed to (*). - RKL: - bspec/49201, 49204: Remove the RKL tag, since there is a separate page for RKL. - bspec/49202: "Combo HBR3: Only supported on SKUs with higher I/O voltage" should be changed to (*). - ADLS: - bspec/49201, 49204: The ADLS tag should be removed, since there is a separate page for ADLS. - bspec/53720: "Combo HBR3: OEM must use VBT to specify a miximum that is tolerated by the board design." should be changed to (*). - DG1: - bspec/49205: "Combo HBR3: Only supported on SKUs with higher I/O voltage" should be changed to (*) above. - DG2: - bspec/53657: For Combo HBR3 (*) should be added. - bspec/54034: For Combo HBR3 (*) should be added. - ADLP: - bspec/49185: "Combo DP/HBR3: OEM must use VBT to specify a miximum that is tolerated by the board design. An external re-timer may be needed." should be changed to (*). Also could you add a debug print with the voltage configuration of combo PHYs somewhere in intel_combo_phy.c? > From what I understand, we can depend upon the VBT's rate, and if there are > some low voltage I/O SKUs that do not support HBR3 rate, it should be > limited by the VBT. > > Thanks & Regards, > > Ankit > > > > BR, > > > Jani. > > > > > > On Tue, 05 Oct 2021, &qu
Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Wed, Oct 13, 2021 at 11:14:42PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
> >
> > v2:
> > - Keep the plane caps calculation in the plane code and pass an enum
> > with these caps to intel_fb_get_modifiers(). (Ville)
> > - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
> > well.
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h| 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 143 ++
> > drivers/gpu/drm/i915/display/intel_fb.h | 16 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c| 181 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 9 files changed, 245 insertions(+), 184 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index b1439ba78f67b..a939accff7ee2 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
> > DRM_FORMAT_XBGR16161616F,
> > };
> >
> > -static const u64 i9xx_format_modifiers[] = {
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_C8:
> > @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct
> > drm_plane *_plane,
> > static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_C8:
> > @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private
> > *dev_priv, enum pipe pipe)
> > struct intel_plane *plane;
> > const struct drm_plane_funcs *plane_funcs;
> > unsigned int supported_rotations;
> > + const u64 *modifiers;
> > const u32 *formats;
> > int num_formats;
> > int ret, zpos;
> > @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private
> > *dev_priv, enum pipe pipe)
> > plane->disable_flip_done = ilk_primary_disable_flip_done;
> > }
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
> > +
> > if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> >0, plane_funcs,
> >formats, num_formats,
> > - i9xx_format_modifiers,
> > + modifiers,
> >DRM_PLANE_TYPE_PRIMARY,
> >"primary %c", pipe_name(pipe));
> > else
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> >0, plane_funcs,
>
Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
On Wed, Oct 13, 2021 at 11:17:04PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 03:19:09AM +0300, Imre Deak wrote:
> > Move the function retrieving the format override information for a given
> > format/modifier to intel_fb.c. We can store a pointer to the format list
> > in each modifier's descriptor instead of the corresponding switch/case
> > logic, avoiding the listing of the modifiers twice.
> >
> > v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
> > userspace.
>
> Do we have any tests for that btw?
Yes, that's how CI caught it: igt/kms_addfb_basic/addfb25-bad-modifier
>
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 132 +--
> > drivers/gpu/drm/i915/display/intel_fb.c | 163 +++
> > drivers/gpu/drm/i915/display/intel_fb.h | 3 +
> > 3 files changed, 167 insertions(+), 131 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4f0badb11bbba..90802d16fbf91 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
> > *y += state->view.color_plane[color_plane].y;
> > }
> >
> > -/*
> > - * From the Sky Lake PRM:
> > - * "The Color Control Surface (CCS) contains the compression status of
> > - * the cache-line pairs. The compression state of the cache-line pair
> > - * is specified by 2 bits in the CCS. Each CCS cache-line represents
> > - * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> > - * cache-line-pairs. CCS is always Y tiled."
> > - *
> > - * Since cache line pairs refers to horizontally adjacent cache lines,
> > - * each cache line in the CCS corresponds to an area of 32x16 cache
> > - * lines on the main surface. Since each pixel is 4 bytes, this gives
> > - * us a ratio of one byte in the CCS for each 8x16 pixels in the
> > - * main surface.
> > - */
> > -static const struct drm_format_info skl_ccs_formats[] = {
> > - { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > - { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > - { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > - { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > -};
> > -
> > -/*
> > - * Gen-12 compression uses 4 bits of CCS data for each cache line pair in
> > the
> > - * main surface. And each 64B CCS cache line represents an area of 4x1
> > Y-tiles
> > - * in the main surface. With 4 byte pixels and each Y-tile having
> > dimensions of
> > - * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32
> > pixels in
> > - * the main surface.
> > - */
> > -static const struct drm_format_info gen12_ccs_formats[] = {
> > - { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > - { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > - { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
>
Re: [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor
On Wed, Oct 13, 2021 at 11:18:27PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 07, 2021 at 11:35:09PM +0300, Imre Deak wrote:
> > Add a tiling atttribute to the modifier descriptor, which let's us
> > get the tiling without listing the modifiers twice.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_fb.c | 20
> > 1 file changed, 8 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 2543232580885..ef3cd375c9942 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -115,6 +115,7 @@ const struct intel_modifier_desc {
> > u64 display_versions;
> > const struct drm_format_info *formats;
> > int format_count;
> > + u8 tiling;
> >
> > struct {
> > #define INTEL_CCS_RC BIT(0)
> > @@ -132,10 +133,12 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_X_TILED,
> > .display_versions = DISPLAY_VER_MASK_ALL,
> > + .tiling = I915_TILING_X,
> > },
> > {
> > .id = I915_FORMAT_MOD_Y_TILED,
> > .display_versions = DISPLAY_VER_MASK(9, 13),
> > + .tiling = I915_TILING_Y,
> > },
> > {
> > .id = I915_FORMAT_MOD_Yf_TILED,
> > @@ -144,6 +147,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > .display_versions = DISPLAY_VER_MASK(9, 11),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> >
> > @@ -160,6 +164,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> >
> > @@ -168,6 +173,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC_CC,
> >
> > @@ -176,6 +182,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_MC,
> >
> > @@ -556,18 +563,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
> >
> > static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> > {
> > - switch (fb_modifier) {
> > - case I915_FORMAT_MOD_X_TILED:
> > - return I915_TILING_X;
> > - case I915_FORMAT_MOD_Y_TILED:
> > - case I915_FORMAT_MOD_Y_TILED_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > - return I915_TILING_Y;
> > - default:
> > - return I915_TILING_NONE;
>
> Had to double check that I915_TILING_NONE is really 0. It is.
Yea, I guess better to explicitly init it.
> > - }
> > + return lookup_modifier(fb_modifier)->tiling;
> > }
> >
> > unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
> > --
> > 2.27.0
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > Future platforms change the location of CCS control planes in CCS
> > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> >
> > Don't we use the term 'ccs_plane' everywhere else?
> >
> > > planes independently of the platform. This function can be used
> > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > since all the callers are only interested in control planes (and not CCS
> > > color-clear planes).
>
> Hmm. I guess you're changing the terminology across the board?
> If it's used consistently then no objections from me.
ccs_plane has been used as a generic term for both the "control" and the
cc plane, or at least I thought of it as such. I'm not sure if control
is a good name, but couldn't think of a better one. In any case I
thought calling the control plane ccs_plane is too generic, and would
make things clearer to use a more explicit term.
Function params and variables still use the ccs_plane name, though all
or most just handle ccs control planes.
main_to_ccs_plane() and skl_ccs_to_main_plane() should be renamed to
intel_fb_main_to_ccs_ctrl_plane() and intel_fb_ccs_ctrl_to_main_plane()
and change the latter one to assert that a control plane was passed.
IGT would also need the corresponding renames.
If you agree with the rational I can follow up with the above renames.
Otherwise we could just continue calling the control plane ccs_plane and
the cc plane ccs_cc_plane.
> > > Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
> > > used everywhere instead of is_gen12_ccs_plane(), based on the above
> > > explanation.
> > >
> > > This change also unexports the is_gen12_ccs_modifier(),
> > > is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
> > > used in intel_fb.c
> > >
> > > Signed-off-by: Imre Deak
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 7 --
> > > drivers/gpu/drm/i915/display/intel_fb.c | 73 ++-
> > > drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
> > > .../drm/i915/display/skl_universal_plane.c| 3 +-
> > > 4 files changed, 56 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index bb53b01f07aee..b4b6a31caf4e3 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > }
> > >
> > > -static inline bool is_gen12_ccs_modifier(u64 modifier)
> > > -{
> > > - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > -modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > > -modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > > -}
> > > -
> > > #endif /* __INTEL_DISPLAY_TYPES_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index e8fe198b1b6a1..392f89e659eb6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -125,6 +125,8 @@ const struct intel_modifier_desc {
> > > #define INTEL_CCS_ANY(INTEL_CCS_RC | INTEL_CCS_RC_CC |
> > > INTEL_CCS_MC)
> > > u8 type:3;
> > > u8 cc_planes:3;
> > > + u8 packed_ctrl_planes:4;
> > > + u8 planar_ctrl_planes:4;
> > > } ccs;
> > > } intel_modifiers[] = {
> > > {
> > > @@ -151,6 +153,7 @@ const struct intel_modifier_desc {
> > > .tiling = I915_TILING_Y,
> > >
> > > .ccs.type = INTEL_CCS_RC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > >
> > > FORMAT_OVERRIDE(skl_ccs_formats),
> > > },
> > > @@ -159,6 +162,7 @@ const struct intel_modifier_desc {
> > > .display_versions = DISPLAY_VER_MASK(9, 11),
> > >
> > > .ccs.type = INTEL_CCS_RC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > >
Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
On Thu, Oct 14, 2021 at 12:54:58AM +0300, Ville Syrjälä wrote: > On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote: > > On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote: > > > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote: > > > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote: > > > > > Future platforms change the location of CCS control planes in CCS > > > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for > > > > > these > > > > > > > > Don't we use the term 'ccs_plane' everywhere else? > > > > > > > > > planes independently of the platform. This function can be used > > > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && > > > > > !cc_plane()), > > > > > since all the callers are only interested in control planes (and not > > > > > CCS > > > > > color-clear planes). > > > > > > Hmm. I guess you're changing the terminology across the board? > > > If it's used consistently then no objections from me. > > > > ccs_plane has been used as a generic term for both the "control" and the > > cc plane, or at least I thought of it as such. > > The official definition I think is: > CCS == color control surface > > So in terms of modifier naming I suppose I tend to think > of it like this: > modifier name has CCS -> color control surface is present > modifier name has CC -> clear color is present > > But if we want to make the distinction somehow stronger I was > thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up > being more confusing since AUX_DIST is also used for planar scanout > on skl/etc. > > Or another way to make it more clear would be to drop the "ccs" part > from the is_ccs_cc_plane() or whatever. But is_cc_plane() is perhaps > also pretty confusing. So could expand it to full on is_clear_color_plane()? Imo it's better to preserve the connection to ccs in the name, maybe regarding the cc as a subplane of the ccs plane. > Shrug. Plenty of different color paint for this one available I think. Ok with all that, I think the best would be to use the ccs_plane / ccs_cc_plane names to mean the control plane and clear color plane. Will change the patch. --Imre
Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Wed, Oct 13, 2021 at 11:40:11PM +0300, Ville Syrjälä wrote: > On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote: > > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); > > bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); > > bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); > > Side note: > We have quite a few of these 'int plane' things still around. I'd > like to see them all renamed to 'color_plane' so that we don't get > confused between diffrent kinds of planes. > > The rules that I've been going for everywhere: > - int color_plane == plane of a planar/compressed framebuffer > - struct intel_plane *plane == representation of the piece of > hardware that does the scanout > - enum plane plane_id == standalone version of plane->id > - enum i9xx_plane_id i9xx_plane == standalone version of plane->i9xx_plane Ok, makes sense, I'll s/plane/color_plane/ in functions I added in this patchset and will follow up to convert the remaining ones. > -- > Ville Syrjälä > Intel
Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
On Thu, Oct 14, 2021 at 01:38:14AM +0300, Ville Syrjälä wrote: > On Thu, Oct 14, 2021 at 01:28:24AM +0300, Imre Deak wrote: > > On Thu, Oct 14, 2021 at 12:54:58AM +0300, Ville Syrjälä wrote: > > > On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote: > > > > On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote: > > > > > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote: > > > > > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote: > > > > > > > Future platforms change the location of CCS control planes in CCS > > > > > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for > > > > > > > these > > > > > > > > > > > > Don't we use the term 'ccs_plane' everywhere else? > > > > > > > > > > > > > planes independently of the platform. This function can be used > > > > > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && > > > > > > > !cc_plane()), > > > > > > > since all the callers are only interested in control planes (and > > > > > > > not CCS > > > > > > > color-clear planes). > > > > > > > > > > Hmm. I guess you're changing the terminology across the board? > > > > > If it's used consistently then no objections from me. > > > > > > > > ccs_plane has been used as a generic term for both the "control" and the > > > > cc plane, or at least I thought of it as such. > > > > > > The official definition I think is: > > > CCS == color control surface > > > > > > So in terms of modifier naming I suppose I tend to think > > > of it like this: > > > modifier name has CCS -> color control surface is present > > > modifier name has CC -> clear color is present > > > > > > But if we want to make the distinction somehow stronger I was > > > thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up > > > being more confusing since AUX_DIST is also used for planar scanout > > > on skl/etc. > > I guess the fact that it would also say "ccs" in additon to "aux" > would make it ok. So ccs_aux goes into AUX_DIST, ccs_cc goes into CC_VAL. Ok, ccs_aux works I guess, and it's actually used at a few places already. So yes, not too consistent atm, will use ccs_aux in this patchset and rename the remaining instances in a follow-up patch. > But anyway, as long we go with something consitent everywhere I'll be > happy. > > -- > Ville Syrjälä > Intel
Re: [Intel-gfx] [PATCH] drm/i915/display: Remove check for low voltage sku for max dp source rate
On Thu, Oct 14, 2021 at 05:02:46PM +0530, Nautiyal, Ankit K wrote: > > On 10/13/2021 8:49 PM, Imre Deak wrote: > > On Thu, Oct 07, 2021 at 01:19:25PM +0530, Nautiyal, Ankit K wrote: > > > On 10/5/2021 9:01 PM, Imre Deak wrote: > > > > On Tue, Oct 05, 2021 at 01:34:21PM +0300, Jani Nikula wrote: > > > > > Cc: Imre, I think you were involved in adding the checks. > > > > About ADL-S the spec says: > > > > > > > > Bspec 53597: > > > > Combo Port Maximum Speed: > > > > OEM must use VBT to specify a maximum that is tolerated by the board > > > > design. > > > > > > > > Combo Port HBR3 support: > > > > May require retimer on motherboard. The OEM must use VBT to limit the > > > > link rate to HBR2 if HBR3 not supported by motherboard. > > > > > > > > Bspec/49201: > > > > Combo Port HBR3/6.48GHz support: > > > > Only supported on SKUs with higher I/O voltage > > > > > > > > I take the above meaning that only high voltage SKUs support HBR3 and > > > > on those SKUs the OEM must limit this to HBR2 if HBR3 would require a > > > > retimer on the board, but the board doesn't have this. > > > > > > > > If the above isn't correct and low voltage SKUs also in fact support > > > > HBR3 (with retimers if necessary) then this should imo clarified at > > > > Bspec/49201. The VBT limit could be used then if present, ignoring the > > > > low voltage SKU readout. > > > Thanks Imre for the inputs. > > > > > > As you have mentioned note : rate >5.4 G supported only on High voltage > > > I/O, > > > is mentioned for platforms like ICL, JSL and Display 12 platforms. > > > > > > I had again asked the HW team and VBT/GOP team whether we can safely rely > > > on > > > VBT for the max rate for these platforms, without worrying about the SKU's > > > IO Voltage, and also requested them to update the Bspec page for the same. > > > > > > In response the Bspec pages 49201, 20598 are now updated with the note > > > "OEM > > > must use VBT to specify a maximum that is tolerated by the board design" > > > for > > > the rates above 5.4G. > > Ok, thanks for this, now the spec is closer to the proposed changes. On > > some platforms it's still unclear if the default max rate in the lack of > > a VBT limit is HBR2 or HBR3. The ADL-S overview at Bspec/53597 is clear > > now wrt. this: > > > > (*) "May require retimer on motherboard. The OEM must use VBT to limit the > > link rate > > to HBR2 if HBR3 not supported by motherboard." > > > > ideally it should still clarify if the potential retimer requirement > > applies to > > both eDP and DP or only to DP. > > Thanks Imre, point noted. > > I realized: in general, the Platform Overview page and Platform Combo phy > clocks pages seem to be not in sync on the combo phy rate in some places. > > Earlier I was looking only on the clock pages for the combo phy rate > information. Yes, it's a bit scattered. Please also cross check the third place at least for each affected platforms (ICL+) which is the Combo vswing programming (Digital Display Interface/Combo PHY DDI Buffer etc.). > I will again clarify this with the H/W team and request for the below > suggested modifications for the given platforms. Thanks. > > I still see the followings to adjust in the spec so that it reflects > > the patch: > > - ICL > >- bspec/20584: > > "Increased IO voltage may be required to support HBR3 for the highest > > DisplayPort > > and eDP resolutions." > > > > should be changed to (*) above mentioning that HBR3 is only supported > > on > > eDP. > > > >- bspec/20598: > > "Combo HBR3: OEM must use VBT to specify a miximum that is tolerated > > by the > > board design." > > > > The DP/HBR3 support on ICL should be removed. > > > > For eDP/HBR3 on ICL the above comment should be changed to (*). > > > > - JSL > >- bspec/32247: > > "Increased IO voltage may be required to support HBR3 for the highest > > DisplayPort > > resolutions." > > > > should be removed/changed to (*). > > > >- bspec/20598: > > "OEM must use VBT to specify a miximum that is tolerated by the >
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Thu, Oct 14, 2021 at 05:07:16PM +0300, Jani Nikula wrote:
> On Thu, 07 Oct 2021, Imre Deak wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
>
> Just some high level comments inline.
>
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h| 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++
> > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c| 137 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 8 files changed, 218 insertions(+), 164 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB,
> > };
> >
> > -static const u64 cursor_format_modifiers[] = {
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct
> > intel_plane *plane,
> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > - format == DRM_FORMAT_ARGB;
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > + return false;
> > +
> > + return format == DRM_FORMAT_ARGB;
> > }
> >
> > static int
> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private
> > *dev_priv,
> > {
> > struct intel_plane *cursor;
> > int ret, zpos;
> > + u64 *modifiers;
> >
> > cursor = intel_plane_alloc();
> > if (IS_ERR(cursor))
> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private
> > *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > cursor->cursor.size = ~0;
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> >0, &intel_cursor_plane_funcs,
> >intel_cursor_formats,
> >ARRAY_SIZE(intel_cursor_formats),
> > - cursor_format_modifiers,
> > + modifiers,
> >DRM_PLANE_TYPE_CURSOR,
> >"cursor %c", pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645a..bb53b01f07aee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > enum plane_id id;
> > enum pipe pipe;
> > bool has_fbc;
> > - bool has_ccs;
> > bool need_async_flip_disable_wa;
> > u32 frontbuffer_bit;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index fa1f375e696bf..aefae988b620b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,6 +13,184 @@
> >
> > #define check_array_bounds(i915, a, i
[Intel-gfx] [PATCH v3 00/11] drm/i915: Simplify handling of modifiers
This is v3 of [1] addressing review comments and adding r-b lines. [1] https://patchwork.freedesktop.org/series/95579/ Cc: Juha-Pekka Heikkila Cc: Ville Syrjälä Cc: Jani Nikula Imre Deak (11): drm/i915: Add a table with a descriptor for all i915 modifiers drm/i915: Move intel_get_format_info() to intel_fb.c drm/i915: Add tiling attribute to the modifier descriptor drm/i915: Simplify the modifier check for interlaced scanout support drm/i915: Unexport is_semiplanar_uv_plane() drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c drm/i915: Add a platform independent way to get the RC CCS CC plane drm/i915: Handle CCS CC planes separately from CCS AUX planes drm/i915: Add a platform independent way to check for CCS AUX planes drm/i915: Move is_ccs_modifier() to intel_fb.c drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 150 + drivers/gpu/drm/i915/display/intel_display.h | 3 - .../drm/i915/display/intel_display_types.h| 17 - drivers/gpu/drm/i915/display/intel_fb.c | 535 -- drivers/gpu/drm/i915/display/intel_fb.h | 30 +- drivers/gpu/drm/i915/display/intel_sprite.c | 35 +- drivers/gpu/drm/i915/display/skl_scaler.c | 1 + .../drm/i915/display/skl_universal_plane.c| 206 ++- drivers/gpu/drm/i915/intel_pm.c | 1 + 12 files changed, 621 insertions(+), 407 deletions(-) -- 2.27.0
[Intel-gfx] [PATCH v3 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(),
as the cursor plane is registered with DRM core elsewhere.
v1: Unchanged.
v2:
- Keep the plane caps calculation in the plane code and pass an enum
with these caps to intel_fb_get_modifiers(). (Ville)
- Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
well.
v3:
- s/.id/.modifier/ (Ville)
- Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville)
- Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville)
- Use from, until display version fields in modifier_desc instead of a mask.
(Jani)
- Unexport struct intel_modifier_desc, separate its decl and init. (Jani)
- Remove enum pipe, plane_id forward decls from intel_fb.h, which are
not needed after v2.
Cc: Ville Syrjälä
Cc: Juha-Pekka Heikkila
Cc: Jani Nikula
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila (v2)
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 159
drivers/gpu/drm/i915/display/intel_fb.h | 13 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 178 +-
8 files changed, 252 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67b..a939accff7ee2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
DRM_FORMAT_XBGR16161616F,
};
-static const u64 i9xx_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane,
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
+ const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->disable_flip_done = ilk_primary_disable_flip_done;
}
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
+
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
[Intel-gfx] [PATCH v3 03/11] drm/i915: Add tiling attribute to the modifier descriptor
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
v1-v2: Unchanged.
v3:
- Initialize .tiling to I915_TILING_NONE explicitly (Ville)
- Move from previous patch lookup_modifier() to here, where it's first
used.
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 33 -
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 772a68a9f65b0..06697379a9917 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -120,6 +120,7 @@ struct intel_modifier_desc {
.formats = format_list, \
.format_count = ARRAY_SIZE(format_list)
+ u8 tiling;
u8 is_linear:1;
struct {
@@ -136,24 +137,29 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
{
.modifier = DRM_FORMAT_MOD_LINEAR,
.display_ver = DISPLAY_VER_ALL,
+ .tiling = I915_TILING_NONE,
.is_linear = true,
},
{
.modifier = I915_FORMAT_MOD_X_TILED,
.display_ver = DISPLAY_VER_ALL,
+ .tiling = I915_TILING_X,
},
{
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
+ .tiling = I915_TILING_Y,
},
{
.modifier = I915_FORMAT_MOD_Yf_TILED,
.display_ver = { 9, 11 },
+ .tiling = I915_TILING_NONE,
},
{
.modifier = I915_FORMAT_MOD_Y_TILED_CCS,
.display_ver = { 9, 11 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -162,6 +168,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
.display_ver = { 9, 11 },
+ .tiling = I915_TILING_NONE,
.ccs.type = INTEL_CCS_RC,
@@ -170,6 +177,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -178,6 +186,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -186,6 +195,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -204,6 +214,16 @@ static const struct intel_modifier_desc
*lookup_modifier_or_null(u64 modifier)
return NULL;
}
+static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
+{
+ const struct intel_modifier_desc *md =
lookup_modifier_or_null(modifier);
+
+ if (WARN_ON(!md))
+ return &intel_modifiers[0];
+
+ return md;
+}
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -535,18 +555,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
[Intel-gfx] [PATCH v3 04/11] drm/i915: Simplify the modifier check for interlaced scanout support
Checking the modifiers that support interlacing makes the condition
simpler and avoids us having to add new modifiers to the list (presuming
all/most of the new modifiers won't support interlacing).
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 264b9a422a224..e1f754270eb02 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1240,13 +1240,8 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
/* Y-tiling is not supported in IF-ID Interlace mode */
if (crtc_state->hw.enable &&
crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
- (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
-fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
+ fb->modifier != DRM_FORMAT_MOD_LINEAR &&
+ fb->modifier != I915_FORMAT_MOD_X_TILED) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
--
2.27.0
[Intel-gfx] [PATCH v3 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
v1: Unchanged.
v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
userspace. (CI/igt_kms_addfb_basic/addfb25-bad-modifier)
v3: Move lookup_modifier() to the next patch, where it's first used.
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +---
drivers/gpu/drm/i915/display/intel_fb.c | 153 +++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 157 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ff598b6cd9530..0f42beef2551e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -897,136 +897,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub
[Intel-gfx] [PATCH v3 05/11] drm/i915: Unexport is_semiplanar_uv_plane()
This function is only used by intel_fb.c, so unexport it.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 06697379a9917..6f618ca01ba01 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -364,7 +364,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer
*fb, int plane)
plane == 2;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 97b31c3a29825..c331df575490d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -30,7 +30,6 @@ enum intel_plane_caps {
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
--
2.27.0
[Intel-gfx] [PATCH v3 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
Move intel_format_info_is_yuv_semiplanar() to intel_fb.c . The number of
planes for YUV semiplanar formats using CCS modifiers will change on
future platforms. We can use the modifier descriptors to simplify
getting the plane numbers for all modifiers, prepare for that here.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 8 -
drivers/gpu/drm/i915/display/intel_display.h | 3 --
drivers/gpu/drm/i915/display/intel_fb.c | 30 +++
drivers/gpu/drm/i915/display/intel_fb.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 1 +
6 files changed, 36 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0be8c00e3db9a..f61a48e1a562b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_fb_pin.h"
#include "intel_pm.h"
#include "intel_sprite.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0f42beef2551e..ef8a9f235ee0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -823,14 +823,6 @@ void intel_disable_transcoder(const struct
intel_crtc_state *old_crtc_state)
intel_wait_for_pipe_off(old_crtc_state);
}
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier)
-{
- return info->is_yuv &&
- info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
-}
-
unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info)
{
unsigned int size = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 0c76bf57f86b5..4267465b5ff97 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -610,9 +610,6 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state);
bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier);
struct intel_encoder *
intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 6f618ca01ba01..60ec38cc1e0fb 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -345,6 +345,36 @@ bool intel_fb_plane_supports_modifier(struct intel_plane
*plane, u64 modifier)
return false;
}
+static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
+const struct drm_format_info *info)
+{
+ int yuv_planes;
+
+ if (!info->is_yuv)
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_ANY))
+ yuv_planes = 4;
+ else
+ yuv_planes = 2;
+
+ return info->num_planes == yuv_planes;
+}
+
+/**
+ * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV
semiplanar
+ * @info: format to check
+ * @modifier: modifier used with the format
+ *
+ * Returns:
+ * %true if @info / @modifier is YUV semiplanar.
+ */
+bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+u64 modifier)
+{
+ return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
+}
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index c331df575490d..a2cdf48f13395 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -38,6 +38,10 @@ bool intel_fb_plane_supports_modifier(struct intel_plane
*plane, u64 modifier);
const struct drm_format_info *
intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+bool
+intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+ u64 modifier);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ecbb3d1416321..6ae48acbe2992 1006
[Intel-gfx] [PATCH v3 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes
Future platforms change the location of CCS AUX planes in CCS
framebuffers, so add intel_fb_is_ccs_aux_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in CCS AUX planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_aux_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
v1-v2: Unchanged
v3: (Ville)
- Use ccs_aux instead of the ccs_ctrl term everywhere.
- Use color_plane instead of plane term for FB plane indicies.
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
.../drm/i915/display/intel_display_types.h| 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 82 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c| 3 +-
4 files changed, 64 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 50b4264f61d62..e3353c2311e52 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2049,11 +2049,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 6e8d600dff6be..60724eed2d864 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -131,6 +131,8 @@ struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_aux_planes:4;
+ u8 planar_aux_planes:4;
} ccs;
};
@@ -163,6 +165,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -172,6 +175,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_NONE,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -181,6 +185,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -190,6 +195,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_aux_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -200,6 +206,8 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_aux_planes = BIT(1),
+ .ccs.planar_aux_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -271,6 +279,13 @@ static bool check_modifier_display_ver(const struct
intel_modifier_desc *md,
display_ver <= md->display_ver.until;
}
+static bool check_modifier_display_ver_range(const struct intel_modifier_desc
*md,
+u8 display_ver_from, u8
display_ver_until)
+{
+ return check_modifier_display_ver(md, display_ver_from) &&
+ check_modifier_display_ver(md, display_ver_until);
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
@@ -377,17 +392,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
+const struct d
[Intel-gfx] [PATCH v3 08/11] drm/i915: Handle CCS CC planes separately from CCS AUX planes
CCS CC planes are quite different from CCS AUX planes, even though we
regard the CC planes as a linear buffer having a 64 byte stride. Thus
it's clearer to check for either CCS plane types explicitly when we need
to handle them; add the required CCS CC planes check here, while the
next patch will change all is_ccs_plane()/is_gen12_ccs_plane() checks to
consider only the CCS AUX planes.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 5273fa5b81622..6e8d600dff6be 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -424,7 +424,8 @@ static bool is_semiplanar_uv_plane(const struct
drm_framebuffer *fb, int color_p
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
- is_gen12_ccs_plane(fb, color_plane);
+ is_gen12_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane);
}
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -517,7 +518,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (is_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane))
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
--
2.27.0
[Intel-gfx] [PATCH v3 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane
On future platforms the index of the color-clear plane will change from
the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve
the index independently of the platform/modifier.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +---
drivers/gpu/drm/i915/display/intel_fb.c | 25 ++--
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ef8a9f235ee0a..dc7778beb938f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9607,10 +9607,14 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct drm_framebuffer *fb = plane_state->hw.fb;
+ int cc_plane;
int ret;
- if (!fb ||
- fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (!fb)
+ continue;
+
+ cc_plane = intel_fb_rc_ccs_cc_plane(fb);
+ if (cc_plane < 0)
continue;
/*
@@ -9627,7 +9631,7 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
* GPU write on it.
*/
ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
-fb->offsets[2] + 16,
+fb->offsets[cc_plane] + 16,
&plane_state->ccval,
sizeof(plane_state->ccval));
/* The above could only fail if the FB obj has an unexpected
backing store type. */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 60ec38cc1e0fb..5273fa5b81622 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -130,6 +130,7 @@ struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
+ u8 cc_planes:3;
} ccs;
};
@@ -189,6 +190,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
@@ -388,10 +390,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb,
int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+/**
+ * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
+ * @fb: Framebuffer
+ *
+ * Returns:
+ * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
+ * framebuffer using a render compression/color clear modifier.
+ */
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ if (!md->ccs.cc_planes)
+ return -1;
+
+ drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
+
+ return ilog2((int)md->ccs.cc_planes);
+}
+
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
- return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
- plane == 2;
+ return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index a2cdf48f13395..74e0fc03319b9 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -31,6 +31,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int
plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
+
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
--
2.27.0
[Intel-gfx] [PATCH v3 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c
Move the function to intel_fb.c and rename it adding the intel_fb_
prefix following the naming of exported functions.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
.../drm/i915/display/intel_display_types.h| 9 --
drivers/gpu/drm/i915/display/intel_fb.c | 29 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 12
4 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e3353c2311e52..d5382f7006f48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2040,13 +2040,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 60724eed2d864..e847568ebe5be 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -272,6 +272,19 @@ static bool is_ccs_type_modifier(const struct
intel_modifier_desc *md, u8 ccs_ty
return md->ccs.type & ccs_type;
}
+/**
+ * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier.
+ */
+bool intel_fb_is_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
+}
+
static bool check_modifier_display_ver(const struct intel_modifier_desc *md,
u8 display_ver)
{
@@ -472,7 +485,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb,
int color_plane)
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
(main_plane && main_plane >= fb->format->num_planes / 2));
return fb->format->num_planes / 2 + main_plane;
@@ -480,7 +493,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int
main_plane)
int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
if (is_gen12_ccs_cc_plane(fb, ccs_plane))
@@ -525,7 +538,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb,
int main_plane)
{
struct drm_i915_private *i915 = to_i915(fb->dev);
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
@@ -1089,7 +1102,7 @@ static bool intel_plane_can_remap(const struct
intel_plane_state *plane_state)
* The new CCS hash mode isn't compatible with remapping as
* the virtual address of the pages affects the compressed data.
*/
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return false;
/* Linear needs a page aligned stride for remapping */
@@ -1496,7 +1509,7 @@ static void intel_plane_remap_gtt(struct
intel_plane_state *plane_state)
src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier));
+ drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
drm_rect_translate(&plane_state->uapi.src,
@@ -1559,7 +1572,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
intel_modifier_uses_dpt(dev_priv, modifier))
r
[Intel-gfx] [PATCH v3 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
Instead of open-coding the checks add functions for this, simplifying
the handling of CCS modifiers on future platforms.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 4 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index e847568ebe5be..05a07943a1257 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -285,6 +285,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
}
+/**
+ * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC
modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render with color clear modifier.
+ */
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC);
+}
+
+/**
+ * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a media compression modifier.
+ */
+bool intel_fb_is_mc_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC);
+}
+
static bool check_modifier_display_ver(const struct intel_modifier_desc *md,
u8 display_ver)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index f32306fbd3dee..042ad81f86082 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -28,6 +28,8 @@ enum intel_plane_caps {
};
bool intel_fb_is_ccs_modifier(u64 modifier);
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
+bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int
color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index bf5c6ee4df147..916378f8ff55e 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1067,7 +1067,7 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
intel_uncore_write64_fw(&dev_priv->uncore,
PLANE_CC_VAL(pipe, plane_id),
plane_state->ccval);
@@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
- if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ if (intel_fb_is_mc_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
--
2.27.0
[Intel-gfx] [PATCH] drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
Reading out the DP encoders' DPCD during booting or resume is only
required for enabled encoders: such encoders may be modesetted during
the initial commit and the link training this involves depends on an
initialized DPCD. For DDI encoders reading out the DPCD is skipped, do
the same on pre-DDI platforms.
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d8132dd4cc5a..23de500d56b52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2007,6 +2007,9 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ if (!crtc_state)
+ return;
+
/*
* Don't clobber DPCD if it's been already read out during output
* setup (eDP) or detect.
--
2.27.0
Re: [Intel-gfx] [PATCH] drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
On Sat, Oct 16, 2021 at 12:59:46AM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, "Souza, Jose" wrote:
> > On Fri, 2021-10-15 at 15:10 +0300, Imre Deak wrote:
> >> Reading out the DP encoders' DPCD during booting or resume is only
> >> required for enabled encoders: such encoders may be modesetted during
> >> the initial commit and the link training this involves depends on an
> >> initialized DPCD. For DDI encoders reading out the DPCD is skipped, do
> >> the same on pre-DDI platforms.
> >
> > Missing fixes tag
> >
> >>
> >> Cc: José Roberto de Souza
> >> Signed-off-by: Imre Deak
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 9d8132dd4cc5a..23de500d56b52 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -2007,6 +2007,9 @@ void intel_dp_sync_state(struct intel_encoder
> >> *encoder,
> >> {
> >>struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>
> >> + if (!crtc_state)
> >> + return;
> >
> > crtc_state is not used
>
> This is why it's so subtle. The commit a532cde31de3 ("drm/i915/tc: Fix
> TypeC port init/resume time sanitization") changes when the sync_state
> hook is called, and now it's also called for disabled encoders, and
> crtc_state != NULL is the way to check that now. Which absolutely must
> be documented in this fix! (And I'm not sure if even that is enough in
> the long term, it seems to me the change is just too subtle and we'll
> get it wrong again.)
The intention was to call the hook on TypeC platforms, where the
encoder/PHY state has to be synced even if the encoder is disabled. I
missed both the dsi and - as now turns out - the g4x dp hooks which I
intended in a532cde31de3 to keep behaving as before.
> I'm guessing the intel_dp_max_common_rate() call gets inlined in
> intel_dp_sync_state(), and it goes wrong with intel_dp->num_common_rates
> being 0 and the array index being -1.
Yes, I came to the same conclusion, see
https://gitlab.freedesktop.org/drm/intel/-/issues/4297
Luckily this doesn't cause an actual problem for regular users, since
the out-of-bound
intel_dp->common_rates[intel_dp->num_common_rates - 1];
access in intel_dp_max_common_rate() in case num_common_rates is 0 will
just return the value of intel_dp->num_common_rates (0). If
KCONFIG_UBSAN is enabled this access will trigger a kernel crash assert
(again luckily for us, even though there could be an explanation message
for the assert).
I'll resend this patch with the root cause for 4297 explained, and
stable CC'd. Also I'll send related patches that will ensure that the
link config parameters derived from DPCD have a valid default value
even in the lack of a valid DPCD.
Imo we should also enable KCONFIG_UBSAN in CI.
> Anyway, having said that, we'll need to stop guessing and dig into the
> root cause.
>
> BR,
> Jani.
>
> >
> >> +
> >>/*
> >> * Don't clobber DPCD if it's been already read out during output
> >> * setup (eDP) or detect.
> >
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 0/6] drm/i915/dp: Fix link parameter use in lack of a valid DPCD
This patchset fixes a few issues, related to invalid accesses from the intel_dp->common_rates[] array and in general the link rate, lane count parameters being invalid until a valid DPCD is read from the sink. One issue in intel_dp_sync_state() was caught by the CONFIG_UBSAN feature. The first 3 patches are also needed for stable kernels. Cc: José Roberto de Souza Cc: Jani Nikula Cc: Ville Syrjälä Imre Deak (6): drm/i915/dp: Skip the HW readout of DPCD on disabled encoders drm/i915/dp: Ensure sink rate values are always valid drm/i915/dp: Ensure max link params are always valid drm/i915/dp: Ensure sink/link max lane count values are always valid drm/i915/dp: Sanitize sink rate DPCD register values drm/i915/dp: Sanitize link common rate array lookups .../drm/i915/display/intel_display_types.h| 2 + drivers/gpu/drm/i915/display/intel_dp.c | 127 ++ 2 files changed, 101 insertions(+), 28 deletions(-) -- 2.27.0
[Intel-gfx] [PATCH 1/6] drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
Reading out the DP encoders' DPCD during booting or resume is only
required for enabled encoders: such encoders may be modesetted during
the initial commit and the link training this involves depends on an
initialized DPCD. For DDI encoders reading out the DPCD is skipped, do
the same on pre-DDI platforms.
Atm, the first DPCD readout without a sink connected - which is a likely
scneario if the encoder is disabled - leaves intel_dp->num_common_rates
at 0, which resulted in
intel_dp_sync_state()->intel_dp_max_common_rate()
in a
intel_dp->common_rates[-1]
access. This by definition results in an undefined behaviour, though to
my best knowledge in all HW/compiler configurations it actually results
in accessing the array item type value preceding the array. In this
case the preceding value happens to be intel_dp->num_common_rates,
which is 0, so this issue - by luck - didn't cause a user visible
problem.
Nevertheless it's still an undefined behaviour and in CONFIG_UBSAN
builds leads to a kernel BUG() (which revealed this problem for us),
hence CC:stable.
A related problem in case the encoder is enabled but the sink is not
connected or the DPCD readout fails is fixed by the next patch.
v2: Amend the commit message describing the root cause of the
CONFIG_UBSAN BUG().
Fixes: a532cde31de3 ("drm/i915/tc: Fix TypeC port init/resume time
sanitization")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
Reported-and-tested-by: Mat Jonczyk
Cc: Mat Jonczyk
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc:
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d8132dd4cc5a..23de500d56b52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2007,6 +2007,9 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ if (!crtc_state)
+ return;
+
/*
* Don't clobber DPCD if it's been already read out during output
* setup (eDP) or detect.
--
2.27.0
[Intel-gfx] [PATCH 3/6] drm/i915/dp: Ensure max link params are always valid
Atm until the DPCD for a connector is read the max link rate and lane
count params are invalid. If the connector is modeset, in
intel_dp_compute_config(), intel_dp_common_len_rate_limit(max_link_rate)
will return 0, leading to a intel_dp->common_rates[-1] access.
Fix the above by making sure the max link params are always valid.
The above access leads to an undefined behaviour by definition, though
not causing a user visible problem to my best knowledge, see the previous
patch why. Nevertheless it is an undefined behaviour and it triggers a
BUG() in CONFIG_UBSAN builds, hence CC:stable.
Cc: Ville Syrjälä
Cc:
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 153ae944a354b..1935eb49f9574 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1864,6 +1864,12 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->lane_count = lane_count;
}
+static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
+{
+ intel_dp->max_link_lane_count =
intel_dp_max_common_lane_count(intel_dp);
+ intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+}
+
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -2023,8 +2029,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
intel_dp_get_dpcd(intel_dp);
- intel_dp->max_link_lane_count =
intel_dp_max_common_lane_count(intel_dp);
- intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp_reset_max_link_params(intel_dp);
}
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
@@ -2597,6 +2602,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_common_rates(intel_dp);
+ intel_dp_reset_max_link_params(intel_dp);
/* Read the eDP DSC DPCD registers */
if (DISPLAY_VER(dev_priv) >= 10)
@@ -4338,12 +4344,7 @@ intel_dp_detect(struct drm_connector *connector,
* supports link training fallback params.
*/
if (intel_dp->reset_link_params || intel_dp->is_mst) {
- /* Initial max link lane count */
- intel_dp->max_link_lane_count =
intel_dp_max_common_lane_count(intel_dp);
-
- /* Initial max link rate */
- intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
-
+ intel_dp_reset_max_link_params(intel_dp);
intel_dp->reset_link_params = false;
}
@@ -5011,6 +5012,7 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
intel_dp_set_source_rates(intel_dp);
intel_dp_set_default_sink_rates(intel_dp);
intel_dp_set_common_rates(intel_dp);
+ intel_dp_reset_max_link_params(intel_dp);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
--
2.27.0
[Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
DPCD capabilities are successfully read from the sink. During this time
intel_dp->num_common_rates is 0 which can lead to a
intel_dp->common_rates[-1](*)
access, which is an undefined behaviour, in the following cases:
- In intel_dp_sync_state(), if the encoder is enabled without a sink
connected to the encoder's connector (BIOS enabled a monitor, but the
user unplugged the monitor until the driver loaded).
- In intel_dp_sync_state() if the encoder is enabled with a sink
connected, but for some reason the DPCD read has failed.
- In intel_dp_compute_link_config() if modesetting a connector without
a sink connected on it.
- In intel_dp_compute_link_config() if modesetting a connector with a
a sink connected on it, but before probing the connector first.
To avoid the (*) access in all the above cases, make sure that the sink
rate table - and hence the common rate table - is always valid, by
setting a default minimum sink rate when registering the connector
before anything could use it.
I also considered setting all the DP link rates by default, so that
modesetting with higher resolution modes also succeeds in the last two
cases above. However in case a sink is not connected that would stop
working after the first modeset, due to the LT fallback logic. So this
would need more work, beyond the scope of this fix.
As I mentioned in the previous patch, I don't think the issue this patch
fixes is user visible, however it is an undefined behaviour by
definition and triggers a BUG() in CONFIG_UBSAN builds, hence CC:stable.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc:
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 23de500d56b52..153ae944a354b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state
*crtc_state)
return crtc_state->port_clock >= 100;
}
+static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
+{
+ intel_dp->sink_rates[0] = 162000;
+ intel_dp->num_sink_rates = 1;
+}
+
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
@@ -5003,6 +5009,8 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
}
intel_dp_set_source_rates(intel_dp);
+ intel_dp_set_default_sink_rates(intel_dp);
+ intel_dp_set_common_rates(intel_dp);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
--
2.27.0
[Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid
Print an error if the DPCD sink max lane count is invalid and fix it up.
While at it also add an assert that the link max lane count (derived
from intel_dp_max_common_lane_count(), potentially reduced by the LT
fallback logic) value is also valid.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 44 ++-
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3f..1e42bf901263c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1563,6 +1563,8 @@ struct intel_dp {
int num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
bool use_rate_select;
+ /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
+ int max_sink_lane_count;
/* intersection of source and sink rates */
int num_common_rates;
int common_rates[DP_MAX_SUPPORTED_RATES];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1935eb49f9574..f7711779df132 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -197,6 +197,35 @@ static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp)
intel_dp->num_sink_rates = i;
}
+static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
+{
+ intel_dp->max_sink_lane_count = 1;
+}
+
+static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
+{
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+
+ intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+
+ switch (intel_dp->max_sink_lane_count) {
+ case 1:
+ case 2:
+ case 4:
+ return;
+ }
+
+ drm_err(&dp_to_i915(intel_dp)->drm,
+ "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count
(%d), using default\n",
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name,
+ intel_dp->max_sink_lane_count);
+
+ intel_dp_set_default_max_sink_lane_count(intel_dp);
+}
+
/* Get length of rates array potentially limited by max_rate. */
static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
{
@@ -230,7 +259,7 @@ static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
int source_max = dig_port->max_lanes;
- int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+ int sink_max = intel_dp->max_sink_lane_count;
int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
int lttpr_max =
drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
@@ -242,7 +271,15 @@ static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
- return intel_dp->max_link_lane_count;
+ switch (intel_dp->max_link_lane_count) {
+ case 1:
+ case 2:
+ case 4:
+ return intel_dp->max_link_lane_count;
+ default:
+ MISSING_CASE(intel_dp->max_link_lane_count);
+ return 1;
+ }
}
/*
@@ -2600,6 +2637,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp->use_rate_select = true;
else
intel_dp_set_sink_rates(intel_dp);
+ intel_dp_set_max_sink_lane_count(intel_dp);
intel_dp_set_common_rates(intel_dp);
intel_dp_reset_max_link_params(intel_dp);
@@ -2645,6 +2683,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
drm_dp_is_branch(intel_dp->dpcd));
intel_dp_set_sink_rates(intel_dp);
+ intel_dp_set_max_sink_lane_count(intel_dp);
intel_dp_set_common_rates(intel_dp);
}
@@ -5011,6 +5050,7 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
intel_dp_set_source_rates(intel_dp);
intel_dp_set_default_sink_rates(intel_dp);
+ intel_dp_set_default_max_sink_lane_count(intel_dp);
intel_dp_set_common_rates(intel_dp);
intel_dp_reset_max_link_params(intel_dp);
--
2.27.0
[Intel-gfx] [PATCH 5/6] drm/i915/dp: Sanitize sink rate DPCD register values
If the DPCD sink rate values read from the sink are invalid, the
driver will sanitize this in intel_dp_set_common_rates(), by setting a
default 162000 link rate in common rates and printing a WARN().
WARN()s should only be triggered by bugs in the code and not by external
factors like the above (an invalid DPCD injected maliciously or read from a
buggy monitor). So fixup the invalid DPCD sink rate values already and print
an error in this case (since it's still a user visible problem).
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f7711779df132..f8082eb8e7263 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -127,7 +127,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp
*intel_dp)
}
/* update sink rates from dpcd */
-static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
+static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
{
static const int dp_rates[] = {
162000, 27, 54, 81
@@ -197,6 +197,25 @@ static void intel_dp_set_sink_rates(struct intel_dp
*intel_dp)
intel_dp->num_sink_rates = i;
}
+static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
+{
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+
+ intel_dp_set_dpcd_sink_rates(intel_dp);
+
+ if (intel_dp->num_sink_rates)
+ return;
+
+ drm_err(&dp_to_i915(intel_dp)->drm,
+ "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link
rates, using defaults\n",
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name);
+
+ intel_dp_set_default_sink_rates(intel_dp);
+}
+
static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
{
intel_dp->max_sink_lane_count = 1;
--
2.27.0
[Intel-gfx] [PATCH 6/6] drm/i915/dp: Sanitize link common rate array lookups
Add an assert that lookups from the intel_dp->common_rates[] array
are always valid.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 -
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f8082eb8e7263..3869d454c10f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -267,10 +267,19 @@ static int intel_dp_common_len_rate_limit(const struct
intel_dp *intel_dp,
intel_dp->num_common_rates, max_rate);
}
+static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
+{
+ if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
+ index < 0 || index >= intel_dp->num_common_rates))
+ return 162000;
+
+ return intel_dp->common_rates[index];
+}
+
/* Theoretical max between source and sink */
static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
{
- return intel_dp->common_rates[intel_dp->num_common_rates - 1];
+ return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
}
/* Theoretical max between source and sink */
@@ -610,13 +619,13 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
if (index > 0) {
if (intel_dp_is_edp(intel_dp) &&
!intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp->common_rates[index - 1],
+
intel_dp_common_rate(intel_dp, index - 1),
lane_count)) {
drm_dbg_kms(&i915->drm,
"Retrying Link training for eDP with same
parameters\n");
return 0;
}
- intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
+ intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
- 1);
intel_dp->max_link_lane_count = lane_count;
} else if (lane_count > 1) {
if (intel_dp_is_edp(intel_dp) &&
@@ -1056,14 +1065,11 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int len;
len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
- if (drm_WARN_ON(&i915->drm, len <= 0))
- return 162000;
- return intel_dp->common_rates[len - 1];
+ return intel_dp_common_rate(intel_dp, len - 1);
}
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
@@ -1260,7 +1266,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
output_bpp);
for (i = 0; i < intel_dp->num_common_rates; i++) {
- link_rate = intel_dp->common_rates[i];
+ link_rate = intel_dp_common_rate(intel_dp, i);
if (link_rate < limits->min_rate ||
link_rate > limits->max_rate)
continue;
@@ -1508,17 +1514,10 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
&pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct link_config_limits limits;
- int common_len;
int ret;
- common_len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_link_rate);
-
- /* No common link rates between source and sink */
- drm_WARN_ON(encoder->base.dev, common_len <= 0);
-
- limits.min_rate = intel_dp->common_rates[0];
- limits.max_rate = intel_dp->common_rates[common_len - 1];
+ limits.min_rate = intel_dp_common_rate(intel_dp, 0);
+ limits.max_rate = intel_dp_max_link_rate(intel_dp);
limits.min_lane_count = 1;
limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
--
2.27.0
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Simplify handling of modifiers (rev10)
Hi Petri, Tomi,
could you check the failure below?
On Fri, Oct 15, 2021 at 11:19:13AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Simplify handling of modifiers (rev10)
> URL : https://patchwork.freedesktop.org/series/95579/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10741_full -> Patchwork_21343_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_21343_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21343_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_21343_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_vblank@pipe-a-wait-busy:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-skl1/igt@kms_vbl...@pipe-a-wait-busy.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-skl1/igt@kms_vbl...@pipe-a-wait-busy.html
This is from Patchwork_21343/shard-skl1/19/dmesg.log , where the above
test passes and is followed by more passing tests, until
kms_busy/extended-modeset-hang-oldfb
also passes at least according to igt_runner.log, though I can't see it in
dmesg.log. After that:
[1091.672412] Overall timeout time exceeded, stopping.
Is it just an overall timeout problem, or some test after
kms_busy/extended-modeset-hand-oldfb?
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@kms_bw@linear-tiling-3-displays-3840x2160p}:
> - shard-snb: NOTRUN -> [FAIL][3]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-snb6/igt@kms...@linear-tiling-3-displays-3840x2160p.html
>
> * {igt@kms_bw@linear-tiling-4-displays-1920x1080p}:
> - shard-apl: NOTRUN -> [DMESG-FAIL][4]
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-apl3/igt@kms...@linear-tiling-4-displays-1920x1080p.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_21343_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@feature_discovery@chamelium:
> - shard-tglb: NOTRUN -> [SKIP][5] ([fdo#111827])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-tglb3/igt@feature_discov...@chamelium.html
>
> * igt@gem_ctx_persistence@hostile:
> - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410])
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-tglb2/igt@gem_ctx_persiste...@hostile.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-tglb5/igt@gem_ctx_persiste...@hostile.html
>
> * igt@gem_ctx_persistence@legacy-engines-mixed:
> - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3
> similar issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html
>
> * igt@gem_exec_fair@basic-none-rrul@rcs0:
> - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-kbl4/igt@gem_exec_fair@basic-none-r...@rcs0.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-kbl4/igt@gem_exec_fair@basic-none-r...@rcs0.html
>
> * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html
>
> * igt@gem_exec_fair@basic-none-vip@rcs0:
> - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842])
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842])
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>
> * igt@gem_exec_whisper@basic-queues-forked-all:
> - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-glk2/igt@gem_exec_whis...@basic-queues-forked-all.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-glk3/igt@gem_exec_whis...@basi
[Intel-gfx] [PATCH v2 2/6] drm/i915/dp: Ensure sink rate values are always valid
Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
DPCD capabilities are successfully read from the sink. During this time
intel_dp->num_common_rates is 0 which can lead to a
intel_dp->common_rates[-1](*)
access, which is an undefined behaviour, in the following cases:
- In intel_dp_sync_state(), if the encoder is enabled without a sink
connected to the encoder's connector (BIOS enabled a monitor, but the
user unplugged the monitor until the driver loaded).
- In intel_dp_sync_state() if the encoder is enabled with a sink
connected, but for some reason the DPCD read has failed.
- In intel_dp_compute_link_config() if modesetting a connector without
a sink connected on it.
- In intel_dp_compute_link_config() if modesetting a connector with a
a sink connected on it, but before probing the connector first.
To avoid the (*) access in all the above cases, make sure that the sink
rate table - and hence the common rate table - is always valid, by
setting a default minimum sink rate when registering the connector
before anything could use it.
I also considered setting all the DP link rates by default, so that
modesetting with higher resolution modes also succeeds in the last two
cases above. However in case a sink is not connected that would stop
working after the first modeset, due to the LT fallback logic. So this
would need more work, beyond the scope of this fix.
As I mentioned in the previous patch, I don't think the issue this patch
fixes is user visible, however it is an undefined behaviour by
definition and triggers a BUG() in CONFIG_UBSAN builds, hence CC:stable.
v2: Clear the default sink rates, before initialzing these for eDP.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc:
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 23de500d56b52..9cbe85746fc41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state
*crtc_state)
return crtc_state->port_clock >= 100;
}
+static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
+{
+ intel_dp->sink_rates[0] = 162000;
+ intel_dp->num_sink_rates = 1;
+}
+
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
@@ -2556,6 +2562,9 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
*/
intel_psr_init_dpcd(intel_dp);
+ /* Clear the default sink rates */
+ intel_dp->num_sink_rates = 0;
+
/* Read the eDP 1.4+ supported link rates. */
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
@@ -5003,6 +5012,8 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
}
intel_dp_set_source_rates(intel_dp);
+ intel_dp_set_default_sink_rates(intel_dp);
+ intel_dp_set_common_rates(intel_dp);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
--
2.27.0
Re: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid
On Mon, Oct 18, 2021 at 06:04:18PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 18, 2021 at 12:41:52PM +0300, Imre Deak wrote:
> > Print an error if the DPCD sink max lane count is invalid and fix it up.
> >
> > While at it also add an assert that the link max lane count (derived
> > from intel_dp_max_common_lane_count(), potentially reduced by the LT
> > fallback logic) value is also valid.
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_types.h| 2 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 44 ++-
> > 2 files changed, 44 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 39e11eaec1a3f..1e42bf901263c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1563,6 +1563,8 @@ struct intel_dp {
> > int num_sink_rates;
> > int sink_rates[DP_MAX_SUPPORTED_RATES];
> > bool use_rate_select;
> > + /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
> > + int max_sink_lane_count;
> > /* intersection of source and sink rates */
> > int num_common_rates;
> > int common_rates[DP_MAX_SUPPORTED_RATES];
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1935eb49f9574..f7711779df132 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -197,6 +197,35 @@ static void intel_dp_set_sink_rates(struct intel_dp
> > *intel_dp)
> > intel_dp->num_sink_rates = i;
> > }
> >
> > +static void intel_dp_set_default_max_sink_lane_count(struct intel_dp
> > *intel_dp)
> > +{
> > + intel_dp->max_sink_lane_count = 1;
> > +}
> > +
> > +static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
> > +{
> > + struct intel_connector *connector = intel_dp->attached_connector;
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > + struct intel_encoder *encoder = &intel_dig_port->base;
> > +
> > + intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> > +
> > + switch (intel_dp->max_sink_lane_count) {
> > + case 1:
> > + case 2:
> > + case 4:
> > + return;
> > + }
> > +
> > + drm_err(&dp_to_i915(intel_dp)->drm,
> > + "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count
> > (%d), using default\n",
> > + connector->base.base.id, connector->base.name,
> > + encoder->base.base.id, encoder->base.name,
> > + intel_dp->max_sink_lane_count);
> > +
> > + intel_dp_set_default_max_sink_lane_count(intel_dp);
> > +}
> > +
> > /* Get length of rates array potentially limited by max_rate. */
> > static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
> > {
> > @@ -230,7 +259,7 @@ static int intel_dp_max_common_lane_count(struct
> > intel_dp *intel_dp)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > int source_max = dig_port->max_lanes;
> > - int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> > + int sink_max = intel_dp->max_sink_lane_count;
> > int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> > int lttpr_max =
> > drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
> >
> > @@ -242,7 +271,15 @@ static int intel_dp_max_common_lane_count(struct
> > intel_dp *intel_dp)
> >
> > int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > {
> > - return intel_dp->max_link_lane_count;
> > + switch (intel_dp->max_link_lane_count) {
> > + case 1:
> > + case 2:
> > + case 4:
> > + return intel_dp->max_link_lane_count;
> > + default:
> > + MISSING_CASE(intel_dp->max_link_lane_count);
> > + return 1;
> > + }
> > }
>
> I guess this is just a second level sanity check. I was wondering it
> gets confusing and people start thinking this can actually happen,
> but I suppose the MISSING_CASE() should be indication enough that it
> in fact should not happen.
Yes it shouldn't happen. Given that we don't consider the FIA reg value
external, but I think that's
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Simplify handling of modifiers (rev10)
On Mon, Oct 18, 2021 at 06:42:38PM +0300, Petri Latvala wrote:
> On Mon, Oct 18, 2021 at 03:10:54PM +0300, Imre Deak wrote:
> > Hi Petri, Tomi,
> >
> > could you check the failure below?
> >
> > On Fri, Oct 15, 2021 at 11:19:13AM +, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: drm/i915: Simplify handling of modifiers (rev10)
> > > URL : https://patchwork.freedesktop.org/series/95579/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > CI Bug Log - changes from CI_DRM_10741_full -> Patchwork_21343_full
> > >
> > >
> > > Summary
> > > ---
> > >
> > > **FAILURE**
> > >
> > > Serious unknown changes coming with Patchwork_21343_full absolutely
> > > need to be
> > > verified manually.
> > >
> > > If you think the reported changes have nothing to do with the changes
> > > introduced in Patchwork_21343_full, please notify your bug team to
> > > allow them
> > > to document this new failure mode, which will reduce false positives in
> > > CI.
> > >
> > > Possible new issues
> > > ---
> > >
> > > Here are the unknown changes that may have been introduced in
> > > Patchwork_21343_full:
> > >
> > > ### IGT changes ###
> > >
> > > Possible regressions
> > >
> > > * igt@kms_vblank@pipe-a-wait-busy:
> > > - shard-skl: [PASS][1] -> [INCOMPLETE][2]
> > >[1]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10741/shard-skl1/igt@kms_vbl...@pipe-a-wait-busy.html
> > >[2]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-skl1/igt@kms_vbl...@pipe-a-wait-busy.html
> >
> > This is from Patchwork_21343/shard-skl1/19/dmesg.log , where the above
> > test passes and is followed by more passing tests, until
> > kms_busy/extended-modeset-hang-oldfb
> >
> > also passes at least according to igt_runner.log, though I can't see it in
> > dmesg.log. After that:
> >
> > [1091.672412] Overall timeout time exceeded, stopping.
> >
> > Is it just an overall timeout problem, or some test after
> > kms_busy/extended-modeset-hand-oldfb?
>
> The test passed but igt_runner's journal.txt for it was left
> empty. Reason for that is unknown (fs corruption, or something like
> that). Because overall timeout got triggered, igt_results was invoked
> against that shard execution in jenkins master host, overwriting the
> DUT-written one, and because the journal didn't state the subtest
> started, it was parsed as being incomplete.
Ok. Maybe igt_runner could sync/stat the file if the write happened as
expected? I can see the same truncation at least on the following
shard-skl test runs:
CI_DRM_10743/shard-skl7/16/118/journal.txt
Patchwork_21337/shard-skl9/15/45/journal.txt
Patchwork_21343/shard-skl1/19/72/journal.txt
Patchwork_21302/shard-skl7/23/45/journal.txt
Patchwork_21362/shard-skl8/21/12/journal.txt
Patchwork_21317/shard-skl3/11/0/journal.txt
I can't see anything obvious in dmesg, so I think the issue is unrelated
to changes in the patchset. Would it make sense to open a ticket for the
above particular file-truncated issue?
> The logs unfortunately were not able to give any indication as to why
> the journal file was left empty. igt_runner syncs it when writing to
> it, and the test execution continued normally after that particular
> test.
> --
> Petri Latvala
>
>
> >
> > > Suppressed
> > >
> > > The following results come from untrusted machines, tests, or statuses.
> > > They do not affect the overall result.
> > >
> > > * {igt@kms_bw@linear-tiling-3-displays-3840x2160p}:
> > > - shard-snb: NOTRUN -> [FAIL][3]
> > >[3]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-snb6/igt@kms...@linear-tiling-3-displays-3840x2160p.html
> > >
> > > * {igt@kms_bw@linear-tiling-4-displays-1920x1080p}:
> > > - shard-apl: NOTRUN -> [DMESG-FAIL][4]
> > >[4]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21343/shard-apl3/igt@kms...@linear-tiling-4-displays-1920x1080p.html
> > >
> > >
> > > Known issues
> > >
> > >
> > > Here are the changes found in Patchwork_21343_full that come from known
> >
Re: [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote:
> On Mon, 18 Oct 2021, Imre Deak wrote:
> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
> > DPCD capabilities are successfully read from the sink. During this time
> > intel_dp->num_common_rates is 0 which can lead to a
> >
> > intel_dp->common_rates[-1](*)
> >
> > access, which is an undefined behaviour, in the following cases:
> >
> > - In intel_dp_sync_state(), if the encoder is enabled without a sink
> > connected to the encoder's connector (BIOS enabled a monitor, but the
> > user unplugged the monitor until the driver loaded).
> > - In intel_dp_sync_state() if the encoder is enabled with a sink
> > connected, but for some reason the DPCD read has failed.
> > - In intel_dp_compute_link_config() if modesetting a connector without
> > a sink connected on it.
> > - In intel_dp_compute_link_config() if modesetting a connector with a
> > a sink connected on it, but before probing the connector first.
> >
> > To avoid the (*) access in all the above cases, make sure that the sink
> > rate table - and hence the common rate table - is always valid, by
> > setting a default minimum sink rate when registering the connector
> > before anything could use it.
> >
> > I also considered setting all the DP link rates by default, so that
> > modesetting with higher resolution modes also succeeds in the last two
> > cases above. However in case a sink is not connected that would stop
> > working after the first modeset, due to the LT fallback logic. So this
> > would need more work, beyond the scope of this fix.
> >
> > As I mentioned in the previous patch, I don't think the issue this patch
> > fixes is user visible, however it is an undefined behaviour by
> > definition and triggers a BUG() in CONFIG_UBSAN builds, hence CC:stable.
>
> I think the question here, and in the following patches, is whether this
> papers over potential bugs elsewhere.
>
> Would the original bug fixed by patch 1 have been detected if all the
> safeguards here had been in place? Point being, we shouldn't be doing
> any of these things before we've read the dpcd.
Modesets are possible even without a connected sink or a read-out DPCD,
so the link parameters need to be valid even without those.
> BR,
> Jani.
>
>
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Cc:
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 23de500d56b52..153ae944a354b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state
> > *crtc_state)
> > return crtc_state->port_clock >= 100;
> > }
> >
> > +static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> > +{
> > + intel_dp->sink_rates[0] = 162000;
> > + intel_dp->num_sink_rates = 1;
> > +}
> > +
> > /* update sink rates from dpcd */
> > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> > {
> > @@ -5003,6 +5009,8 @@ intel_dp_init_connector(struct intel_digital_port
> > *dig_port,
> > }
> >
> > intel_dp_set_source_rates(intel_dp);
> > + intel_dp_set_default_sink_rates(intel_dp);
> > + intel_dp_set_common_rates(intel_dp);
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
On Tue, Oct 19, 2021 at 10:37:33AM +0300, Jani Nikula wrote:
> On Tue, 19 Oct 2021, Imre Deak wrote:
> > On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote:
> >> On Mon, 18 Oct 2021, Imre Deak wrote:
> >> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
> >> > DPCD capabilities are successfully read from the sink. During this time
> >> > intel_dp->num_common_rates is 0 which can lead to a
> >> >
> >> > intel_dp->common_rates[-1](*)
> >> >
> >> > access, which is an undefined behaviour, in the following cases:
> >> >
> >> > - In intel_dp_sync_state(), if the encoder is enabled without a sink
> >> > connected to the encoder's connector (BIOS enabled a monitor, but the
> >> > user unplugged the monitor until the driver loaded).
> >> > - In intel_dp_sync_state() if the encoder is enabled with a sink
> >> > connected, but for some reason the DPCD read has failed.
> >> > - In intel_dp_compute_link_config() if modesetting a connector without
> >> > a sink connected on it.
> >> > - In intel_dp_compute_link_config() if modesetting a connector with a
> >> > a sink connected on it, but before probing the connector first.
> >> >
> >> > To avoid the (*) access in all the above cases, make sure that the sink
> >> > rate table - and hence the common rate table - is always valid, by
> >> > setting a default minimum sink rate when registering the connector
> >> > before anything could use it.
> >> >
> >> > I also considered setting all the DP link rates by default, so that
> >> > modesetting with higher resolution modes also succeeds in the last two
> >> > cases above. However in case a sink is not connected that would stop
> >> > working after the first modeset, due to the LT fallback logic. So this
> >> > would need more work, beyond the scope of this fix.
> >> >
> >> > As I mentioned in the previous patch, I don't think the issue this patch
> >> > fixes is user visible, however it is an undefined behaviour by
> >> > definition and triggers a BUG() in CONFIG_UBSAN builds, hence CC:stable.
> >>
> >> I think the question here, and in the following patches, is whether this
> >> papers over potential bugs elsewhere.
> >>
> >> Would the original bug fixed by patch 1 have been detected if all the
> >> safeguards here had been in place? Point being, we shouldn't be doing
> >> any of these things before we've read the dpcd.
> >
> > Modesets are possible even without a connected sink or a read-out DPCD,
> > so the link parameters need to be valid even without those.
>
> Modeset on a disconnected DP? How?
Yes, just do a modeset on it. It doesn't have to be disconnected either,
you can modeset a DP connector before probing it.
>
> BR,
> Jani.
>
>
> >
> >> BR,
> >> Jani.
> >>
> >>
> >> >
> >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
> >> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
> >> > Suggested-by: Ville Syrjälä
> >> > Cc: Ville Syrjälä
> >> > Cc:
> >> > Signed-off-by: Imre Deak
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_dp.c | 8
> >> > 1 file changed, 8 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 23de500d56b52..153ae944a354b 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state
> >> > *crtc_state)
> >> > return crtc_state->port_clock >= 100;
> >> > }
> >> >
> >> > +static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> >> > +{
> >> > +intel_dp->sink_rates[0] = 162000;
> >> > +intel_dp->num_sink_rates = 1;
> >> > +}
> >> > +
> >> > /* update sink rates from dpcd */
> >> > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> >> > {
> >> > @@ -5003,6 +5009,8 @@ intel_dp_init_connector(struct intel_digital_port
> >> > *dig_port,
> >> > }
> >> >
> >> > intel_dp_set_source_rates(intel_dp);
> >> > +intel_dp_set_default_sink_rates(intel_dp);
> >> > +intel_dp_set_common_rates(intel_dp);
> >> >
> >> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >> > intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v3 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Tue, Oct 19, 2021 at 10:42:42AM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Juha-Pekka Heikkila wrote:
> > I did prefer v2 bit field graphics version comparison over this {from,
> > until} for the simple reason it had runtime just one AND instead of two
> > separate CMP but either way also for v3
>
> Premature optimization. For maintainability I prefer not adding new ways
> of checking for display version ranges. We already have IS_DISPLAY_VER()
> for that.
>
> ...which makes me wonder why that isn't used here but instead open-coded
> into check_modifier_display_ver()?!?
Because it's not always the device version which is queried, rather is
the modifier support a given display version range? See the follow-up
patch where this is needed.
>
> BR,
> Jani.
>
> >
> > Reviewed-by: Juha-Pekka Heikkila
> >
> > On 15.10.2021 1.09, Imre Deak wrote:
> >> Add a table describing all the framebuffer modifiers used by i915 at one
> >> place. This has the benefit of deduplicating the listing of supported
> >> modifiers for each platform and checking the support of these modifiers
> >> on a given plane. This also simplifies in a similar way getting some
> >> attribute for a modifier, for instance checking if the modifier is a
> >> CCS modifier type.
> >>
> >> While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(),
> >> as the cursor plane is registered with DRM core elsewhere.
> >>
> >> v1: Unchanged.
> >> v2:
> >> - Keep the plane caps calculation in the plane code and pass an enum
> >>with these caps to intel_fb_get_modifiers(). (Ville)
> >> - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
> >>well.
> >> v3:
> >> - s/.id/.modifier/ (Ville)
> >> - Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville)
> >> - Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville)
> >> - Use from, until display version fields in modifier_desc instead of a
> >> mask. (Jani)
> >> - Unexport struct intel_modifier_desc, separate its decl and init. (Jani)
> >> - Remove enum pipe, plane_id forward decls from intel_fb.h, which are
> >>not needed after v2.
> >>
> >> Cc: Ville Syrjälä
> >> Cc: Juha-Pekka Heikkila
> >> Cc: Jani Nikula
> >> Signed-off-by: Imre Deak
> >> Reviewed-by: Juha-Pekka Heikkila (v2)
> >> ---
> >> drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
> >> drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> >> .../drm/i915/display/intel_display_types.h| 1 -
> >> drivers/gpu/drm/i915/display/intel_fb.c | 159
> >> drivers/gpu/drm/i915/display/intel_fb.h | 13 ++
> >> drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> >> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> >> .../drm/i915/display/skl_universal_plane.c| 178 +-
> >> 8 files changed, 252 insertions(+), 184 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> >> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> >> index b1439ba78f67b..a939accff7ee2 100644
> >> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> >> @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
> >>DRM_FORMAT_XBGR16161616F,
> >> };
> >>
> >> -static const u64 i9xx_format_modifiers[] = {
> >> - I915_FORMAT_MOD_X_TILED,
> >> - DRM_FORMAT_MOD_LINEAR,
> >> - DRM_FORMAT_MOD_INVALID
> >> -};
> >> -
> >> static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> >>u32 format, u64 modifier)
> >> {
> >> - switch (modifier) {
> >> - case DRM_FORMAT_MOD_LINEAR:
> >> - case I915_FORMAT_MOD_X_TILED:
> >> - break;
> >> - default:
> >> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> >>return false;
> >> - }
> >>
> >>switch (format) {
> >>case DRM_FORMAT_C8:
> >> @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct
> >> drm_plane *_plane,
> >> static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
> >>u32 format, u64 modifier)
> >> {
> >> - switch (mod
Re: [Intel-gfx] [PATCH v3 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes
On Tue, Oct 19, 2021 at 11:02:45AM +0300, Jani Nikula wrote:
>
> From patch 1:
>
> static bool check_modifier_display_ver(const struct intel_modifier_desc *md,
> u8 display_ver)
> {
> return display_ver >= md->display_ver.from &&
> display_ver <= md->display_ver.until;
> }
>
> On Fri, 15 Oct 2021, Imre Deak wrote:
> > +static bool check_modifier_display_ver_range(const struct
> > intel_modifier_desc *md,
> > +u8 display_ver_from, u8
> > display_ver_until)
> > +{
> > + return check_modifier_display_ver(md, display_ver_from) &&
> > + check_modifier_display_ver(md, display_ver_until);
> > +}
> > +
>
> ...
>
> > +/**
> > + * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is
> > a GEN12 CCS AUX plane
> > + * @fb: Framebuffer
> > + * @color_plane: color plane index to check
> > + *
> > + * Returns:
> > + * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS
> > AUX plane.
> > + */
> > +static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer
> > *fb, int color_plane)
> > {
> > - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> > +
> > + return check_modifier_display_ver_range(md, 12, 13) &&
> > + ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
> > }
>
> check_modifier_display_ver_range(md, 12, 13)
>
> ==>
>
> check_modifier_display_ver(md, 12) &&
> check_modifier_display_ver(md, 13)
>
> ==>
>
> 12 >= md->display_ver.from &&
> 12 <= md->display_ver.until &&
> 13 >= md->display_ver.from &&
> 13 <= md->display_ver.until
>
> ==>
>
> Always false.
If md->display_ver.from=12, md->display_ver.until=13
12 >= 12 &&
12 <= 13 &&
13 >= 12 &&
13 <= 13
not false.
But yes, check_modifier_display_ver_range() is bogus for the
md->display_ver.from == md->display_ver.until case, and should be
md->display_ver.from >= display_ver_from &&
md->display_ver.until <= disaply_ver_until
Thanks for catching this, will fix it.
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v3 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes
On Tue, Oct 19, 2021 at 11:38:33AM +0300, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 11:02:45AM +0300, Jani Nikula wrote:
> >
> > From patch 1:
> >
> > static bool check_modifier_display_ver(const struct intel_modifier_desc *md,
> >u8 display_ver)
> > {
> > return display_ver >= md->display_ver.from &&
> >display_ver <= md->display_ver.until;
> > }
> >
> > On Fri, 15 Oct 2021, Imre Deak wrote:
> > > +static bool check_modifier_display_ver_range(const struct
> > > intel_modifier_desc *md,
> > > + u8 display_ver_from, u8
> > > display_ver_until)
> > > +{
> > > + return check_modifier_display_ver(md, display_ver_from) &&
> > > +check_modifier_display_ver(md, display_ver_until);
> > > +}
> > > +
> >
> > ...
> >
> > > +/**
> > > + * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane
> > > is a GEN12 CCS AUX plane
> > > + * @fb: Framebuffer
> > > + * @color_plane: color plane index to check
> > > + *
> > > + * Returns:
> > > + * Returns %true if @fb's color plane at index @color_plane is a GEN12
> > > CCS AUX plane.
> > > + */
> > > +static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer
> > > *fb, int color_plane)
> > > {
> > > - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> > > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> > > +
> > > + return check_modifier_display_ver_range(md, 12, 13) &&
> > > +ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
> > > }
> >
> > check_modifier_display_ver_range(md, 12, 13)
> >
> > ==>
> >
> > check_modifier_display_ver(md, 12) &&
> > check_modifier_display_ver(md, 13)
> >
> > ==>
> >
> > 12 >= md->display_ver.from &&
> > 12 <= md->display_ver.until &&
> > 13 >= md->display_ver.from &&
> > 13 <= md->display_ver.until
> >
> > ==>
> >
> > Always false.
>
> If md->display_ver.from=12, md->display_ver.until=13
>
> 12 >= 12 &&
> 12 <= 13 &&
> 13 >= 12 &&
> 13 <= 13
>
> not false.
>
> But yes, check_modifier_display_ver_range() is bogus for the
> md->display_ver.from == md->display_ver.until case, and should be
>
> md->display_ver.from >= display_ver_from &&
> md->display_ver.until <= disaply_ver_until
arg the above is still bogus and should be:
check_modifier_display_ver(md, display_ver_from) ||
check_modifier_display_ver(md, display_ver_until);
> Thanks for catching this, will fix it.
>
> > BR,
> > Jani.
> >
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v4 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes
Future platforms change the location of CCS AUX planes in CCS
framebuffers, so add intel_fb_is_ccs_aux_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in CCS AUX planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_aux_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
v1-v2: Unchanged
v3: (Ville)
- Use ccs_aux instead of the ccs_ctrl term everywhere.
- Use color_plane instead of plane term for FB plane indicies.
v4: Fix version range check. (Jani)
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
.../drm/i915/display/intel_display_types.h| 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 82 ++-
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c| 3 +-
4 files changed, 64 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 50b4264f61d62..e3353c2311e52 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2049,11 +2049,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 6e8d600dff6be..d65340d7fd843 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -131,6 +131,8 @@ struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_aux_planes:4;
+ u8 planar_aux_planes:4;
} ccs;
};
@@ -163,6 +165,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -172,6 +175,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_NONE,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -181,6 +185,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_aux_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -190,6 +195,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_aux_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -200,6 +206,8 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_aux_planes = BIT(1),
+ .ccs.planar_aux_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -271,6 +279,13 @@ static bool check_modifier_display_ver(const struct
intel_modifier_desc *md,
display_ver <= md->display_ver.until;
}
+static bool check_modifier_display_ver_range(const struct intel_modifier_desc
*md,
+u8 display_ver_from, u8
display_ver_until)
+{
+ return md->display_ver.from <= display_ver_until &&
+ display_ver_from <= md->display_ver.until;
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
@@ -377,17 +392,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_aux_plane_mask(co
Re: [Intel-gfx] [PATCH v3 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes
On Tue, Oct 19, 2021 at 11:47:45AM +0300, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 11:38:33AM +0300, Imre Deak wrote:
> > On Tue, Oct 19, 2021 at 11:02:45AM +0300, Jani Nikula wrote:
> > >
> > > From patch 1:
> > >
> > > static bool check_modifier_display_ver(const struct intel_modifier_desc
> > > *md,
> > > u8 display_ver)
> > > {
> > > return display_ver >= md->display_ver.from &&
> > > display_ver <= md->display_ver.until;
> > > }
> > >
> > > On Fri, 15 Oct 2021, Imre Deak wrote:
> > > > +static bool check_modifier_display_ver_range(const struct
> > > > intel_modifier_desc *md,
> > > > +u8 display_ver_from, u8
> > > > display_ver_until)
> > > > +{
> > > > + return check_modifier_display_ver(md, display_ver_from) &&
> > > > + check_modifier_display_ver(md, display_ver_until);
> > > > +}
> > > > +
> > >
> > > ...
> > >
> > > > +/**
> > > > + * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane
> > > > is a GEN12 CCS AUX plane
> > > > + * @fb: Framebuffer
> > > > + * @color_plane: color plane index to check
> > > > + *
> > > > + * Returns:
> > > > + * Returns %true if @fb's color plane at index @color_plane is a GEN12
> > > > CCS AUX plane.
> > > > + */
> > > > +static bool intel_fb_is_gen12_ccs_aux_plane(const struct
> > > > drm_framebuffer *fb, int color_plane)
> > > > {
> > > > - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb,
> > > > plane);
> > > > + const struct intel_modifier_desc *md =
> > > > lookup_modifier(fb->modifier);
> > > > +
> > > > + return check_modifier_display_ver_range(md, 12, 13) &&
> > > > + ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
> > > > }
> > >
> > > check_modifier_display_ver_range(md, 12, 13)
> > >
> > > ==>
> > >
> > > check_modifier_display_ver(md, 12) &&
> > > check_modifier_display_ver(md, 13)
> > >
> > > ==>
> > >
> > > 12 >= md->display_ver.from &&
> > > 12 <= md->display_ver.until &&
> > > 13 >= md->display_ver.from &&
> > > 13 <= md->display_ver.until
> > >
> > > ==>
> > >
> > > Always false.
> >
> > If md->display_ver.from=12, md->display_ver.until=13
> >
> > 12 >= 12 &&
> > 12 <= 13 &&
> > 13 >= 12 &&
> > 13 <= 13
> >
> > not false.
> >
> > But yes, check_modifier_display_ver_range() is bogus for the
> > md->display_ver.from == md->display_ver.until case, and should be
> >
> > md->display_ver.from >= display_ver_from &&
> > md->display_ver.until <= disaply_ver_until
>
> arg the above is still bogus and should be:
>
> check_modifier_display_ver(md, display_ver_from) ||
> check_modifier_display_ver(md, display_ver_until);
Somehow the intersect check for two ranges was difficult :/ I hope v4 I
sent is correct.
>
> > Thanks for catching this, will fix it.
> >
> > > BR,
> > > Jani.
> > >
> > >
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
On Tue, Oct 19, 2021 at 01:24:51PM +0300, Jani Nikula wrote: > On Mon, 18 Oct 2021, Vandita Kulkarni wrote: > > MIPI DSI transcoder cannot be in video mode to support any of the > > display C states. > > Imre, could you review this one please? > > The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and > POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and > POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account. You mean they are not listed in the power_domain->power_well mappings. Those power domains don't use any power wells above PW#1. PW#0/1 is handled "automatically" by DMC, so we don't have to toggle the power for those manually. However they still need a runtime PM reference, since whatever HW domain you want to use, the PCI device must be in the runtime resumed state. This is ensured by the always-on power well, which every domain has a dependency on. The transcoder power domains are acquired in get_crtc_power_domains(), doesn't the DSI encoder using the DSI_A/C transcoders? Yes, POWER_DOMAIN_TRANSCODER is now broken wrt. DSI due to POWER_DOMAIN_TRANSCODER_VDSC_PW2. So that would need to be moved after the TRANSCODER_DSI_C. And the POWER_DOMAIN_TRANSCODER macro could be also simplified afaics. Otherwise this patch looks ok to me, just the bspec links would be good to have here too. > > > Signed-off-by: Vandita Kulkarni > > --- > > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 709569211c85..8406db5e573e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct > > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_MODESET) | \ > > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > - BIT_ULL(POWER_DOMAIN_INIT)) > > + BIT_ULL(POWER_DOMAIN_INIT)) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DSI) > > Everywhere else POWER_DOMAIN_INIT is last in the list. > > BR, > Jani. > > > > > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS > > BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) > > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS > > BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) > > -- > Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
Hi Lakshmi, the failure below is expected, could we add cibug filter for it? On Tue, Oct 19, 2021 at 12:52:22AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > URL : https://patchwork.freedesktop.org/series/95948/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_21374_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21374_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21374_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > - shard-apl: NOTRUN -> [FAIL][1] +2 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@kms...@linear-tiling-4-displays-1920x1080p.html The test is broken, since it assumes it can set any mode on any connector. However these modesets won't through a WARN() any more after this change. > Warnings > > * igt@kms_bw@linear-tiling-3-displays-2560x1440p: > - shard-apl: [DMESG-FAIL][2] ([i915#4298]) -> [FAIL][3] +2 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html > > > Known issues > > > Here are the changes found in Patchwork_21374_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_create@create-massive: > - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@gem_cre...@create-massive.html > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1373]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html > > * igt@gem_ctx_param@set-priority-not-supported: > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/igt@gem_ctx_pa...@set-priority-not-supported.html > > * igt@gem_ctx_persistence@legacy-engines-hostile: > - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-hostile.html > > * igt@gem_ctx_persistence@many-contexts: > - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html > > * igt@gem_eio@unwedge-stress: > - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / > [i915#3063] / [i915#3648]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/igt@gem_...@unwedge-stress.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/igt@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar > issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_fair@basic-pace@vcs0: > - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html > > * igt@gem_exec_params@no-blt: > - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109283]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@no-blt.html > > * i
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
On Tue, Oct 19, 2021 at 06:33:12PM +0300, Vudum, Lakshminarayana wrote: > Re-reported. Looks like kms_bw tests are broken? Thanks. Yes, I think so. > -Original Message- > From: Deak, Imre > Sent: Tuesday, October 19, 2021 5:54 AM > To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana > > Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in > lack of a valid DPCD (rev2) > > Hi Lakshmi, > > the failure below is expected, could we add cibug filter for it? > > On Tue, Oct 19, 2021 at 12:52:22AM +, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > > URL : https://patchwork.freedesktop.org/series/95948/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_21374_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_21374_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_21374_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > > - shard-apl: NOTRUN -> [FAIL][1] +2 similar issues > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > > t@kms...@linear-tiling-4-displays-1920x1080p.html > > The test is broken, since it assumes it can set any mode on any connector. > However these modesets won't through a WARN() any more after this change. > > > Warnings > > > > * igt@kms_bw@linear-tiling-3-displays-2560x1440p: > > - shard-apl: [DMESG-FAIL][2] ([i915#4298]) -> [FAIL][3] +2 > > similar issues > >[2]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html > >[3]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl7/ig > > t@kms...@linear-tiling-3-displays-2560x1440p.html > > > > > > Known issues > > > > > > Here are the changes found in Patchwork_21374_full that come from known > > issues: > > > > ### IGT changes ### > > > > Issues hit > > > > * igt@gem_create@create-massive: > > - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) > >[4]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > > t@gem_cre...@create-massive.html > > > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1373]) > >[5]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html > >[6]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/i > > gt@gem_ctx_isolation@preservation...@rcs0.html > > > > * igt@gem_ctx_param@set-priority-not-supported: > > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314]) > >[7]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/i > > gt@gem_ctx_pa...@set-priority-not-supported.html > > > > * igt@gem_ctx_persistence@legacy-engines-hostile: > > - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) > >[8]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/ig > > t@gem_ctx_persiste...@legacy-engines-hostile.html > > > > * igt@gem_ctx_persistence@many-contexts: > > - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410]) > >[9]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/i > > gt@gem_ctx_persiste...@many-contexts.html > > > > * igt@gem_eio@unwedge-stress: > > - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / > > [i915#3063] / [i915#3648]) > >[10]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html > >[11]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/i > > gt@gem_...@unwedge-stress.html > > > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > > - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) > >[12]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/ig > > t@gem_exec_fair@basic-none-r...@rcs0.html > > > > * igt@gem_exec_fair@basic-pace@rcs0: > > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar > > issue > >[13]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs
Re: [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
On Tue, Oct 19, 2021 at 10:39:08AM +0300, Imre Deak wrote: > On Tue, Oct 19, 2021 at 10:37:33AM +0300, Jani Nikula wrote: > > On Tue, 19 Oct 2021, Imre Deak wrote: > > > On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote: > > >> On Mon, 18 Oct 2021, Imre Deak wrote: > > >> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until the > > >> > DPCD capabilities are successfully read from the sink. During this time > > >> > intel_dp->num_common_rates is 0 which can lead to a > > >> > > > >> > intel_dp->common_rates[-1](*) > > >> > > > >> > access, which is an undefined behaviour, in the following cases: > > >> > > > >> > - In intel_dp_sync_state(), if the encoder is enabled without a sink > > >> > connected to the encoder's connector (BIOS enabled a monitor, but the > > >> > user unplugged the monitor until the driver loaded). > > >> > - In intel_dp_sync_state() if the encoder is enabled with a sink > > >> > connected, but for some reason the DPCD read has failed. > > >> > - In intel_dp_compute_link_config() if modesetting a connector without > > >> > a sink connected on it. > > >> > - In intel_dp_compute_link_config() if modesetting a connector with a > > >> > a sink connected on it, but before probing the connector first. > > >> > > > >> > To avoid the (*) access in all the above cases, make sure that the sink > > >> > rate table - and hence the common rate table - is always valid, by > > >> > setting a default minimum sink rate when registering the connector > > >> > before anything could use it. > > >> > > > >> > I also considered setting all the DP link rates by default, so that > > >> > modesetting with higher resolution modes also succeeds in the last two > > >> > cases above. However in case a sink is not connected that would stop > > >> > working after the first modeset, due to the LT fallback logic. So this > > >> > would need more work, beyond the scope of this fix. > > >> > > > >> > As I mentioned in the previous patch, I don't think the issue this > > >> > patch > > >> > fixes is user visible, however it is an undefined behaviour by > > >> > definition and triggers a BUG() in CONFIG_UBSAN builds, hence > > >> > CC:stable. > > >> > > >> I think the question here, and in the following patches, is whether this > > >> papers over potential bugs elsewhere. > > >> > > >> Would the original bug fixed by patch 1 have been detected if all the > > >> safeguards here had been in place? Point being, we shouldn't be doing > > >> any of these things before we've read the dpcd. > > > > > > Modesets are possible even without a connected sink or a read-out DPCD, > > > so the link parameters need to be valid even without those. > > > > Modeset on a disconnected DP? How? > > Yes, just do a modeset on it. It doesn't have to be disconnected either, > you can modeset a DP connector before probing it. Jani, any objections to merge patches 2-6 as well? In a summary the reasons: - Fix userspace triggerable WARNs(). - Fix undefined behavior triggerring BUG() in UBSAN builds (in addition to the case the first patch fixes). - Validate the DP_MAX_LINK_RATE value we read from DPCD. - It unifies some open-coded functionality (patch 3 and 6). > > BR, > > Jani. > > > > > > > > > >> BR, > > >> Jani. > > >> > > >> > > >> > > > >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297 > > >> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298 > > >> > Suggested-by: Ville Syrjälä > > >> > Cc: Ville Syrjälä > > >> > Cc: > > >> > Signed-off-by: Imre Deak > > >> > --- > > >> > drivers/gpu/drm/i915/display/intel_dp.c | 8 > > >> > 1 file changed, 8 insertions(+) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > >> > b/drivers/gpu/drm/i915/display/intel_dp.c > > >> > index 23de500d56b52..153ae944a354b 100644 > > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > >> > +++ b/drivers/gpu/drm/i915/display/in
Re: [Intel-gfx] [PATCH 6/6] drm/i915/dp: Sanitize link common rate array lookups
On Tue, Oct 19, 2021 at 10:23:14PM +0300, Jani Nikula wrote:
> On Mon, 18 Oct 2021, Imre Deak wrote:
> > Add an assert that lookups from the intel_dp->common_rates[] array
> > are always valid.
>
> The one thought I had here was that if we're adding helper functions for
> accessing common rates, they should probably be of the form "this is the
> rate I have now, give me a slower rate" instead of making the index part
> of the interface. The index doesn't really mean anything, and if we want
> to avoid overflows, it should be hidden from the interfaces.
intel_dp_rate_index() is also part of the interface, but I suppose it
could be improved.
> But again, can be follow-up.
>
> BR,
> Jani.
>
>
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 33 -
> > 1 file changed, 16 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index f8082eb8e7263..3869d454c10f0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -267,10 +267,19 @@ static int intel_dp_common_len_rate_limit(const
> > struct intel_dp *intel_dp,
> >intel_dp->num_common_rates, max_rate);
> > }
> >
> > +static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
> > +{
> > + if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> > + index < 0 || index >= intel_dp->num_common_rates))
> > + return 162000;
> > +
> > + return intel_dp->common_rates[index];
> > +}
> > +
> > /* Theoretical max between source and sink */
> > static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> > {
> > - return intel_dp->common_rates[intel_dp->num_common_rates - 1];
> > + return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> > }
> >
> > /* Theoretical max between source and sink */
> > @@ -610,13 +619,13 @@ int intel_dp_get_link_train_fallback_values(struct
> > intel_dp *intel_dp,
> > if (index > 0) {
> > if (intel_dp_is_edp(intel_dp) &&
> > !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> > -
> > intel_dp->common_rates[index - 1],
> > +
> > intel_dp_common_rate(intel_dp, index - 1),
> > lane_count)) {
> > drm_dbg_kms(&i915->drm,
> > "Retrying Link training for eDP with same
> > parameters\n");
> > return 0;
> > }
> > - intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
> > + intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
> > - 1);
> > intel_dp->max_link_lane_count = lane_count;
> > } else if (lane_count > 1) {
> > if (intel_dp_is_edp(intel_dp) &&
> > @@ -1056,14 +1065,11 @@ static void intel_dp_print_rates(struct intel_dp
> > *intel_dp)
> > int
> > intel_dp_max_link_rate(struct intel_dp *intel_dp)
> > {
> > - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > int len;
> >
> > len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
> > - if (drm_WARN_ON(&i915->drm, len <= 0))
> > - return 162000;
> >
> > - return intel_dp->common_rates[len - 1];
> > + return intel_dp_common_rate(intel_dp, len - 1);
> > }
> >
> > int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> > @@ -1260,7 +1266,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> > *intel_dp,
> >output_bpp);
> >
> > for (i = 0; i < intel_dp->num_common_rates; i++) {
> > - link_rate = intel_dp->common_rates[i];
> > + link_rate = intel_dp_common_rate(intel_dp, i);
> > if (link_rate < limits->min_rate ||
> > link_rate > limits->max_rate)
> > continue;
> > @@ -1508,17 +1514,10 @@ intel_dp_compute_link_config(struct intel_encoder
> > *encoder,
>
Re: [Intel-gfx] [PATCH v3 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
On Wed, Oct 20, 2021 at 12:40:30PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 01:09:11AM +0300, Imre Deak wrote:
> > +static const struct intel_modifier_desc intel_modifiers[] = {
> > + {
> > + .modifier = DRM_FORMAT_MOD_LINEAR,
> > + .display_ver = DISPLAY_VER_ALL,
> > +
> > + .is_linear = true,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_X_TILED,
> > + .display_ver = DISPLAY_VER_ALL,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Y_TILED,
> > + .display_ver = { 9, 13 },
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Yf_TILED,
> > + .display_ver = { 9, 11 },
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
> > + .display_ver = { 9, 11 },
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
> > + .display_ver = { 9, 11 },
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > + .display_ver = { 12, 13 },
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > + .display_ver = { 12, 13 },
> > +
> > + .ccs.type = INTEL_CCS_RC_CC,
> > + },
> > + {
> > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > + .display_ver = { 12, 13 },
> > +
> > + .ccs.type = INTEL_CCS_MC,
> > + },
> > +};
> > +
>
> > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> > + enum intel_plane_caps plane_caps)
> > +{
> > + u64 *list, *p;
> > + int count = 1; /* +1 for invalid modifier terminator */
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> > + count++;
> > + }
> > +
> > + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
> > + if (drm_WARN_ON(&i915->drm, !list))
> > + return NULL;
> > +
> > + p = list;
> > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> > + *p++ = intel_modifiers[i].modifier;
> > + }
> > + *p++ = DRM_FORMAT_MOD_INVALID;
>
> Oh, one thing I just realized is that this will now list the modifiers
> in the opposite order to what we had before. Previously we had roughly
> compressed->tiled->linear order. I'm not sure sure anything relies on
> that, but seems best to try and preserve it. I guess one could think
> of it as some kind of priority order for the modifiers, where the more
> efficient ones (in some sense) come first.
Hm, right that was subtle, thanks for catching it.
As I understood Mesa (for instance) has to know what kind of modifiers
it sees and do a priority reorder for other clients anyway (which don't
know more about the mods besides the ID?).
+Danvet.
But the order shouldn't definitely be changed if there is no reason for
it. Ensuring some priority order scheme already at the kernel i/f makes
also sense to me. So if it's ok, I'll fix it up to be in the
gen12_mc -> gen12_rc -> gen12_rc_cc -> gen9_yf_rc -> gen9_y_rc -> yf_tiled ->
y_tiled -> x_tiled -> linear
order, which is the current one.
For that matter, shouldn't gen12_rc_cc be before gen12_rc?
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
On Tue, Oct 19, 2021 at 02:45:53PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > URL : https://patchwork.freedesktop.org/series/95948/ > State : success Pushed to drm-intel-next, thanks for the reviews. > > == Summary == > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_21374_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_create@create-massive: > - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@gem_cre...@create-massive.html > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > - shard-tglb: [PASS][2] -> [INCOMPLETE][3] ([i915#1373]) >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html > > * igt@gem_ctx_param@set-priority-not-supported: > - shard-iclb: NOTRUN -> [SKIP][4] ([fdo#109314]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/igt@gem_ctx_pa...@set-priority-not-supported.html > > * igt@gem_ctx_persistence@legacy-engines-hostile: > - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-hostile.html > > * igt@gem_ctx_persistence@many-contexts: > - shard-tglb: NOTRUN -> [FAIL][6] ([i915#2410]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html > > * igt@gem_eio@unwedge-stress: > - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / > [i915#3063] / [i915#3648]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/igt@gem_...@unwedge-stress.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-glk: NOTRUN -> [FAIL][9] ([i915#2842]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/igt@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar > issue >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_fair@basic-pace@vcs0: > - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html > > * igt@gem_exec_params@no-blt: > - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109283]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@no-blt.html > > * igt@gem_exec_params@secure-non-master: > - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112283]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@secure-non-master.html > > * igt@gem_exec_schedule@u-semaphore-user: > - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +195 similar > issues >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_exec_sched...@u-semaphore-user.html > > * igt@gem_huc_copy@huc-copy: > - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl3/igt@gem_huc_c...@huc-copy.html > > * igt@gem_mmap_gtt@coherency: > - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111656]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_mmap_...@coherency.html > > * igt@gem_pread@exhaustion: > - shard-tglb: NOTRUN -> [WARN][19] ([i915#2658]) >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_pr...@exhaustion.html > > * igt@gem_pxp@reject-modify-context-protection-on: > - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270]) >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_...@reject-modify-context-protection-on.html > >
[Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers
This is v4 of [1] addressing review comments from Jani and Ville in patch 1 and 9. [1] https://patchwork.freedesktop.org/series/95579/ Cc: Juha-Pekka Heikkila Cc: Ville Syrjälä Cc: Jani Nikula Imre Deak (11): drm/i915: Add a table with a descriptor for all i915 modifiers drm/i915: Move intel_get_format_info() to intel_fb.c drm/i915: Add tiling attribute to the modifier descriptor drm/i915: Simplify the modifier check for interlaced scanout support drm/i915: Unexport is_semiplanar_uv_plane() drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c drm/i915: Add a platform independent way to get the RC CCS CC plane drm/i915: Handle CCS CC planes separately from CCS AUX planes drm/i915: Add a platform independent way to check for CCS AUX planes drm/i915: Move is_ccs_modifier() to intel_fb.c drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 150 + drivers/gpu/drm/i915/display/intel_display.h | 3 - .../drm/i915/display/intel_display_types.h| 17 - drivers/gpu/drm/i915/display/intel_fb.c | 526 -- drivers/gpu/drm/i915/display/intel_fb.h | 30 +- drivers/gpu/drm/i915/display/intel_sprite.c | 35 +- drivers/gpu/drm/i915/display/skl_scaler.c | 1 + .../drm/i915/display/skl_universal_plane.c| 206 ++- drivers/gpu/drm/i915/intel_pm.c | 1 + 12 files changed, 612 insertions(+), 407 deletions(-) -- 2.27.0
[Intel-gfx] [PATCH v4 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
v1: Unchanged.
v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
userspace. (CI/igt_kms_addfb_basic/addfb25-bad-modifier)
v3: Move lookup_modifier() to the next patch, where it's first used.
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +---
drivers/gpu/drm/i915/display/intel_fb.c | 153 +++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 157 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 79a7552af7b5e..86333c0cd7937 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -669,136 +669,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h
= { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h
= { 1, 1, 1, 1 },
- .hsub
[Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(),
as the cursor plane is registered with DRM core elsewhere.
v1: Unchanged.
v2:
- Keep the plane caps calculation in the plane code and pass an enum
with these caps to intel_fb_get_modifiers(). (Ville)
- Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
well.
v3:
- s/.id/.modifier/ (Ville)
- Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville)
- Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville)
- Use from, until display version fields in modifier_desc instead of a mask.
(Jani)
- Unexport struct intel_modifier_desc, separate its decl and init. (Jani)
- Remove enum pipe, plane_id forward decls from intel_fb.h, which are
not needed after v2.
v4:
- Reuse IS_DISPLAY_VER() instead of open-coding it. (Jani)
- Preserve the current modifier order exposed to user space. (Ville)
Cc: Ville Syrjälä
Cc: Juha-Pekka Heikkila
Cc: Jani Nikula
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila (v3)
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 152 +++
drivers/gpu/drm/i915/display/intel_fb.h | 13 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 178 +-
8 files changed, 245 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67b..a939accff7ee2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
DRM_FORMAT_XBGR16161616F,
};
-static const u64 i9xx_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane,
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
+ const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->disable_flip_done = ilk_primary_disable_flip_done;
}
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
+
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+
[Intel-gfx] [PATCH v4 03/11] drm/i915: Add tiling attribute to the modifier descriptor
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
v1-v2: Unchanged.
v3:
- Initialize .tiling to I915_TILING_NONE explicitly (Ville)
- Move from previous patch lookup_modifier() to here, where it's first
used.
Cc: Juha-Pekka Heikkila
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 31 +++--
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 539c23c1c9990..8982cfa7205fe 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -120,6 +120,7 @@ struct intel_modifier_desc {
.formats = format_list, \
.format_count = ARRAY_SIZE(format_list)
+ u8 tiling;
u8 is_linear:1;
struct {
@@ -136,6 +137,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -144,6 +146,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -152,6 +155,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_ver = { 12, 13 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -168,6 +172,7 @@ static const struct intel_modifier_desc intel_modifiers[] =
{
{
.modifier = I915_FORMAT_MOD_Y_TILED_CCS,
.display_ver = { 9, 11 },
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -180,14 +185,17 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
{
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
+ .tiling = I915_TILING_Y,
},
{
.modifier = I915_FORMAT_MOD_X_TILED,
.display_ver = DISPLAY_VER_ALL,
+ .tiling = I915_TILING_X,
},
{
.modifier = DRM_FORMAT_MOD_LINEAR,
.display_ver = DISPLAY_VER_ALL,
+ .tiling = I915_TILING_NONE,
.is_linear = true,
},
@@ -204,6 +212,16 @@ static const struct intel_modifier_desc
*lookup_modifier_or_null(u64 modifier)
return NULL;
}
+static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
+{
+ const struct intel_modifier_desc *md =
lookup_modifier_or_null(modifier);
+
+ if (WARN_ON(!md))
+ return &intel_modifiers[0];
+
+ return md;
+}
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -528,18 +546,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
