this by updating the adjusted_mode.crtc_* fields when we set the
fixed panel mode.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_panel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
path as well.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0b38f88..4a13523 100644
--- a/drivers/gpu/drm/i915
=77565
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d49ec02..19020e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu
On Mon, 2014-04-21 at 13:34 +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
Signed-off-by: Deepak S deepa...@linux.intel.com
---
for the pipe.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index
I915_WRITE(DISPLAY_PHY_CONTROL, val | PHY_COM_LANE_RESET_DEASSERT(phy));
The above issues are minor, so even without fixing them this patch is
Reviewed-by: Imre Deak imre.d...@intel.com
+ }
+
+ } else {
+ /*
+ * From
On Mon, 2014-04-28 at 14:57 -0300, Paulo Zanoni wrote:
2014-04-25 5:08 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Fri, Apr 25, 2014 at 10:29:57AM +0300, Imre Deak wrote:
The PC8 state won't be entered unless runtime PM is enabled, so support
for PC8 residency counters alone is not enough
On Mon, 2014-04-28 at 15:35 -0300, Paulo Zanoni wrote:
2014-04-28 15:22 GMT-03:00 Imre Deak imre.d...@intel.com:
On Mon, 2014-04-28 at 14:57 -0300, Paulo Zanoni wrote:
2014-04-25 5:08 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Fri, Apr 25, 2014 at 10:29:57AM +0300, Imre Deak wrote
On Mon, 2014-04-28 at 15:35 -0300, Paulo Zanoni wrote:
2014-04-28 15:22 GMT-03:00 Imre Deak imre.d...@intel.com:
On Mon, 2014-04-28 at 14:57 -0300, Paulo Zanoni wrote:
2014-04-25 5:08 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Fri, Apr 25, 2014 at 10:29:57AM +0300, Imre Deak wrote
On Mon, 2014-04-28 at 21:23 +0200, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 8:14 PM, Paulo Zanoni przan...@gmail.com wrote:
This can probably be reproduced on non-BDW machines too, with RC6 disabled.
If I understand Imre's patch correctly the bug is that we didn't have
rc6 on bdw, but
Lee chon.ming@intel.com
[vsyrjala: Avoid div-by-zero in chv_clock()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Took a while to understand all the different clock rates along the path,
but it looks ok:
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915
reset.
v5: Squash in fixup from Rafael Barbalho.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chon Ming Lee chon.ming@intel.com
A couple of nitpicks below, fixing any/all of those is optional. This
patch is
Reviewed-by: Imre Deak imre.d...@intel.com
Ming Lee chon.ming@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
[vsyrjala: Don't touch panel power sequencing on DP]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Looks ok, so:
Reviewed-by: Imre Deak imre.d...@intel.com
Some nitpicks follow, fixing them
registers are added.
For HDMI, VLV uses bit 30, CHV uses bit 24-25.
For DP, VLV uses bit 30, CHV uses bit 16-17.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chon Ming Lee chon.ming@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915
callback
drm/i915/crt: Remove -mode_set callback
drm/i915/sdvo: Remove -mode_set callback
Removal of encoder-mode_set callbacks, part 1
Reviewer: Imre
1-9 look good to me:
Reviewed-by: Imre Deak imre.d...@intel.com
drm/i915/hdmi: Enable hdmi mode on g4x, too
drm/i915: Track
On Wed, 2014-04-30 at 21:05 +0300, Ville Syrjälä wrote:
On Tue, Apr 15, 2014 at 04:39:45PM +0300, Imre Deak wrote:
Atm, none of the RPM callbacks can fail, but the next patch adding
RPM support for VLV changes this, so prepare for it.
In case one of these callbacks return error RPM
On Wed, 2014-04-30 at 13:41 -0700, Ben Widawsky wrote:
On Wed, Apr 30, 2014 at 01:34:36PM -0700, Kristen Carlson Accardi wrote:
On Tue, 29 Apr 2014 22:31:49 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Apr 09, 2014 at 11:44:06AM -0700, Tom O'Rourke wrote:
Higher RC6 residency
register prefixes
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
[ rebased (according to v4) ]
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 327
drivers/gpu/drm/i915/i915_drv.h | 62
2 files changed
.
Suggested by Ville.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4024e16..2d4bb48 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
On Tue, 2014-05-06 at 12:40 +0100, Chris Wilson wrote:
On Tue, May 06, 2014 at 02:28:50PM +0300, Imre Deak wrote:
Currently user space can access GEM buffers mapped to GTT through
existing mappings concurrently while the platform specific suspend
handlers are running. Since these handlers
On Tue, 2014-05-06 at 12:59 +0100, Chris Wilson wrote:
On Tue, May 06, 2014 at 02:42:26PM +0300, Imre Deak wrote:
On Tue, 2014-05-06 at 12:40 +0100, Chris Wilson wrote:
On Tue, May 06, 2014 at 02:28:50PM +0300, Imre Deak wrote:
Currently user space can access GEM buffers mapped to GTT
On Tue, 2014-05-06 at 21:27 +0200, Daniel Vetter wrote:
On Tue, May 06, 2014 at 05:46:01PM +0300, Imre Deak wrote:
On Tue, 2014-05-06 at 12:59 +0100, Chris Wilson wrote:
On Tue, May 06, 2014 at 02:42:26PM +0300, Imre Deak wrote:
On Tue, 2014-05-06 at 12:40 +0100, Chris Wilson wrote
-by: Imre Deak imre.d...@intel.com
drm/i915: Make -update_primary_plane infallible
drm/i915: More cargo-culted locking for intel_update_fbc
drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
drm/i915: Inline set_base into crtc_mode_set
drm/i915: Move fb pinning
i915_gem_release_all_mmaps() (Chris, Daniel)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index
On Wed, 2014-05-07 at 19:57 +0300, Imre Deak wrote:
Currently user space can access GEM buffers mapped to GTT through
existing mappings concurrently while the platform specific suspend
handlers are running. Since these handlers may change the HW state in a
way that would break such accesses
for the pipe.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index
, while second phy is only for port D.
v2: Move the pipe to determine which phy to select for
vlv_dpio_read/vlv_dpio_write to another patch. (Daniel)
v3: Rebase the code based on rework on how to calculate DPIO offset.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
Reviewed-by: Imre Deak
-by: Imre Deak imre.d...@intel.com
#define _MASKED_BIT_ENABLE(a) (((a) 16) | (a))
#define _MASKED_BIT_DISABLE(a) ((a) 16)
@@ -1385,6 +1387,10 @@ enum punit_power_well {
#define DPLL_PORTB_READY_MASK (0xf)
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f
-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++--
drivers/gpu/drm/i915/i915_suspend.c | 2 --
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2413fc3..855295a 100644
--- a/drivers
In
commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae
Author: Imre Deak imre.d...@intel.com
Date: Mon Apr 14 20:24:29 2014 +0300
drm/i915: get a runtime PM ref for the deferred GT powersave enabling
I added an RPM get-ref when enabling RPS from a deferred work, but forgot
to add
On Mon, 2014-05-12 at 19:51 +0200, Daniel Vetter wrote:
On Mon, May 12, 2014 at 06:35:04PM +0300, Imre Deak wrote:
In
commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae
Author: Imre Deak imre.d...@intel.com
Date: Mon Apr 14 20:24:29 2014 +0300
drm/i915: get a runtime PM ref
On Tue, 2014-05-13 at 15:54 +0200, Daniel Vetter wrote:
On Tue, May 13, 2014 at 04:46:10PM +0300, Imre Deak wrote:
On Mon, 2014-05-12 at 19:51 +0200, Daniel Vetter wrote:
On Mon, May 12, 2014 at 06:35:04PM +0300, Imre Deak wrote:
In
commit
from the vlv
runtime pm code and unexport the internal function from i915_irq.c
again. Yay!
v2: Keep the display irq disabling, spotted by Imre.
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers
these registers are reset and failing to program them results
in a blank screen.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915
These opcodes are not specific for an endpoint, but are the same for all
endpoints. So rename them accordingly, using the name the VLV2 sideband
HAS uses. Also move the macros to the .c file, since they aren't used
anywhere else.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm
These opcodes are not specific for an endpoint, but are the same for all
endpoints. So rename them accordingly, using the name the VLV2 sideband
HAS uses. Also move the macros to the .c file, since they aren't used
anywhere else.
Signed-off-by: Imre Deak imre.d...@intel.com
---
lib/intel_iosf.c
Signed-off-by: Imre Deak imre.d...@intel.com
---
lib/intel_io.h | 2 ++
lib/intel_iosf.c | 14 ++
tools/quick_dump/chipset.i | 2 ++
tools/quick_dump/quick_dump.py | 2 ++
tools/quick_dump/reg_access.py | 6 ++
tools/quick_dump
On Mon, 2014-05-19 at 08:03 -0700, Jesse Barnes wrote:
On Mon, 19 May 2014 16:48:31 +0300
Imre Deak imre.d...@intel.com wrote:
These opcodes are not specific for an endpoint, but are the same for all
endpoints. So rename them accordingly, using the name the VLV2 sideband
HAS uses. Also
On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
On Mon, 19 May 2014 11:41:18 +0300
Imre Deak imre.d...@intel.com wrote:
So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers
On Tue, 2014-05-20 at 05:52 +0300, Lin, Mengdong wrote:
This RFC is based on previous discussion to set up a generic
communication channel between display and audio driver and
an internal design of Intel MCG/VPG HDMI audio driver. It's still an
initial draft and your advice would be
On Tue, 2014-05-20 at 20:05 +0530, Vinod Koul wrote:
On Tue, May 20, 2014 at 05:29:07PM +0300, Imre Deak wrote:
On Tue, 2014-05-20 at 05:52 +0300, Lin, Mengdong wrote:
This RFC is based on previous discussion to set up a generic
communication channel between display and audio driver
unregister_shrinker()
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index bf81396..f14c47a 100644
--- a/drivers/gpu/drm/i915
On Wed, 2014-05-21 at 18:05 +0200, Daniel Vetter wrote:
On Wed, May 21, 2014 at 5:56 PM, Babu, Ramesh ramesh.b...@intel.com wrote:
On Tue, May 20, 2014 at 05:29:07PM +0300, Imre Deak wrote:
On Tue, 2014-05-20 at 05:52 +0300, Lin, Mengdong wrote:
This RFC is based on previous discussion
On Wed, 2014-05-21 at 21:43 +0300, Ville Syrjälä wrote:
On Wed, May 21, 2014 at 11:11:15AM -0700, Jesse Barnes wrote:
And to answer more specifically...
On Wed, 21 May 2014 20:54:03 +0300
Ville Syrjälä ville.syrj...@linux.intel.com wrote:
+
seem to match reality based on
the above and it's also asymmetric with the enabling sequence, where we
first enable the port and then the pipe.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
On Tue, 2014-05-27 at 19:45 +0530, Kumar, Shobhit wrote:
On 5/27/2014 6:45 PM, Imre Deak wrote:
If we disable first the port (by disabling DPI) and only then the
display pipe the pipe-off flag will never be set, possibly leading to a
hanged pipe state at the next modeset-enable.
Note
On Tue, 2014-05-27 at 21:04 +0530, Kumar, Shobhit wrote:
On 5/27/2014 8:42 PM, Imre Deak wrote:
On Tue, 2014-05-27 at 19:45 +0530, Kumar, Shobhit wrote:
On 5/27/2014 6:45 PM, Imre Deak wrote:
If we disable first the port (by disabling DPI) and only then the
display pipe the pipe-off flag
seem to match reality based on
the above and it's also asymmetric with the enabling sequence, where we
first enable the port and then the pipe.
v2:
- send the panel shutdown command before stopping the pipe, since this
is the recommended sequence (Shobhit)
Signed-off-by: Imre Deak imre.d
On Tue, 2014-05-27 at 22:58 +0200, Daniel Vetter wrote:
Looks like work for Imre or someone else from the runtime pm gang.
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c | 4
1 file changed, 4 insertions
On Wed, 2014-05-28 at 09:50 -0700, Jesse Barnes wrote:
This saves many ms per call on my BYT by eliminating Punit communication
from the hw readout paths.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 3
state
is entered, disabling that also gets rid of the problem. As an
alternative I also tried to increase the plane SR watermark close to its
maximum but that didn't solve the issue.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915
...@virtuousgeek.org
Looks ok to me:
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e2bfdda..66c6ffb 100644
--- a/drivers/gpu/drm/i915
-by: Imre Deak imre.d...@intel.com
console_lock();
intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index c597b0d..bf90e7d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm
() and
correspondingly the above call to hsw_enable_pc8() to suspend_late()
before we call pci_disable_device().
With that change this is:
Reviewed-by: Imre Deak imre.d...@intel.com
+
if (drm_core_check_feature(dev, DRIVER_MODESET)
restore_gtt_mappings) {
mutex_lock
);
+
This could be moved after intel_opregion_init() just for clarity, but
I'm also fine keeping it here.
This patch depends on Rafael's change in his PM tree to export
acpi_target_system_state(), other than that this is:
Reviewed-by: Imre Deak imre.d...@intel.com
intel_runtime_pm_put(dev_priv
References: https://bugs.freedesktop.org/show_bug.cgi?id=79038
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
This matches the runtime suspend paths and allows the system to enter
the lowest power mode at freeze time.
On Mon, 2014-06-02 at 14:35 +0100, Chris Wilson wrote:
On Fri, Dec 20, 2013 at 03:09:41PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We're iterating over the CPU transcoders, so check for the correct
power domain.
This fixes many unclaimed register error
On Mon, 2014-06-02 at 17:32 +0200, Daniel Vetter wrote:
On Mon, Jun 02, 2014 at 02:37:35PM +0300, Imre Deak wrote:
On Mon, 2014-06-02 at 10:45 +0200, Daniel Vetter wrote:
On Thu, May 29, 2014 at 02:11:37PM -0700, Jesse Barnes wrote:
From: Kristen Carlson Accardi kris...@linux.intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
---
tools/quick_dump/quick_dump.py | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 523f675..2eb7724 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools
to freeze_late (Imre/Jesse)
v3: drop spurious hunk from _freeze now that we have freeze_late (Jesse)
v4: move back to suspend_late (Imre was right)
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Imre Deak imre.d
regression where boot time increased by
~4 seconds due to frequent power well state queries on VLV during eDP
EDID read.
Reported-by: Jesse Barnes jesse.bar...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c
On Thu, 2014-06-05 at 10:35 -0700, Jesse Barnes wrote:
On Thu, 5 Jun 2014 20:31:47 +0300
Imre Deak imre.d...@intel.com wrote:
Jesse noticed that the punit communication needed to query the VLV power
well status can cause substantial delays. Since we can query the state
frequently
where we zeroed the counters were driver load and unload time,
where it was redundant anyway.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78059
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3
If the timer putting the last forcewake refcount was pending and we
canceled it, we'll leak the corresponding forcewake and RPM references.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions
If the timer putting the last forcewake refcount was pending and we
canceled it, we'll leak the corresponding forcewake and RPM references.
v2:
- do the ptr casting at the caller instead of adding a separate helper
for this (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu
with the vgacon code.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 4
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 -
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
On Fri, 2014-06-06 at 19:19 +0200, Daniel Vetter wrote:
On Thu, Jun 05, 2014 at 08:31:47PM +0300, Imre Deak wrote:
Jesse noticed that the punit communication needed to query the VLV power
well status can cause substantial delays. Since we can query the state
frequently, for example during
On Fri, 2014-06-06 at 19:46 +0200, Daniel Vetter wrote:
On Fri, Jun 06, 2014 at 12:08:43PM +0100, Chris Wilson wrote:
On Fri, Jun 06, 2014 at 02:04:37PM +0300, Imre Deak wrote:
If the timer putting the last forcewake refcount was pending and we
canceled it, we'll leak the corresponding
On Fri, 2014-06-06 at 22:15 +0200, Daniel Vetter wrote:
On Fri, Jun 06, 2014 at 09:38:26PM +0300, Imre Deak wrote:
On Fri, 2014-06-06 at 19:46 +0200, Daniel Vetter wrote:
On Fri, Jun 06, 2014 at 12:08:43PM +0100, Chris Wilson wrote:
On Fri, Jun 06, 2014 at 02:04:37PM +0300, Imre Deak
On Fri, 2014-06-06 at 22:35 +0200, Daniel Vetter wrote:
On Fri, Jun 06, 2014 at 11:19:28PM +0300, Imre Deak wrote:
On Fri, 2014-06-06 at 22:15 +0200, Daniel Vetter wrote:
On Fri, Jun 06, 2014 at 09:38:26PM +0300, Imre Deak wrote:
On Fri, 2014-06-06 at 19:46 +0200, Daniel Vetter wrote
Hi Sagar,
On Tue, 2014-06-10 at 00:27 +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
Display power island is on during boot, we have one count for it
once this power gates, we do a put making sure runtime_suspend is
called
Cc: Daniel Vetter
On Tue, 2014-06-10 at 00:27 +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
To do a platform wide S0i3 transition, Gfx is required to go
to D3_hot state. pci_save_state and pci_restore_state needed to avoid ring
hangs across D3_hot transitions.
Cc:
On Wed, 2014-06-04 at 13:45 -0700, Jesse Barnes wrote:
This allows the system to enter the lowest power mode during system freeze.
v2: delete force wake timer at suspend (Imre)
v3: add GT work suspend function (Imre)
v4: use uncore forcewake reset (Daniel)
Signed-off-by: Kristen Carlson
On Tue, 2014-06-10 at 15:57 +0200, Daniel Vetter wrote:
On Tue, Jun 10, 2014 at 04:42:50PM +0300, Imre Deak wrote:
On Wed, 2014-06-04 at 13:45 -0700, Jesse Barnes wrote:
This allows the system to enter the lowest power mode during system
freeze.
v2: delete force wake timer
On Tue, 2014-06-10 at 23:05 +0530, Sagar Arun Kamble wrote:
On Tue, 2014-06-10 at 15:43 +0300, Imre Deak wrote:
On Tue, 2014-06-10 at 00:27 +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
To do a platform wide S0i3 transition, Gfx is required to go
On Tue, 2014-06-10 at 12:35 -0700, Steven Noonan wrote:
On Wed, Apr 16, 2014 at 3:03 PM, Steven Noonan ste...@uplinklabs.net wrote:
On Wed, Apr 16, 2014 at 2:46 PM, Jani Nikula
jani.nik...@linux.intel.com wrote:
On Tue, 15 Apr 2014, Imre Deak imre.d...@intel.com wrote:
On Tue, 2014-04-15
On Wed, 2014-06-11 at 15:24 -0700, Jesse Barnes wrote:
On Wed, 11 Jun 2014 15:21:16 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 10 Jun 2014 17:26:45 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jun 10, 2014 at 05:41:49PM +0300, Imre Deak wrote:
On Tue, 2014
Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 21
, in my latest tests disabling it
alone didn't make a difference
- add vblank between disabling plane and pipe (Ville)
- apply the same workaround for all gmch platforms (Ville)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 15 +--
1 file
On Mon, 2014-06-16 at 12:30 +0100, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
Otherwise, we might receive a new interrupt before we have time to
ack the first one, eventually missing it.
Notice that, before clearing a port-sourced interrupt in the IIR, the
);
+#define PTE_READ_ONLY (12)
As this uses the same namespace as GLOBAL_BIND, I would keep their
definitions together. Also I couldn't find any other flag besides
GLOBAL_BIND, in which case this could be (1 1).
With the above fixed the patch looks good to me:
Reviewed-by: Imre Deak imre.d
as per Chris
Wilson's request.
v3: Improve the source comments.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
I couldn't spot any problems, so on all 4 patches:
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 20 +++-
1 file changed, 15
On Wed, 2014-06-18 at 09:52 -0700, Jesse Barnes wrote:
We don't need to uninstall the full handler, simply disabling interrupts
ought to be enough.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Imre Deak imre.d...@intel.com
For follow-up:
I agree with Daniel that we
Barnes jbar...@virtuousgeek.org
Reviewed-by: Imre Deak imre.d...@intel.com
Btw, we also have the same redundancy in intel_dp_detect().
--Imre
---
drivers/gpu/drm/i915/i915_drv.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915
...@virtuousgeek.org
Date: Thu Jun 12 08:35:47 2014 -0700
drm/i915: send proper opregion notifications on suspend/resume
Reported-by: Randy Dunlap rdun...@infradead.org
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 7 ---
1 file changed, 4 insertions(+), 3
On Tue, 2014-06-24 at 16:54 +0300, Jani Nikula wrote:
On Mon, 23 Jun 2014, Imre Deak imre.d...@intel.com wrote:
To achieve further power savings during system freeze (aka connected
standby, or s0ix) we have to send a PCI_D1 opregion notification. As
the information about the state we're
On Tue, 2014-06-24 at 17:53 +0300, Jani Nikula wrote:
On Tue, 24 Jun 2014, Imre Deak imre.d...@intel.com wrote:
On Tue, 2014-06-24 at 16:54 +0300, Jani Nikula wrote:
On Mon, 23 Jun 2014, Imre Deak imre.d...@intel.com wrote:
To achieve further power savings during system freeze (aka
From: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
From: Daniel Vetter daniel.vet...@ffwll.ch
This way only the dynamic WRPLL selection for hdmi ddi mode is
done in intel_ddi_pll_select.
v2: Don't clobber the precomputed values when selecting clocks fro
hdmi encoders.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
refactoring]
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_crt.c | 13 +
drivers/gpu/drm/i915/intel_ddi.c | 19 +--
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915
From: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
From: Daniel Vetter daniel.vet...@ffwll.ch
This time around another cute hack to pre-fill the pll-hw_state with
the right values. And also remove a bunch of checks which will be
replaced by lots more checks in the common framework.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by:
This is needed by an upcoming patch that moves the PCH/CRT PLL disabling
into the post_disable hook, after which we want to keep the modeset
sequence at its current state. At this point this won't have an effect
since the PCH/CRT post_disable hook is atm a NOP.
Signed-off-by: Imre Deak imre.d
From: Daniel Vetter daniel.vet...@ffwll.ch
Just boring sed job for preparation.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak imre.d...@intel.com
From: Daniel Vetter daniel.vet...@ffwll.ch
Just filing in names and ids, but not yet officially registering them
so that the hw state cross checker doesn't completely freak out about
them. Still since we do already read out and cross check
config-shared_dpll the basics are now there to flesh out
type is now finally complete.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_crt.c | 15 +++
drivers/gpu/drm/i915/intel_ddi.c | 7 ---
2
From: Daniel Vetter daniel.vet...@ffwll.ch
SPLL would be a reference clock we could potentially share,
especially if we want to use the SSC mode. But currently we
don't, so let's rip out this complexity for a simpler conversion
to the new display pll framework.
Signed-off-by: Daniel Vetter
From: Daniel Vetter daniel.vet...@ffwll.ch
Currently still with a redudant WARN_ON in there, the common shared
dpll code will take care of this in the future.
Also we need to flip the switch for the transitional hack now to make
sure that we disable the right pll.
Signed-off-by: Daniel Vetter
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 40 +-
drivers/gpu/drm
101 - 200 of 5412 matches
Mail list logo
