On 8/16/2023 12:10 PM, Kalvala, Haridhar wrote:
On 8/11/2023 5:16 AM, Matt Roper wrote:
Rather than picking random tiling formats from a pool that contains both
TileY and Tile4 and then trying to replace one with the other depending
on the platform, it's simpler to just use a single enum
On 8/16/2023 8:48 PM, Matt Roper wrote:
On Wed, Aug 16, 2023 at 12:16:25PM +0530, Kalvala, Haridhar wrote:
On 8/11/2023 5:16 AM, Matt Roper wrote:
We don't really need a feature flag for has_4tile since there's a
well-defined cutover point (DG2) at which all new platforms started
using Tile4
On 8/11/2023 5:16 AM, Matt Roper wrote:
Rather than picking random tiling formats from a pool that contains both
TileY and Tile4 and then trying to replace one with the other depending
on the platform, it's simpler to just use a single enum value that
represents whatever the
On 8/11/2023 5:16 AM, Matt Roper wrote:
We don't really need a feature flag for has_4tile since there's a
well-defined cutover point (DG2) at which all new platforms started
using Tile4 as their Y-major tiling layout. The GT side of the code
already handles Tile4 vs legacy TileY with checks
On 4/26/2023 9:41 PM, Sripada, Radhakrishna wrote:
-Original Message-
From: Kalvala, Haridhar
Sent: Wednesday, April 26, 2023 5:36 AM
To: Sripada, Radhakrishna ; intel-
g...@lists.freedesktop.org
Cc: Vivi, Rodrigo
Subject: Re: [Intel-gfx] [PATCH v1.1] drm/i915/mtl: Implement
On 4/26/2023 12:00 AM, Radhakrishna Sripada wrote:
Enable strict RAR to prevent spurious GPU hangs.
v1.1: Rebase
Cc: Rodrigo Vivi
Cc: Umesh Nerlige Ramappa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
On 4/21/2023 3:42 AM, Radhakrishna Sripada wrote:
From: Stanislav Lisovskiy
We try to verify pll registers in sw state for slave crtc with the hw state.
However in case of bigjoiner we don't calculate those at all, so this
verification
will then always fail.
So we should either skip the
On 4/21/2023 3:42 AM, Radhakrishna Sripada wrote:
CPU transcoder mask is used to iterate over the available
CPU transcoders in the macro for_each_cpu_transcoder().
The macro is broken on MTL and got highlighted when audio
state was being tracked for each transcoder added in [1].
Add the
On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
On 29/03/2023 01:49, Matt Atwood wrote:
On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
By default the indirect state sampler data (border colors) are stored
in the same heap
On 3/31/2023 12:35 PM, Kalvala, Haridhar wrote:
On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
On 29/03/2023 01:49, Matt Atwood wrote:
On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
By default the indirect state sampler
On 3/31/2023 2:12 AM, Lionel Landwerlin wrote:
By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border
On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border
On 6/17/2023 4:20 AM, Matt Roper wrote:
This workaround was already implemented for DG2, PVC, and some steppings
of MTL, but the workaround database has now been updated to extend this
workaround to TGL, RKL, DG1, and ADL.
v2:
- Skip readback verification for these extra gen12lp platforms.
On 5/13/2023 7:44 AM, Radhakrishna Sripada wrote:
The dg2 workaround which is used for performance tuning
is needed for Meteorlake A-step.
v2: Limit the WA for A-step
Bspec: 68331
Cc: Haridhar Kalvala
Cc: Matt Roper
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
---
On 5/13/2023 7:44 AM, Radhakrishna Sripada wrote:
MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.
v2: Add DRAW_WATERMARK tuning parameter.
Bspec: 68331
Cc: Haridhar Kalvala
Cc: Matt Roper
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
On 1/19/2024 5:03 AM, Matt Roper wrote:
On Mon, Jan 08, 2024 at 03:37:29PM -, Patchwork wrote:
== Series Details ==
Series: Extend ARL support
URL : https://patchwork.freedesktop.org/series/128322/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14092_full ->
On 12/18/2023 9:24 PM, Matt Roper wrote:
Oh, and one more thing I forgot to mention before hitting send...the
title for this patch doesn't make sense. Xe_LPG is the graphics IP used
by MTL; that's completely unrelated to the display IP (which is
Xe_LPD+).
Since we're assigning the fake PCH
On 12/19/2023 10:39 PM, Matt Roper wrote:
On Tue, Dec 19, 2023 at 02:58:00PM +0530, Haridhar Kalvala wrote:
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC
On 12/11/2023 9:26 PM, Matt Roper wrote:
On Mon, Dec 11, 2023 at 05:08:48PM +0530, Kalvala, Haridhar wrote:
On 12/6/2023 1:54 AM, Matt Roper wrote:
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off
On 12/21/2023 3:41 AM, Matt Roper wrote:
On Wed, Dec 20, 2023 at 12:22:33AM +0530, Haridhar Kalvala wrote:
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC
On 12/6/2023 1:54 AM, Matt Roper wrote:
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: Haridhar Kalvala
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
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