Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11
.
v2: Rebase on new modular FIA code (Lucas)
v3: Also add new port in port_identifier(), even though it can't
possibly be used there (requested by José)
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
h
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-21-lucas.demar...@intel.com
---
drivers/gpu/drm/i915
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link
: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-3-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-6-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid
function for TGL, but rather reuse the ICL one
(suggested by Rodrigo)
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190709170044.29489-1-lucas.demar...@intel.com
---
drivers/gpu/drm/i915
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-10-lucas.demar...@intel.com
---
.../drm/i915/display
en)
v3 (Lucas):
- Rename power domain so it's clear it can also be used for transcoder
A in TGL (requested by José and Manasi)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Acked-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_p
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-8-lucas.demar...@intel.com
-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-23-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions
-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-12-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Revi
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-5-lucas.demar...@intel.com
---
drivers/gpu/drm/i915
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 3
ita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/display/intel_display.h | 8
include/drm/i915_component.h | 2 +-
include/
: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 29
drivers/gpu/drm/i915
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu
en)
v3 (Lucas):
- Rename power domain so it's clear it can also be used for transcoder
A in TGL (requested by José and Manasi)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Acked-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_p
A
drm/i915/tgl: Update DPLL clock reference register
Lucas De Marchi (6):
drm/i915: Add 4th pipe and transcoder
drm/i915/tgl: Add TGL PCI IDs
drm/i915/tgl: Add additional PHYs for Tiger Lake
drm/i915/tgl: apply Display WA #1178 to fix type C dongles
drm/i915/tgl: port to ddc pin mapping
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
function for TGL, but rather reuse the ICL one
(suggested by Rodrigo)
v3: rebase after the introduction of enum phy and use it for the
conversions
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 36 ++-
1
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 28 +--
.../drm/i915/display
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8
Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
conversion functions from port to phy.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
drivers/gpu/drm/i915/display/intel_display.h | 3 +++
2 files changed, 7 insertions(+), 1 deletion
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 10 insertions(+), 1
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_power.c| 474 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu
-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Revi
-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the
SOC,
then Display Driver will access the additional instances of
FIA based on pre
): Add comment about the mapping between FIA and TC port
(suggested by Stuart)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Acked-by: Ville Syrjälä
Reviewed-by: Stuart Summers
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +++
drivers/gpu/drm/i915
Tiger Lake has modular FIA bit indicating if we are using it, so add to
the device info.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e83c94cf2744
https://patchwork.freedesktop.org/series/63175/
Changes:
- Add comment explaining mapping port <-> FIA
- Add commit to apply modular FIA on TGL
Anusha Srivatsa (1):
drm/i915: Add modular FIA
Lucas De Marchi (1):
drm/i915/tgl: add modular FIA to device info
drivers/gpu/drm/i915/d
t;= 12. Or we can
leave as is and change it to be a gen check when next platforms come.
Lucas De Marchi
Lucas De Marchi
>
>Thanks,
>Stuart
>
>>func(has_overlay); \
>>func(has_psr); \
>>func(overlay_needs_physical); \
>> diff --git a/drivers/gpu
On Fri, Jul 12, 2019 at 10:48:48AM -0700, Summers, Stuart wrote:
On Thu, 2019-07-11 at 22:57 -0700, Lucas De Marchi wrote:
Tiger Lake has modular FIA bit indicating if we are using it, so add
to
the device info.
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Both patches
From: Michel Thierry
Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
register (and format).
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
The final save operation into pll_state of the calculations done will
be different for DKL PHY. Prepare for that by reindenting code so it's
easier to check for correctness. This one has no change in behavior.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
tate() in intel_display.c that was
missing
- Define macros using the _SHIFT macros so we don't lose other users
Cc: Ville Syrjälä
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++-
drivers/gpu/drm/i915/dis
phy introduction
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
From: Vandita Kulkarni
Reuse the existing calculate icl_calc_mg_pll_state() function.
Since the pll variables are calculated differently for DKL phy, add
support for the same.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
From: Michel Thierry
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
For Tiger Lake the DE Port Interrupt Definition bits changed, so use the
new bit definitions.
Cc: Jose Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 16 +++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions
From: José Roberto de Souza
TGL has 3 combophys and 6 TC/TBT ports, so it has 2 more TC/TBT ports
than ICL and the PORT_C on TGL is a combophy.
So here adding a new hpd north table and function to detect long
pulse for TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Cc: Matt Roper
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
().
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers change -
prepare for that using an empty dkl_pll_write() to be implemented later.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 98
to work.
Although we are changing the gen11 table, those changes are supposed to
be backward compatible since we are only touching previously undefined
entries.
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tomasz Lis
Signed-off-by: Lucas De Marchi
---
drivers
From: Vandita Kulkarni
Add a new function to write to dkl phy pll registers. As per the
spec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++-
1 file changed, 64
connect
Lucas De Marchi (5):
drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
drm/i915/tgl: Add hpd interrupt handling
drm/i915/tgl: handle DP aux interrupts
drm/i915/tgl: re-indent code to prepare for DKL changes
drm/i915/tgl: start adding the DKL PLLs to use on TC ports
From: Tvrtko Ursulin
Hide the details of MOCS setup from i915_gem by moving both current calls
into one in intel_mocs_init.
Cc: Stuart Summers
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++
drivers/gpu/drm/i915/gt
Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_pm.c
From: Vandita Kulkarni
These are the registers needed to program Dekel PHY. Some register
definitions reuse the MG PHY definitions. Add a comment on those so we
don't need to duplicate the functions for programming them.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 475ab3d4d91d..2b839acfa0f6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm
Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
is refactored to be shared with TGP.
While we increase the number of pins, add a BUILD_BUG_ON() to avoid
going over the number of bits allowed.
Cc: Jose Souza
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers
part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).
Cc: Daniele Ceraolo Spurio
Cc: Tomasz Lis
Signed-off-by: Michel Thierry
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
---
drivers/gpu
From: José Roberto de Souza
Tiger Lask has a new register offset for DC5 and DC6 residency counters.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files
From: Anusha Srivatsa
Add Support to load DMC v2.02 on TGL.
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index
From: Michel Thierry
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm
From: Michel Thierry
There are no changes with respect to GEN11, which Paulo wrote.
This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.
Cc: Paulo Zanoni
Cc: Lionel Landwerlin
Signed-off-by: Michel Thierry
Signed-off-by: Lucas
-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so just check for IS_TIGERLAKE() inside it.
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915
From: Michel Thierry
Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
register (and format).
Cc: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86
-by: Imre Deak
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 480 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 18 +
4 files changed
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 +++
2
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
From: Mahesh Kumar
Create a helper function to get ddc pin according to port number.
Cc: Anusha Srivatsa
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 29
drivers/gpu/drm/i915
n)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file changed, 9 insertions(+), 3
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19 insertions
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++-
drivers/gpu/drm/i915/i915_r
-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9ccf58ff4dba
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
dri
.
v2: Rebase on new modular FIA code (Lucas)
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
include/drm/i915_component.h
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
drivers/gpu/drm
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm
clock reference register
Lucas De Marchi (5):
drm/i915: Add 4th pipe and transcoder
drm/i915/tgl: Add TGL PCI IDs
drm/i915/tgl: apply Display WA #1178 to fix type C dongles
drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
drm/i915/tgl: Add DPLL registers
Mahesh Kumar (8):
drm
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 30 ---
.../drm/i915/display/intel_display_power.h
Separate local includes with a blank line and sort the groups
alphabetically.
v2: don't make intel_tc.h be the first include
v3: don't make local includes be included first
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display
On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo
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