[Intel-gfx] [PATCH] drm/i915: Re-enable per-engine reset for Broxton

("drm/i915: Stop touching forcewake following a gen6+ engine reset"), lets try to enable per-engine resets in Broxton one more time. This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for Broxton"). Cc: Chris Wilson <ch...@chris-wilson.co.uk> Sig

Re: [Intel-gfx] [PATCH v2] drm/i915: Clear lost context-switch interrupts across reset

ed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: "Dong, Chuanxiao" <chuanxiao.d...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Link: https://patc

Re: [Intel-gfx] [PATCH] drm/i915: Stop touching forcewake following a gen6+ engine reset

o read protected registers elsewhere and those results may be clobbered by the concurrent dropping of forcewake. Reported-by: Michel Thierry <michel.thie...@intel.com> Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery") Signed-off-by: Chris Wilson <

Re: [Intel-gfx] [PATCH 3/3] drm/i915: More surgically unbreak the modeset vs reset deadlock

and broke the unbreak/wakeup logic. v4: Also handle deadlocks in pin_to_display. v5: Review from Michel: - Fixup the BUILD_BUG_ON - Don't forget about the overlay Reviewed-by: Michel Thierry <michel.thie...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Clear lost context-switch interrupts across reset

.d...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a

Re: [Intel-gfx] [PATCH v2 01/16] drm/i915/guc: Add support for data reporting in GuC responses

prohibited space after '~' (Michel) update commit message (Daniele) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com&g

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Push i915_sw_fence_wait into the nonblocking atomic commit

On 8/7/2017 8:33 AM, Daniel Vetter wrote: On Thu, Aug 03, 2017 at 12:44:40PM -0700, Michel Thierry wrote: On 7/20/2017 10:57 AM, Daniel Vetter wrote: Blocking in a worker is ok, that's what the unbound_wq is for. And it unifies the paths between the blocking and nonblocking commit, giving me

Re: [Intel-gfx] [PATCH 07/15] drm/i915/guc: Create a GuC receive function

On 8/4/2017 9:27 AM, Michal Wajdeczko wrote: From: Oscar Mateo This function, symmetrical to the send(), will handle Guc2Host message interrupts (which at the moment still only covers requests to flush the GuC logs). Cc: Michal Wajdeczko Cc:

Re: [Intel-gfx] [PATCH 04/15] drm/i915/guc: Implement response handling in send_mmio()

i] = I915_READ(guc_send_reg(guc, i)); + } new line here? /* Use data encoded in status dword as return value */ ret = INTEL_GUC_RECV_TO_DATA(status); } Reviewed-by: Michel Thierry <michel.thie...@intel.com>

Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc: Add send_and_receive() helper function

hide underlying details. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/gpu/drm/i915/intel_uc.h | 7

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Prepare send() function to accept bigger response

;oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/gpu/drm/i915/intel_guc_ct.c | 7 --- drivers/gpu/drm/i915/intel_uc.c | 6 -- drivers/gpu/drm/i915/intel_uc.h | 8 --

Re: [Intel-gfx] [PATCH 01/15] drm/i915/guc: Add support for data reporting in GuC responses

gt; Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/gpu/drm/i915/intel_guc_ct.c | 14 +++--- drivers/gpu/drm/i915/intel_guc_fwif.h | 6 ++ drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Push i915_sw_fence_wait into the nonblocking atomic commit

atomic_commit_tail(state); - } + return 0; } Reviewed-by: Michel Thierry <michel.thie...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/7] drm/i915: More surgically unbreak the modeset vs reset deadlock

Hi, First sorry about the delay... On 7/20/2017 10:57 AM, Daniel Vetter wrote: There's no reason to entirely wedge the gpu, for the minimal deadlock bugfix we only need to unbreak/decouple the atomic commit from the gpu reset. The simplest way to fix that is by replacing the unconditional

Re: [Intel-gfx] [PATCH] drm/i915: Avoid the gpu reset vs. modeset deadlock

me since it only affects very old platforms, and is a temporary measure. Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Also, Reviewed-by: Michel Thierry <michel.thie...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/guc: Prevent ggtt->invalidate assert during GuC reload

On 6/30/2017 10:41 AM, Michel Thierry wrote: The driver reloads the GuC firmware after full gpu reset or suspend/resume, but it never disables the GuC beforehand. This leads us to hit the assert inside i915_ggtt_enable_guc added by commit 04f7b24eccdf ("drm/i915/guc: Assert that we s

Re: [Intel-gfx] [PATCH 18/20] drm/i915/selftests: Retarget igt_render_engine_reset_fallback()

On 7/21/2017 5:32 AM, Chris Wilson wrote: The purpose of the test was to check per-engine resets would fallback to the global reset when required, but first we actually need a test for a basic i915_handle_error()! Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <mi

Re: [Intel-gfx] [PATCH 19/20] drm/i915: Squelch reset messages during selftests

(dev_priv); + i915_reset(dev_priv, 0); I guess adding a wrapper to make flags=0 the default it's an overkill, plus I see the benefit of not flooding dmesg. Reviewed-by: Michel Thierry <michel.thie...@intel.com> mutex_unlock(_priv-&g

Re: [Intel-gfx] [PATCH 15/20] drm/i915: Don't touch fence->error when resetting an innocent request

the active request at the time of the reset. Reported-by: Daniel Vetter <daniel.vet...@ffwll.ch> Fixes: c64992e035d7 ("drm/i915: Look for active requests earlier in the reset path") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie

Re: [Intel-gfx] [PATCH 17/20] drm/i915/selftest: Refactor reset locking

oppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <michel.thie...@intel.com> I don't know how you trigger that, but Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 58 ++-- 1 file chang

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Assert that machine is wedged for nop_submit_request

On 7/20/2017 5:51 AM, Chris Wilson wrote: Quoting Michel Thierry (2017-07-18 01:15:00) On 17/07/17 02:11, Chris Wilson wrote: We should only ever do nop_submit_request when the machine is wedged, so assert it is so. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/g

Re: [Intel-gfx] [PATCH 13/15] drm/i915: Emit a user level message when resetting the GPU (or engine)

the context was banned, and also reduces awareness overall of when a GPU (engine) reset occurs with its possible side-effects. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> ---

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Assert that machine is wedged for nop_submit_request

On 17/07/17 02:11, Chris Wilson wrote: We should only ever do nop_submit_request when the machine is wedged, so assert it is so. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git

Re: [Intel-gfx] [PATCH 14/15] drm/i915: Disable per-engine reset for Broxton

), ctx=0, rq=3 Note that this bug may be affect all machines and not just Broxton, Broxton is just the first machine on which I have confirmed this bug. Hopefully this is just broxton being broxton... I think I already sent this, but anyway... Acked-by: Michel Thierry <michel.thie...@inte

Re: [Intel-gfx] [PATCH 05/15] drm/i915: Check execlist/ring status during hangcheck

hc->seqno) return ENGINE_ACTIVE_SEQNO; - if (i915_seqno_passed(hc->seqno, intel_engine_last_submit(engine))) + if (intel_engine_is_idle(engine)) return ENGINE_IDLE; return engine_stuck(engine, hc->acthd); Reviewed-by: Michel Thierry <mic

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Clear engine irq posted following a reset

*request) { + engine->irq_posted = 0; + if (request && i915_gem_reset_request(request)) { DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", engine->name, request->global_seqno); Reviewed-by: Mich

Re: [Intel-gfx] [PATCH 03/15] drm/i915: Serialize per-engine resets against new requests

Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 16 +++- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/execlists: Read the context-status HEAD from the HWSP

resubmit latency, although it appears lost in the noise! v2: Cannonlake moved the CSB write index v3: Include the sw/hwsp state in debugfs/i915_engine_info v4: Also revert to using CSB mmio for GVT-g Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@inte

Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/execlists: Read the context-status buffer from the HWSP

, it currently depends on intercepting CSB mmio Suggested-by: Ben Widawsky <benjamin.widaw...@intel.com> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/lrc: allocate separate page for HWSP

avoid the conflict, instead of re-using the PPHWSP of the kernel ctx we can allocate a separate page for the HWSP like what happens for pre-execlists platform. v2: Add a use-case for the register arena of the HWSP. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Mi

Re: [Intel-gfx] [PATCH 2/3] drm/i915/execlists: Read the context-status buffer from the HWSP

co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

Re: [Intel-gfx] [PATCH 3/3] drm/i915/execlists: Read the context-status HEAD from the HWSP

. Still a step in the right direction towards reducing our resubmit latency, although it appears lost in the noise! Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Ku

Re: [Intel-gfx] [PATCH 1/3] drm/i915/lrc: allocate separate page for HWSP

small changes I noticed were in intel_engine_init_common and logical_ring_init). Apart from those 2 things, it looks good to me. Reviewed-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michel Thierry <

Re: [Intel-gfx] [PATCH 1/2] drm/i915/lrc: Clarify the format of the context image

On 7/12/2017 12:45 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-07-12 20:30:31) Not only the context image consist of two parts (the PPHWSP, and the logical context state), but we also allocate a header at the start of for sharing data with GuC. Thus every lrc looks like

[Intel-gfx] [PATCH 1/2] drm/i915/lrc: Clarify the format of the context image

.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: inte

[Intel-gfx] [PATCH 2/2] drm/i915/guc: Don't make assumptions while getting the lrca offset

Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Osca

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't make assumptions while getting the lrca offset

On 7/11/2017 5:54 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-07-12 01:14:46) On 7/11/2017 5:07 PM, Chris Wilson wrote: Quoting Chris Wilson (2017-07-12 01:00:02) Also feel free to try and fixup the other confusion in intel_lrc.c. Perhaps something like: diff --git a/drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't make assumptions while getting the lrca offset

On 7/11/2017 5:07 PM, Chris Wilson wrote: Quoting Chris Wilson (2017-07-12 01:00:02) Also feel free to try and fixup the other confusion in intel_lrc.c. Perhaps something like: diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index b0738d2..f498aa6 100644 ---

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't make assumptions while getting the lrca offset

On 7/11/2017 3:37 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-07-11 22:29:39) Using the HWSP ggtt_offset to get the lrca offset is only correct if the HWSP happens to be before it (when we reuse the PPHWSP of the kernel context as the engine HWSP). Instead of making this assumption

[Intel-gfx] [PATCH] drm/i915/guc: Don't make assumptions while getting the lrca offset

of the GuC interaction, it was also noticed that the firmware expects the size of only the engine context (context minus the execlist part, i.e. don't include the first 80 dwords), so pass the right size. Reported-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915: Emit a user level message when resetting the GPU (or engine)

reset but not the engine resets. This leaves a bit of mystery as to why the context was banned, and also reduces awareness overall of when a GPU (engine) reset occurs with its possible side-effects. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com>

Re: [Intel-gfx] [RFC] drm/i915/lrc: allocate separate page for HWSP

On 07/07/17 14:15, Daniele Ceraolo Spurio wrote: After a bit of investigation I've found that the issue is not actually with the positioning of the HWSP but with the fact that we use status_page.ggtt_offset to point to the lrca offset of the default context in guc_ads_create instead of using

Re: [Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_reset_stats: Enforce full chip reset mode before run

On 06/07/17 15:50, Antonio Argenziano wrote: + +igt_fixture { +int fd; + +fd = drm_open_driver(DRIVER_INTEL); +igt_assert(igt_sysfs_set_parameter + (fd, "reset", "%d", INT_MAX /* any reset method */)); I would still suggest that we restore the reset

Re: [Intel-gfx] [RFC] drm/i915/lrc: allocate separate page for HWSP

pens for pre-execlists platform. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> > --- drivers/gpu/drm/i915/intel_engine_cs.c | 123 +++ drivers/gpu/drm/i915/intel_lrc.c| 42 +--

Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_reset_stats: Enforce full chip reset mode before run

On 06/07/17 04:12, Arkadiusz Hiler wrote: On Tue, Jun 20, 2017 at 11:25:02AM -0700, Michel Thierry wrote: Platforms with per-engine reset enabled (i915.reset=2) are unlikely to perform a full chip reset, keeping the reset_count unmodified. In order to keep the expectations of this test, enforce

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise independence of per-engine resets

-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 165

Re: [Intel-gfx] [PATCH] drm/i915: Disable per-engine reset for Broxton

On Thu, Jul 6, 2017 at 12:11 AM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: Quoting Michel Thierry (2017-07-06 02:24:26) On 04/07/17 09:09, Chris Wilson wrote: > Triggering a GPU reset for one engine affects another, notably > corrupting the context status buffer (CSB) effect

Re: [Intel-gfx] [PATCH] drm/i915: Disable per-engine reset for Broxton

he first machine on which I have confirmed this bug. Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <michel.thie.

[Intel-gfx] [PATCH] drm/i915/guc: Prevent ggtt->invalidate assert during GuC reload

need to keep this for the full gpu reset case. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Mic

Re: [Intel-gfx] [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle

On 6/29/2017 6:07 AM, Chris Wilson wrote: Quoting Ville Syrjälä (2017-06-29 14:05:25) On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote: There's no need to keep reading random registers in i915_swizzle_info if the platform is not doing GPU side swizzling. After HSW, swizzling

[Intel-gfx] [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle

emory controller do all the swizzling"). Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugf

[Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_reset_stats: Enforce full chip reset mode before run

the number of per-engine resets and use reset_count + reset_engine_count when checking for the updated reset count. v2: Rebase, don't use gem_gpu_reset_type directly, since we now have additional helpers. Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com> Signed-off-by: Michel Thierry <mi

[Intel-gfx] [PATCH i-g-t v2 1/2] lib: Add reset-type helper in ioctl_wrappers

Soon we will have tests that are only for platforms with reset-engine (GEN8+), so add a helper to query the has_gpu_reset via the getparam ioctl. v2: Add more helper functions to avoid using magic numbers in tests (Arek). Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com> Signed-off-by:

Re: [Intel-gfx] [PATCH i-g-t 2/3] lib: Add reset-type helper in ioctl_wrappers

On 6/28/2017 7:10 AM, Arkadiusz Hiler wrote: On Tue, Jun 20, 2017 at 11:25:01AM -0700, Michel Thierry wrote: Soon we will have tests that are only for platforms with reset-engine (GEN8+), so add a helper to query the has_gpu_reset via the getparam ioctl. Signed-off-by: Michel Thierry

[Intel-gfx] [PATCH v2] drm/i915: There is only one fault register from Gen8 onwards

register addresses haven't been reused, but we should not been reading (and writing to) registers that do not exist. v2: Rename fault variable, use INTEL_GEN (Chris). References: IHD-OS-BDW-Vol 2c-11.15, page 75. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <mi

Re: [Intel-gfx] [PATCH] drm/i915: There is only one fault register from Gen8 onwards

On 23/06/17 16:35, Chris Wilson wrote: Quoting Michel Thierry (2017-06-24 00:17:29) Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register, 0x4194 - media fault register, etc). But since Broadwell, all these registers were combined

[Intel-gfx] [PATCH] drm/i915: There is only one fault register from Gen8 onwards

register addresses haven't been reused, but we should not been reading (and writing to) registers that do not exist. References: IHD-OS-BDW-Vol 2c-11.15, page 75. Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fix mutex imbalance for igt_render_engine_reset_fallback

On 23/06/17 06:19, Chris Wilson wrote: Smatch spots: drivers/gpu/drm/i915/selftests/intel_hangcheck.c:669 igt_render_engine_reset_fallback() error: double unlock 'mutex:>drm.struct_mutex' Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Michel Thierry <

[Intel-gfx] [PATCH i-g-t 1/3] lib: Force global reset + uevents for hang detector

resets for explict igt_allow_hang() Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170605121314.21135-1-ch...@chris-wilson.co.uk Reviewed-by: Michel Thierry <michel.thie...@

[Intel-gfx] [PATCH i-g-t 3/3] tests/gem_reset_stats: Enforce full chip reset mode before run

the number of per-engine resets and use reset_count + reset_engine_count when checking for the updated reset count. Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- tests/gem_reset_stats.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tests/gem_reset_s

[Intel-gfx] [PATCH i-g-t 2/3] lib: Add reset-type helper in ioctl_wrappers

Soon we will have tests that are only for platforms with reset-engine (GEN8+), so add a helper to query the has_gpu_reset via the getparam ioctl. Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- lib/ioctl_wrappers.c | 22 ++ lib/ioctl_wrappers.h | 1 + 2

Re: [Intel-gfx] Per-engine reset

On 20/06/17 04:03, Tvrtko Ursulin wrote: On 20/06/2017 10:57, Chris Wilson wrote: Next chunk from Michel finally reviewed, after a little hiatus as the series uncovered a deadlock with concurrent resets. Will apply if no objections, and move on to the guc enabling patches. Go for it! :)

Re: [Intel-gfx] [PATCH v2] drm/i915: Wait for concurrent global resets to complete

into the existing reset_queue, and remember that kselftests is playing games with I915_RESET_BACKOFF to prevent hangcheck from screwing up. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michel Thierry <michel.thie...@intel.co

Re: [Intel-gfx] [PATCH v9 05/21] drm/i915: Add support for per engine reset recovery

On 19/06/17 05:46, Chris Wilson wrote: Quoting Michel Thierry (2017-06-15 21:18:12) @@ -2992,10 +3014,8 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) lockdep_assert_held(_priv->drm.struct_mutex); - for_each_engine(engine, dev_priv,

Re: [Intel-gfx] [PATCH v9 10/21] drm/i915: Add engine reset count in get-reset-stats ioctl

On 15/06/17 14:14, Chris Wilson wrote: Quoting Michel Thierry (2017-06-15 21:18:17) Users/tests relying on the total reset count will start seeing a smaller number since most of the hangs can be handled by engine reset. Note that if reset engine x, context a running on engine y will be unaware

[Intel-gfx] [PATCH v9 21/21] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs

, provide a simple debugfs entry to see the number of times media reset has happened. v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic; use READ_ONCE. (Chris) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- dri

[Intel-gfx] [PATCH v9 11/21] drm/i915/selftests: reset engine self tests

Check that we can reset specific engines, also check the fallback to full reset if something didn't work. v2: rebase. v3: use RESET_ENGINE_IN_PROGRESS flag. v4: use I915_RESET_ENGINE flag. Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/sel

[Intel-gfx] [PATCH v9 14/21] drm/i915/guc: Rename the function that resets the GuC

rsu...@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_uc.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 3 files changed,

[Intel-gfx] [PATCH v9 09/21] drm/i915: Enable Engine reset and recovery support

luvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 045

[Intel-gfx] [PATCH v9 18/21] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+

ize in emit_stop_watchdog. (Chris) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Ian Lister <ian.lis...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.

[Intel-gfx] [PATCH v9 04/21] drm/i915: Include reset engine information in has_gpu_reset getparam

So users (tests) can detect which type of reset (engine vs global) is active. Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dri

[Intel-gfx] [PATCH v9 20/21] drm/i915: Watchdog timeout: Include threshold value in error state

Save the watchdog threshold (in us) as part of the engine state. v2: Only do it for gen8+ (and prevent a missing-case warn). Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 12 -

[Intel-gfx] [PATCH v9 12/21] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

t;michal.winiar...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <michal.winiar...@intel.com> (v2) Signed-off-by: Michel Thierry <michel

[Intel-gfx] [PATCH v9 16/21] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load

/resume/reset (Daniele). Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH v9 RFC 08/21] drm/i915: Carry on with reset even if hw engine is not ready

, but it has been seen at least once in CI. References: https://intel-gfx-ci.01.org/CI/Trybot_831/ Reported-by: Antonio Argenziano <antonio.argenzi...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Michel Th

[Intel-gfx] [PATCH v9 07/21] drm/i915: Export per-engine reset count info to debugfs

in i915_engine_info too (Chris). Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/

[Intel-gfx] [PATCH v9 03/21] drm/i915: Modify error handler for per engine hang recovery

gine flag locking better (Chris) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Ian Lister <ian.lis...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.inte

[Intel-gfx] [PATCH v9 19/21] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

(magic 8-ball predicts this will change again later on, so future-proof it). (Daniele) Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Mi

[Intel-gfx] [PATCH v9 10/21] drm/i915: Add engine reset count in get-reset-stats ioctl

to use pad as input (Antonio) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Antonio Argenziano <antonio.argenzi...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v9 13/21] drm/i915/guc: Provide register list to be saved/restored during engine reset

/WA_REG_WR_GUC_RESTORE). v5: Only ask guc to reapply workarounds in case of render reset (Daniele). Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Jeff McGee <jeff.mc...@intel.com> Signed-off-

[Intel-gfx] [PATCH v9 06/21] drm/i915: Add engine reset count to error state

/reset_engine/ (Chris) Define count as unsigned int (Tvrtko) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> -

[Intel-gfx] [PATCH v9 01/21] drm/i915: Look for active requests earlier in the reset path

-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> (v5) Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 14 +++--- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 2 files cha

[Intel-gfx] [PATCH v9 17/21] drm/i915: Watchdog timeout: IRQ handler for gen8+

n Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_irq.c | 19 +++-- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_hang

[Intel-gfx] [PATCH v9 02/21] drm/i915: Update i915.reset to handle engine resets

<arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_params.c | 6 +++--- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/

[Intel-gfx] [PATCH v9 15/21] drm/i915/guc: Add support for reset engine using GuC commands

it regardless of submission mode. (Chris) Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c| 24 +++ dr

[Intel-gfx] [PATCH v9 05/21] drm/i915: Add support for per engine reset recovery

ris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 48

[Intel-gfx] [PATCH v9 00/21] Gen8+ engine-reset

eset _readiness_. v9: Support parallel resets (in different engines). Return type of reset available in get-param ioctl. Watchdog timeout won't capture the error state. Daniele Ceraolo Spurio (1): drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder Michel Thierry (20): drm/i915:

Re: [Intel-gfx] Fixes that failed to backport to v4.12-rc1

On 13/06/17 01:27, Jani Nikula wrote: On Mon, 15 May 2017, Jani Nikula wrote: Continuing [1] for v4.12-rc1 The following commits have been marked as Cc: stable or fixing something in v4.12-rc1 or earlier, but failed to cherry-pick to drm-intel-fixes. Please see if they

Re: [Intel-gfx] [PATCH v2] igt/gem_reset_stats: Fix pending batches status expectation

ge (Michel Thierry) Cc: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Antonio Argenziano <antonio.argenzi...@intel.com> My rb[1] still stands. Thanks for resending this. -Michel [1]https://lists.freedesktop.org/archives/intel-gfx

Re: [Intel-gfx] [i-g-t] igt/gem_reset_stats: Fix pending batches status expectation

uests"), that is no longer the case. Cc: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Antonio Argenziano <antonio.argenzi...@intel.com> If we want the test to pass, then it's ok. Someone else may say we need further subtests. On the basis this brings existing tests to t

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Clear enable_guc_loading in case of init failure (rev2)

On 6/5/2017 10:32 AM, Patchwork wrote: == Series Details == Series: drm/i915/guc: Clear enable_guc_loading in case of init failure (rev2) URL : https://patchwork.freedesktop.org/series/25228/ State : success == Summary == Series 25228v2 drm/i915/guc: Clear enable_guc_loading in case of init

Re: [Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

On 6/6/2017 3:16 AM, Chris Wilson wrote: I didn't think it was sensible to advertise reset-engine support without global reset (or the hangcheck to detect the error), and for the time being we can keep thinking of this as an integer rather than a set of flags. So I was just thinking of value =

[Intel-gfx] [PATCH v9] drm/i915: Modify error handler for per engine hang recovery

ux.intel.com> Signed-off-by: Ian Lister <ian.lis...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c

Re: [Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

On 6/4/2017 5:06 AM, Chris Wilson wrote: And whilst I'm here, we need to extend I915_PARAM_HAS_GPU_RESET to indicate having per-engine resets for the complimentary set of igt. -Chris Something like this? case I915_PARAM_HAS_GPU_RESET: - value = i915.enable_hangcheck &&

Re: [Intel-gfx] [PATCH igt v2] lib: Force global reset + uevents for hang detector

On 6/5/2017 3:57 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-06-05 22:21:48) On 6/5/2017 5:13 AM, Chris Wilson wrote: The hang detector relies on a uevent for notification and aborting the test. As proposed, fine-grained resets may not produce a global uevent and so this hang

Re: [Intel-gfx] [PATCH igt v2] lib: Force global reset + uevents for hang detector

for explict igt_allow_hang() Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> --- lib/igt_aux.c | 10 lib/igt_gt.c| 4 lib/igt_sysfs.c | 72 ++--- lib/igt_

[Intel-gfx] [PATCH v2] drm/i915/guc: Clear enable_guc_loading in case of init failure

oonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c

[Intel-gfx] [PATCH] drm/i915/guc: Clear enable_guc_loading in case of init failure

is Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 5 + 1 file changed, 5 insertions(

Re: [Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

On 6/2/2017 1:16 PM, Chris Wilson wrote: Quoting Michel Thierry (2017-05-22 18:46:24) + /* try engine reset first, and continue if fails */ /* Please use sentences when convenient. It looks much neater that way. */ _less_ broken English: /* * Try engine reset when available. We

Re: [Intel-gfx] [PATCH] drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionally

{ - i915->ggtt.invalidate = gen6_ggtt_invalidate; + if (i915->ggtt.invalidate == guc_ggtt_invalidate) + i915->ggtt.invalidate = gen6_ggtt_invalidate; } void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) Reviewed-by: Michel Thierry <michel.thie.

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