[Intel-gfx] [PATCH i-g-t 0/5] Validate TEST_ONLY correctness against full atomic commit

[Mika Kahola]

This test case adds TEST_ONLY flag to the following test cases to test
atomic commit correctness.

 - kms_plane_multiple
 - kms_atomic_transitions
 - kms_plane_scaling
 - kms_rotation_crc

The test randomly selects one of the above test cases and tests atomic
commit. If the test fails with TEST_ONLY flag the real deal atomic commit
is executed and the outcome is verified.

For: VIZ-6956

Mika Kahola (5):
  tests/kms_plane_multiple: Add TEST_ONLY flag
  tests/kms_atomic_transition: Add TEST_ONLY flag
  tests/kms_plane_scaling: Add TEST_ONLY flag
  tests/kms_rotation_crc: Add TEST_ONLY flag
  tests/kms_test_only: Validate TEST_ONLY correctness against full
atomic commit

 tests/Makefile.sources|   1 +
 tests/kms_atomic_transition.c | 227 ++---
 tests/kms_plane_multiple.c|  79 +---
 tests/kms_plane_scaling.c | 152 --
 tests/kms_rotation_crc.c  | 282 --
 tests/kms_test_only.c | 455 ++
 6 files changed, 1014 insertions(+), 182 deletions(-)
 create mode 100644 tests/kms_test_only.c

-- 
2.7.4

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[Intel-gfx] [PATCH i-g-t 4/5] tests/kms_rotation_crc: Add TEST_ONLY flag

[Mika Kahola]

Add TEST_ONLY flag to test atomic transition display commits without
actual real-life commit.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/kms_rotation_crc.c | 282 +--
 1 file changed, 222 insertions(+), 60 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 796b448..434f845 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -84,11 +84,25 @@ paint_squares(data_t *data, drmModeModeInfo *mode, 
igt_rotation_t rotation,
cairo_destroy(cr);
 }
 
-static void commit_crtc(data_t *data, igt_output_t *output, igt_plane_t *plane)
+static int display_commit_test_only(igt_display_t *display)
+{
+   int ret;
+
+   ret = igt_display_try_commit_atomic(display,
+   DRM_MODE_ATOMIC_TEST_ONLY |
+   DRM_MODE_ATOMIC_ALLOW_MODESET,
+   NULL);
+
+   return ret;
+}
+
+static void commit_crtc(data_t *data, igt_output_t *output, igt_plane_t *plane,
+   bool test_only)
 {
igt_display_t *display = >display;
enum igt_commit_style commit = COMMIT_LEGACY;
igt_plane_t *primary;
+   int ret;
 
/*
 * With igt_display_commit2 and COMMIT_UNIVERSAL, we call just the
@@ -99,7 +113,13 @@ static void commit_crtc(data_t *data, igt_output_t *output, 
igt_plane_t *plane)
 
primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
igt_plane_set_fb(primary, >fb_modeset);
-   igt_display_commit(display);
+
+   if (test_only) {
+   ret = display_commit_test_only(display);
+   igt_assert_eq(ret, 0);
+   } else {
+   igt_display_commit(display);
+   }
 
igt_plane_set_fb(plane, >fb);
 
@@ -111,12 +131,19 @@ static void commit_crtc(data_t *data, igt_output_t 
*output, igt_plane_t *plane)
 
if (data->display.is_atomic)
commit = COMMIT_ATOMIC;
+   else
+   igt_skip_on(test_only);
 
-   igt_display_commit2(display, commit);
+   if (test_only) {
+   ret = display_commit_test_only(display);
+   igt_assert_eq(ret, 0);
+   } else {
+   igt_display_commit2(display, commit);
+   }
 }
 
 static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
-igt_plane_t *plane)
+igt_plane_t *plane, bool test_only)
 {
drmModeModeInfo *mode;
int fb_id, fb_modeset_id;
@@ -181,8 +208,10 @@ static void prepare_crtc(data_t *data, igt_output_t 
*output, enum pipe pipe,
 
/* Step 1: create a reference CRC for a software-rotated fb */
paint_squares(data, mode, data->rotation, >fb, 1.0);
-   commit_crtc(data, output, plane);
-   igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
+   commit_crtc(data, output, plane, test_only);
+
+   if (!test_only)
+   igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
 
/*
 * Step 2: prepare the plane with an non-rotated fb let the hw
@@ -192,10 +221,12 @@ static void prepare_crtc(data_t *data, igt_output_t 
*output, enum pipe pipe,
igt_plane_set_fb(plane, >fb);
 }
 
-static void cleanup_crtc(data_t *data, igt_output_t *output, igt_plane_t 
*plane)
+static void cleanup_crtc(data_t *data, igt_output_t *output, igt_plane_t 
*plane,
+   bool test_only)
 {
igt_display_t *display = >display;
-
+   int ret;
+
igt_pipe_crc_free(data->pipe_crc);
data->pipe_crc = NULL;
 
@@ -215,7 +246,12 @@ static void cleanup_crtc(data_t *data, igt_output_t 
*output, igt_plane_t *plane)
igt_plane_set_fb(plane, NULL);
igt_output_set_pipe(output, PIPE_ANY);
 
-   igt_display_commit(display);
+   if (test_only) {
+   ret = display_commit_test_only(display);
+   igt_assert_eq(ret, 0);
+   } else {
+   igt_display_commit(display);
+   }
 }
 
 static void wait_for_pageflip(int fd)
@@ -235,7 +271,7 @@ static void wait_for_pageflip(int fd)
igt_assert(drmHandleEvent(fd, ) == 0);
 }
 
-static void test_plane_rotation(data_t *data, enum igt_plane plane_type)
+static void test_plane_rotation(data_t *data, enum igt_plane plane_type, bool 
test_only)
 {
igt_display_t *display = >display;
igt_output_t *output;
@@ -254,6 +290,8 @@ static void test_plane_rotation(data_t *data, enum 
igt_plane plane_type)
 
if (data->display.is_atomic)
commit = COMMIT_ATOMIC;
+   else
+   igt_skip_on(test_only);
 
for_each_connected_output(display, output) {
for_each_pipe(display, pipe) {
@@ -264,17 +302,32 @@ static void test_plane_rotation(data_t *data, enum 
igt_plane plane_type)
plane = igt_output_get_plane(ou

[Intel-gfx] [PATCH i-g-t 5/5] tests/kms_test_only: Validate TEST_ONLY correctness against full atomic commit

[Mika Kahola]

This test case adds TEST_ONLY flag to the following test cases to test
atomic commit correctness.

 - kms_plane_multiple
 - kms_atomic_transitions
 - kms_plane_scaling
 - kms_rotation_crc

The test randomly selects one of the above test cases and tests atomic
commit. If the test fails with TEST_ONLY flag the real deal atomic commit
is executed and the outcome is verified.

The test runs by default for 64 iterations.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_test_only.c  | 455 +
 2 files changed, 456 insertions(+)
 create mode 100644 tests/kms_test_only.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6316ea6..ff599c3 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -112,6 +112,7 @@ TESTS_progs_M = \
kms_plane \
kms_plane_multiple \
kms_plane_lowres \
+   kms_test_only \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_test_only.c b/tests/kms_test_only.c
new file mode 100644
index 000..1ae835e
--- /dev/null
+++ b/tests/kms_test_only.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with a TEST_ONLY flag");
+
+#define LOOP_FOREVER -1
+
+#define FAIL   -1
+#define SKIP0
+#define SUCCESS 1
+
+/* Command line parameters. */
+struct {
+   int iterations;
+} opt = {
+   .iterations = 64,
+};
+
+static
+int parse_output(char *testname)
+{
+   FILE *fid;
+   char output[1024];
+   char result[32];
+
+   fid = popen(testname, "r");
+   igt_assert(fid != NULL);
+
+   while (fgets(output, sizeof(output)-1, fid) != NULL) {
+   if (strstr(output, "Subtest")) {
+   sscanf(output, "%*s %*s %s%*c", result);
+
+   if (strncmp(result, "FAIL", 4) == 0) {
+   pclose(fid);
+   return FAIL;
+   } else if (strncmp(result, "SKIP", 4) == 0) {
+   pclose(fid);
+   return SKIP;
+   } else if (strncmp(result, "SUCCESS", 7) == 0) {
+   pclose(fid);
+   return SUCCESS;
+   }
+   } else if (strstr(output, "Test requirement not met in 
function")) {
+   pclose(fid);
+   return SKIP;
+   }
+   }
+
+   pclose(fid);
+
+   return -EINVAL;
+}
+
+static
+void test_kms_rotation_crc(void)
+{
+   int ret;
+   char testname[256];
+
+   strcpy(testname, "kms_rotation_crc --run-subtest 
primary-rotation-180-test-only");
+   ret = parse_output(testname);
+   if (ret == SKIP)
+   return;
+
+   if (ret == FAIL) {
+   igt_info("%s failed. Trying with real atomic commit\n", 
testname);
+   strcpy(testname, "kms_rotation_crc --run-subtest 
primary-rotation-180");
+   ret = parse_output(testname);
+   igt_assert_eq(ret, FAIL);
+   }
+
+   strcpy(testname, "kms_rotation_crc --run-subtest 
sprite-rotation-180-test-only");
+   ret = parse_output(testname);
+   if (ret == SKIP)
+   return;
+
+   if (ret == FAIL) {
+   igt_info("%s failed. Trying with real atomic commit\n", 
testname);
+   strcpy(testname, "kms_rotation_crc --run-subtest 
sprite-rotation-180"

[Intel-gfx] [PATCH i-g-t 1/5] tests/kms_plane_multiple: Add TEST_ONLY flag

[Mika Kahola]

Add TEST_ONLY flag to test atomic modesetting commits without
actual real-life commit.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/kms_plane_multiple.c | 79 --
 1 file changed, 49 insertions(+), 30 deletions(-)

diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index 5e12be4..1a77a38 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -61,10 +61,12 @@ struct {
int iterations;
bool user_seed;
int seed;
+   bool test_only;
 } opt = {
.iterations = 64,
.user_seed = false,
.seed = 1,
+   .test_only = false,
 };
 
 static inline uint32_t pipe_select(int pipe)
@@ -228,7 +230,7 @@ prepare_planes(data_t *data, enum pipe pipe, color_t *color,
 static void
 test_atomic_plane_position_with_output(data_t *data, enum pipe pipe,
   igt_output_t *output, int max_planes,
-  uint64_t tiling)
+  uint64_t tiling, bool test_only)
 {
char buf[256];
struct drm_event *e = (void *)buf;
@@ -240,6 +242,12 @@ test_atomic_plane_position_with_output(data_t *data, enum 
pipe pipe,
int iterations = opt.iterations < 1 ? 1 : opt.iterations;
bool loop_forever;
char info[256];
+   int flags = DRM_MODE_ATOMIC_ALLOW_MODESET;
+
+   if (test_only)
+   flags |= DRM_MODE_ATOMIC_TEST_ONLY;
+   else
+   flags |= DRM_MODE_PAGE_FLIP_EVENT;
 
if (opt.iterations == LOOP_FOREVER) {
loop_forever = true;
@@ -256,8 +264,9 @@ test_atomic_plane_position_with_output(data_t *data, enum 
pipe pipe,
 
test_init(data, pipe);
 
-   test_grab_crc(data, output, pipe, true, , tiling,
- _crc);
+   if (!test_only)
+   test_grab_crc(data, output, pipe, true, , tiling,
+ _crc);
 
i = 0;
while (i < iterations || loop_forever) {
@@ -265,24 +274,27 @@ test_atomic_plane_position_with_output(data_t *data, enum 
pipe pipe,
 
vblank_start = get_vblank(data->display.drm_fd, pipe, 
DRM_VBLANK_NEXTONMISS);
 
-   igt_display_commit_atomic(>display,
- DRM_MODE_PAGE_FLIP_EVENT,
- >display);
+   ret = igt_display_try_commit_atomic(>display,
+   flags,
+   >display);
+   igt_assert(ret != -EINVAL);
 
-   igt_set_timeout(1, "Stuck on page flip");
+   if (!test_only) {
+   igt_set_timeout(1, "Stuck on page flip");
 
-   ret = read(data->display.drm_fd, buf, sizeof(buf));
-   igt_assert(ret >= 0);
+   ret = read(data->display.drm_fd, buf, sizeof(buf));
+   igt_assert(ret >= 0);
 
-   igt_assert_eq(get_vblank(data->display.drm_fd, pipe, 0), 
vblank_start + 1);
-   igt_assert_eq(e->type, DRM_EVENT_FLIP_COMPLETE);
-   igt_reset_timeout();
+   igt_assert_eq(get_vblank(data->display.drm_fd, pipe, 
0), vblank_start + 1);
+   igt_assert_eq(e->type, DRM_EVENT_FLIP_COMPLETE);
+   igt_reset_timeout();
 
-   n = igt_pipe_crc_get_crcs(data->pipe_crc, MAX_CRCS, );
+   n = igt_pipe_crc_get_crcs(data->pipe_crc, MAX_CRCS, 
);
 
-   igt_assert_eq(n, MAX_CRCS);
+   igt_assert_eq(n, MAX_CRCS);
 
-   igt_assert_crc_equal(_crc, crc);
+   igt_assert_crc_equal(_crc, crc);
+   }
 
i++;
}
@@ -345,7 +357,7 @@ test_legacy_plane_position_with_output(data_t *data, enum 
pipe pipe,
 
 static void
 test_plane_position(data_t *data, enum pipe pipe, bool atomic, int max_planes,
-   uint64_t tiling)
+   uint64_t tiling, bool test_only)
 {
igt_output_t *output;
int connected_outs;
@@ -372,7 +384,8 @@ test_plane_position(data_t *data, enum pipe pipe, bool 
atomic, int max_planes,
test_atomic_plane_position_with_output(data, pipe,
   output,
   max_planes,
-  tiling);
+  tiling,
+  test_only);
else
test_legacy_plane_position_with_output(data, pipe,
   output,
@@ -387,54 +

Re: [Intel-gfx] [PATCH v2] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

Hi Bob,

On Tue, 2016-12-20 at 09:53 -0800, Bob Paauwe wrote:
> On Tue, 13 Dec 2016 16:11:20 +0200
> Jani Nikula <jani.nik...@intel.com> wrote:
> 
> > 
> > On Mon, 05 Dec 2016, Mika Kahola <mika.kah...@intel.com> wrote:
> > > 
> > > From: Jani Nikula <jani.nik...@intel.com>
> > > 
> > > Request the GPIO by index through the consumer API. For now, use
> > > a quick
> > > hack to store the already requested ones, simply because I have
> > > no idea
> > > whether this actually works or not, and I have no way to test it.
> > > 
> > > v2: switch *NULL* to *"panel"* when requesting gpio for MIPI/DSI
> > > panel. (Mika)
> > > 
> Jani, Mika,
> 
> I'm working on getting a dual-link MIPI panel working on BXT and have
> a
> problem getting the proper GPIO pins set.  This patch gets things
> closer, but at least for the platform I'm working on, there's one
> GPIO
> pin (backlight/panel control) that doesn't seem to be available via
> the
> consumer API.  If I use the alternate#2 method that Jani posted
> (legacy GPIO API) along with the proper defines I can set this pin.
> I'm
> using:
> 
> 
> #define BXT_PANEL1_VDDEN_PIN   196
> #define BXT_PANEL1_BKLTEN_PIN  197
> #define BXT_PANEL1_BKLTCTL_PIN 198
> 
> #define BXT_PANEL1_VDDEN_OFFSET366
> #define BXT_PANEL1_BKLTEN_OFFSET   367
> #define BXT_PANEL1_BKLTCTL_OFFSET  368
> 
> to create my GPIO table.  
> 
> These three pins need to be set VDDEN, BKLTCTL, BKLTEN, in that order
> to get the panel to turn on.
> 
> For testing, I have a call in the vbt_panel_prepare() to set the pin
> and one in vbt_panel_unprepare() to clear it.  That works but that
> doesn't seem like the right solution.  I was wondering if either of
> you
> have any insights?
Do you see these warnings in dmesg such as 'GPIO index x request
failed'? This is what you should see if the pin can't be accessed. 

Can you see  all of these GPIO pins in /sys/kernel/debug/gpio file?

And you also need to enable pincontrol for Broxton in kernel config

CONFIG_PINCTRL_BROXTON=y



> Bob
> 
> > 
> > > 
> > > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> > > Signed-off-by: Mika Kahola <mika.kah...@intel.com>  
> > Pushed to dinq.
> > 
> > BR,
> > Jani.
> > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 38
> > > +-
> > >  1 file changed, 32 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > index 0d8ff00..dda678b 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > @@ -29,6 +29,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >  #include 
> > >  #include 
> > >  #include 
> > > @@ -304,19 +305,44 @@ static void chv_exec_gpio(struct
> > > drm_i915_private *dev_priv,
> > >   mutex_unlock(_priv->sb_lock);
> > >  }
> > >  
> > > +static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> > > +   u8 gpio_source, u8 gpio_index, bool
> > > value)
> > > +{
> > > + /* XXX: this table is a quick ugly hack. */
> > > + static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
> > > + struct gpio_desc *gpio_desc =
> > > bxt_gpio_table[gpio_index];
> > > +
> > > + if (!gpio_desc) {
> > > + gpio_desc = devm_gpiod_get_index(dev_priv-
> > > >drm.dev,
> > > +  "panel",
> > > gpio_index,
> > > +  value ?
> > > GPIOD_OUT_LOW :
> > > +  GPIOD_OUT_HIGH)
> > > ;
> > > +
> > > + if (IS_ERR_OR_NULL(gpio_desc)) {
> > > + DRM_ERROR("GPIO index %u request failed
> > > (%ld)\n",
> > > +   gpio_index,
> > > PTR_ERR(gpio_desc));
> > > + return;
> > > + }
> > > +
> > > + bxt_gpio_table[gpio_index] = gpio_desc;
> > > + }
> > > +
> > > + gpiod_set_value(gpio_desc, value);
> > > +}
> > > +
> > >  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi,
> > > const u8 *data)
&

[Intel-gfx] [PATCH i-g-t v3] tests/kms_plane_lowres: Plane visibility after atomic modesets

[Mika Kahola]

Testcase for plane visibility after atomic modesets. The idea of the test
is the following:

 - draw a blue screen with high resolution
 - enable a yellow plane, visible, in lower-left corner
 - set a new lower resolution mode (1024x768) that makes plane invisible
 - check from debugfs 'i915_display_info' that the plane is invisible
 - switch back to higher resolution mode
 - check from debugfs 'i915_display_info' that the plane is visible again
 - repeat number of iterations, default 64

v2: allow test to be run on non-Intel drivers (Daniel)
moved test for plane visibility to as helper function (Daniel)
moved get_vblank() function to be part of helper functions (Daniel)
rename 'tiling' parameter as 'modifier' (Daniel)
select a mode from a list so that the plane should be invisible.
use default 1024x768 mode only as a fallback if decent mode has not
been found (Daniel)
add tiling MODE_NONE (Daniel)

v3: draw as many overlay planes as the platform supports + cursor plane
on top of each other on lower-left corner
skip the test if i915_display_info file is not available
test plane visibility with igt_assert_plane_visibility() function
drop option for multiple test iterations (Daniel Vetter)

Cc: Daniel Stone <dan...@fooishbar.org>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 lib/igt_kms.c| 161 ++
 lib/igt_kms.h|  23 
 tests/Makefile.sources   |   1 +
 tests/kms_plane_lowres.c | 344 +++
 4 files changed, 529 insertions(+)
 create mode 100644 tests/kms_plane_lowres.c

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 989704e..1ef74dc 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -324,6 +324,24 @@ const char *kmstest_pipe_name(enum pipe pipe)
 }
 
 /**
+ * kmstest_pipe_to_index:
+ *@pipe: display pipe in string format
+ *
+ * Returns: index to corresponding pipe
+ */
+int kmstest_pipe_to_index(char pipe)
+{
+   if (pipe == 'A')
+   return 0;
+   else if (pipe == 'B')
+   return 1;
+   else if (pipe == 'C')
+   return 2;
+   else
+   return -EINVAL;
+}
+
+/**
  * kmstest_plane_name:
  * @plane: display plane
  *
@@ -1176,6 +1194,149 @@ int kmstest_get_crtc_idx(drmModeRes *res, uint32_t 
crtc_id)
igt_assert(false);
 }
 
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pipe > 0)
+   return DRM_VBLANK_SECONDARY;
+   else
+   return 0;
+}
+
+unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe) | flags;
+   if (drmIoctl(fd, DRM_IOCTL_WAIT_VBLANK, ))
+   return 0;
+
+   return vbl.reply.sequence;
+}
+
+static void get_plane(char *str, int type, struct kmstest_plane *plane)
+{
+   int ret;
+   char buf[256];
+
+   plane->plane = type;
+   ret = sscanf(str + 12, "%d%*c %*s %[^n]s",
+>id,
+buf);
+   igt_assert_eq(ret, 2);
+
+   ret = sscanf(buf + 9, "%4d%*c%4d%*c", >pos_x, >pos_y);
+   igt_assert_eq(ret, 2);
+
+   ret = sscanf(buf + 30, "%4d%*c%4d%*c", >width, >height);
+   igt_assert_eq(ret, 2);
+}
+
+static int parse_planes(FILE *fid, struct kmstest_plane *plane)
+{
+   char tmp[256];
+   int nplanes;
+   int ovl;
+
+   ovl = 0;
+   nplanes = 0;
+   while (fgets(tmp, 256, fid) != NULL) {
+   igt_assert_neq(nplanes, IGT_MAX_PLANES);
+   if (strstr(tmp, "type=PRI") != NULL) {
+   get_plane(tmp, IGT_PLANE_PRIMARY, [nplanes]);
+   nplanes++;
+   } else if (strstr(tmp, "type=OVL") != NULL) {
+   get_plane(tmp, IGT_PLANE_2 + ovl, [nplanes]);
+   ovl++;
+   nplanes++;
+   } else if (strstr(tmp, "type=CUR") != NULL) {
+   get_plane(tmp, IGT_PLANE_CURSOR, [nplanes]);
+   nplanes++;
+   break;
+   }
+   }
+
+   return nplanes;
+}
+
+static void parse_crtc(char *info, struct kmstest_crtc *crtc)
+{
+   char buf[256];
+   int ret;
+   char pipe;
+
+   ret = sscanf(info + 4, "%d%*c %*s %c%*c %*s %s%*c",
+>id, , buf);
+   igt_assert_eq(ret, 3);
+
+   crtc->pipe = kmstest_pipe_to_index(pipe);
+   igt_assert(crtc->pipe >= 0);
+
+   ret = sscanf(buf + 6, "%d%*c%d%*c",
+>width, >height);
+   igt_assert_eq(ret, 2);
+}
+
+void kmstest_get_crtc(enum pipe pipe, struct kmstest

[Intel-gfx] [PATCH 2/3] drm/i915: Intel panel downclock cleanup

[Mika Kahola]

Let's switch to use dev_priv instead of dev when calling
intel_find_panel_downclock() function.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 2 +-
 drivers/gpu/drm/i915/intel_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_panel.c | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d95c445..4cec029 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5493,7 +5493,7 @@ intel_dp_drrs_init(struct intel_connector 
*intel_connector,
}
 
downclock_mode = intel_find_panel_downclock
-   (dev, fixed_mode, connector);
+   (dev_priv, fixed_mode, connector);
 
if (!downclock_mode) {
DRM_DEBUG_KMS("Downclock mode is not found. DRRS not 
supported\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 79edcf1..eb4bd6a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1594,7 +1594,7 @@ void intel_panel_disable_backlight(struct intel_connector 
*connector);
 void intel_panel_destroy_backlight(struct drm_connector *connector);
 enum drm_connector_status intel_panel_detect(struct drm_i915_private 
*dev_priv);
 extern struct drm_display_mode *intel_find_panel_downclock(
-   struct drm_device *dev,
+   struct drm_i915_private *dev_priv,
struct drm_display_mode *fixed_mode,
struct drm_connector *connector);
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index f6637bd..41427a45 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -48,7 +48,7 @@ intel_fixed_panel_mode(const struct drm_display_mode 
*fixed_mode,
 
 /**
  * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID
- * @dev: drm device
+ * @dev_priv: i915 device instance
  * @fixed_mode : panel native mode
  * @connector: LVDS/eDP connector
  *
@@ -56,7 +56,7 @@ intel_fixed_panel_mode(const struct drm_display_mode 
*fixed_mode,
  * Find the reduced downclock for LVDS/eDP in EDID.
  */
 struct drm_display_mode *
-intel_find_panel_downclock(struct drm_device *dev,
+intel_find_panel_downclock(struct drm_i915_private *dev_priv,
struct drm_display_mode *fixed_mode,
struct drm_connector *connector)
 {
@@ -94,7 +94,7 @@ intel_find_panel_downclock(struct drm_device *dev,
}
 
if (temp_downclock < fixed_mode->clock)
-   return drm_mode_duplicate(dev, tmp_mode);
+   return drm_mode_duplicate(_priv->drm, tmp_mode);
else
return NULL;
 }
-- 
2.7.4

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[Intel-gfx] [PATCH 3/3] drm/i915: Hz to PWM for i965

[Mika Kahola]

Unify function structure as any other *_hz_to_pwm() functions are
structured.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_panel.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index 41427a45..a67da98 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1330,8 +1330,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector 
*connector, u32 pwm_freq_hz)
  */
 static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
-   struct drm_device *dev = connector->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
int clock;
 
if (IS_G4X(dev_priv))
-- 
2.7.4

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[Intel-gfx] [PATCH 1/3] drm/i915: Intel panel detection cleanup

[Mika Kahola]

Let's switch to use private dev_priv instead of dev when detecting
intel panels.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c| 3 ++-
 drivers/gpu/drm/i915/intel_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_lvds.c  | 4 ++--
 drivers/gpu/drm/i915/intel_panel.c | 4 +---
 4 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9dfbde4..d95c445 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4152,9 +4152,10 @@ static enum drm_connector_status
 edp_detect(struct intel_dp *intel_dp)
 {
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+   struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_connector_status status;
 
-   status = intel_panel_detect(dev);
+   status = intel_panel_detect(dev_priv);
if (status == connector_status_unknown)
status = connector_status_connected;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d126c2..79edcf1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1592,7 +1592,7 @@ int intel_panel_setup_backlight(struct drm_connector 
*connector,
 void intel_panel_enable_backlight(struct intel_connector *connector);
 void intel_panel_disable_backlight(struct intel_connector *connector);
 void intel_panel_destroy_backlight(struct drm_connector *connector);
-enum drm_connector_status intel_panel_detect(struct drm_device *dev);
+enum drm_connector_status intel_panel_detect(struct drm_i915_private 
*dev_priv);
 extern struct drm_display_mode *intel_find_panel_downclock(
struct drm_device *dev,
struct drm_display_mode *fixed_mode,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index ea1ce17..9ca4dc4 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -460,13 +460,13 @@ static bool intel_lvds_compute_config(struct 
intel_encoder *intel_encoder,
 static enum drm_connector_status
 intel_lvds_detect(struct drm_connector *connector, bool force)
 {
-   struct drm_device *dev = connector->dev;
+   struct drm_i915_private *dev_priv = to_i915(connector->dev);
enum drm_connector_status status;
 
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  connector->base.id, connector->name);
 
-   status = intel_panel_detect(dev);
+   status = intel_panel_detect(dev_priv);
if (status != connector_status_unknown)
return status;
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index 2332970..f6637bd 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -375,10 +375,8 @@ void intel_gmch_panel_fitting(struct intel_crtc 
*intel_crtc,
 }
 
 enum drm_connector_status
-intel_panel_detect(struct drm_device *dev)
+intel_panel_detect(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
/* Assume that the BIOS does not lie through the OpRegion... */
if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) {
return *dev_priv->opregion.lid_state & 0x1 ?
-- 
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[Intel-gfx] [PATCH 0/3] Various cleanups on intel_panel.c

[Mika Kahola]

Proposal for cleanup. Let's favor dev_priv instead of dev in intel_panel.c
functions. Cleanup for HZ to PWM functions to unify the look and feel of
these functions.

Mika Kahola (3):
  drm/i915: Intel panel detection cleanup
  drm/i915: Intel panel downclock cleanup
  drm/i915: Hz to PWM for i965

 drivers/gpu/drm/i915/intel_dp.c|  5 +++--
 drivers/gpu/drm/i915/intel_drv.h   |  4 ++--
 drivers/gpu/drm/i915/intel_lvds.c  |  4 ++--
 drivers/gpu/drm/i915/intel_panel.c | 13 +
 4 files changed, 12 insertions(+), 14 deletions(-)

-- 
2.7.4

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Re: [Intel-gfx] [PATCH] drm/i915: Parse panel BL controller from VBT

[Mika Kahola]

Tested-by: Mika Kahola <mika.kah...@intel.com>

On Wed, 2016-12-07 at 20:32 +0530, Vidya Srinivas wrote:
> Currently the backlight controller is taken as 0. It needs to derive
> value from the VBT. Adding the necessary changes.
> 
> v2: Updated the commit header
> 
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srini...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h| 1 +
>  drivers/gpu/drm/i915/intel_bios.c  | 5 +
>  drivers/gpu/drm/i915/intel_panel.c | 2 +-
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 8daa4fb..6a85fdf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1633,6 +1633,7 @@ struct intel_vbt_data {
>   bool present;
>   bool active_low_pwm;
>   u8 min_brightness;  /* min_brightness/255 of
> max */
> + u8 controller;  /* brightness
> controller number */
>   enum intel_backlight_type type;
>   } backlight;
>  
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index eaade27..130db0f 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -330,6 +330,8 @@ static u32 get_blocksize(const void *block_data)
>  
>   method = _data-
> >backlight_control[panel_type];
>   dev_priv->vbt.backlight.type = method->type;
> + dev_priv->vbt.backlight.controller = 0;
> + dev_priv->vbt.backlight.controller = method-
> >controller;
>   }
>  
>   dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
> @@ -341,6 +343,9 @@ static u32 get_blocksize(const void *block_data)
>     dev_priv->vbt.backlight.active_low_pwm ? "low"
> : "high",
>     dev_priv->vbt.backlight.min_brightness,
>     backlight_data->level[panel_type]);
> +
> + DRM_DEBUG_KMS("VBT BL controller %u\n",
> + dev_priv->vbt.backlight.controller);
>  }
>  
>  /* Try to find sdvo panel data */
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 3578b40..6a7d4c3 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1612,7 +1612,7 @@ static int vlv_setup_backlight(struct
> intel_connector *connector, enum pipe pipe
>    * For BXT hard coding the Backlight controller to 0.
>    * TODO : Read the controller value from VBT and generalize
>    */
> - panel->backlight.controller = 0;
> + panel->backlight.controller = dev_priv-
> >vbt.backlight.controller;
>  
>   pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel-
> >backlight.controller));
>  
-- 
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[Intel-gfx] [PATCH v2] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

From: Jani Nikula <jani.nik...@intel.com>

Request the GPIO by index through the consumer API. For now, use a quick
hack to store the already requested ones, simply because I have no idea
whether this actually works or not, and I have no way to test it.

v2: switch *NULL* to *"panel"* when requesting gpio for MIPI/DSI panel. (Mika)

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 38 +-
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 0d8ff00..dda678b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -304,19 +305,44 @@ static void chv_exec_gpio(struct drm_i915_private 
*dev_priv,
mutex_unlock(_priv->sb_lock);
 }
 
+static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
+ u8 gpio_source, u8 gpio_index, bool value)
+{
+   /* XXX: this table is a quick ugly hack. */
+   static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
+   struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
+
+   if (!gpio_desc) {
+   gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
+"panel", gpio_index,
+value ? GPIOD_OUT_LOW :
+GPIOD_OUT_HIGH);
+
+   if (IS_ERR_OR_NULL(gpio_desc)) {
+   DRM_ERROR("GPIO index %u request failed (%ld)\n",
+ gpio_index, PTR_ERR(gpio_desc));
+   return;
+   }
+
+   bxt_gpio_table[gpio_index] = gpio_desc;
+   }
+
+   gpiod_set_value(gpio_desc, value);
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   u8 gpio_source, gpio_index;
+   u8 gpio_source, gpio_index = 0, gpio_number;
bool value;
 
DRM_DEBUG_KMS("\n");
 
if (dev_priv->vbt.dsi.seq_version >= 3)
-   data++;
+   gpio_index = *data++;
 
-   gpio_index = *data++;
+   gpio_number = *data++;
 
/* gpio source in sequence v2 only */
if (dev_priv->vbt.dsi.seq_version == 2)
@@ -328,11 +354,11 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
value = *data++ & 1;
 
if (IS_VALLEYVIEW(dev_priv))
-   vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+   vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
-   chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+   chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else
-   DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
+   bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 
return data;
 }
-- 
2.7.4

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Re: [Intel-gfx] [PATCH alternative #1] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

On Tue, 2016-11-15 at 14:08 +0200, Jani Nikula wrote:
> Request the GPIO by index through the consumer API. For now, use a
> quick
> hack to store the already requested ones, simply because I have no
> idea
> whether this actually works or not, and I have no way to test it.
> 
> Cc: Mika Kahola <mika.kah...@intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 38
> +-
>  1 file changed, 32 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 9f279a3d0f74..41e0eeac97f4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -304,19 +305,44 @@ static void chv_exec_gpio(struct
> drm_i915_private *dev_priv,
>   mutex_unlock(_priv->sb_lock);
>  }
>  
> +static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> +   u8 gpio_source, u8 gpio_index, bool value)
> +{
> + /* XXX: this table is a quick ugly hack. */
> + static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
> + struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
> +
> + if (!gpio_desc) {
> + gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
> +  NULL, gpio_index,
This patch works better with *NULL* replaced by *"panel"*. With this
change we can access GPIO's without GPIO index request failures.

> +  value ?
> GPIOD_OUT_LOW :
> +  GPIOD_OUT_HIGH);
> +
> + if (IS_ERR_OR_NULL(gpio_desc)) {
> + DRM_ERROR("GPIO index %u request failed
> (%ld)\n",
> +   gpio_index, PTR_ERR(gpio_desc));
> + return;
> + }
> +
> + bxt_gpio_table[gpio_index] = gpio_desc;
> + }
> +
> + gpiod_set_value(gpio_desc, value);
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const
> u8 *data)
>  {
>   struct drm_device *dev = intel_dsi->base.base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> - u8 gpio_source, gpio_index;
> + u8 gpio_source, gpio_index = 0, gpio_number;
>   bool value;
>  
>   DRM_DEBUG_KMS("\n");
>  
>   if (dev_priv->vbt.dsi.seq_version >= 3)
> - data++;
> + gpio_index = *data++;
>  
> - gpio_index = *data++;
> + gpio_number = *data++;
>  
>   /* gpio source in sequence v2 only */
>   if (dev_priv->vbt.dsi.seq_version == 2)
> @@ -328,11 +354,11 @@ static const u8 *mipi_exec_gpio(struct
> intel_dsi *intel_dsi, const u8 *data)
>   value = *data++ & 1;
>  
>   if (IS_VALLEYVIEW(dev_priv))
> - vlv_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
> + vlv_exec_gpio(dev_priv, gpio_source, gpio_number,
> value);
>   else if (IS_CHERRYVIEW(dev_priv))
> - chv_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
> + chv_exec_gpio(dev_priv, gpio_source, gpio_number,
> value);
>   else
> - DRM_DEBUG_KMS("GPIO element not supported on this
> platform\n");
> + bxt_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
>  
>   return data;
>  }
-- 
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[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: Fix CRC based atomic correctness test

[Mika Kahola]

Fixes issues on kms_plane_multiple i-g-t test found when running CI tests

v1:
 - don't use tiling for cursor plane (Ville)
 - for y/yf tiling check that the platform is at least GEN9 (Ville)

Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/kms_plane_multiple.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index bedee16..5e12be4 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -210,7 +210,7 @@ prepare_planes(data_t *data, enum pipe pipe, color_t *color,
igt_create_color_fb(data->drm_fd,
size[i], size[i],
data->plane[i]->is_cursor ? 
DRM_FORMAT_ARGB : DRM_FORMAT_XRGB,
-   tiling,
+   data->plane[i]->is_cursor ? 
LOCAL_DRM_FORMAT_MOD_NONE : tiling,
color->red, color->green, color->blue,
>fb[i]);
 
@@ -349,6 +349,7 @@ test_plane_position(data_t *data, enum pipe pipe, bool 
atomic, int max_planes,
 {
igt_output_t *output;
int connected_outs;
+   int devid = intel_get_drm_devid(data->drm_fd);
 
if (atomic)
igt_require(data->display.is_atomic);
@@ -356,6 +357,10 @@ test_plane_position(data_t *data, enum pipe pipe, bool 
atomic, int max_planes,
igt_skip_on(pipe >= data->display.n_pipes);
igt_skip_on(max_planes >= data->display.pipes[pipe].n_planes);
 
+   if ((tiling == LOCAL_I915_FORMAT_MOD_Y_TILED ||
+tiling == LOCAL_I915_FORMAT_MOD_Yf_TILED))
+   igt_require(AT_LEAST_GEN(devid, 9));
+
if (!opt.user_seed)
opt.seed = time(NULL);
 
-- 
2.7.4

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[Intel-gfx] [PATCH i-g-t v2] tests/kms_plane_lowres: Plane visibility after atomic modesets

[Mika Kahola]

Testcase for plane visibility after atomic modesets. The idea of the test
is the following:

 - draw a blue screen with high resolution
 - enable a yellow plane, visible, in lower-left corner
 - set a new lower resolution mode (1024x768) that makes plane invisible
 - check from debugfs 'i915_display_info' that the plane is invisible
 - switch back to higher resolution mode
 - check from debugfs 'i915_display_info' that the plane is visible again
 - repeat number of iterations, default 64

v2: allow test to be run on non-Intel drivers (Daniel)
moved test for plane visibility to as helper function (Daniel)
moved get_vblank() function to be part of helper functions (Daniel)
rename 'tiling' parameter as 'modifier' (Daniel)
select a mode from a list so that the plane should be invisible.
use default 1024x768 mode only as a fallback if decent mode has not
been found (Daniel)
add tiling MODE_NONE (Daniel)

Cc: Daniel Stone <dan...@fooishbar.org>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 lib/igt_kms.c|  93 +++
 lib/igt_kms.h|   9 ++
 tests/Makefile.sources   |   1 +
 tests/kms_plane_lowres.c | 394 +++
 4 files changed, 497 insertions(+)
 create mode 100644 tests/kms_plane_lowres.c

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 989704e..098b29b 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1176,6 +1176,99 @@ int kmstest_get_crtc_idx(drmModeRes *res, uint32_t 
crtc_id)
igt_assert(false);
 }
 
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pipe > 0)
+   return DRM_VBLANK_SECONDARY;
+   else
+   return 0;
+}
+
+unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe) | flags;
+   if (drmIoctl(fd, DRM_IOCTL_WAIT_VBLANK, ))
+   return 0;
+
+   return vbl.reply.sequence;
+}
+
+static int parse_resolution(struct kmstest_resolution *resolution, char *info)
+{
+   char size[32];
+   int ret;
+
+   ret = sscanf(info + 4, "%d%*c %*s %*s %*s %s%*c",
+>id, size);
+
+   if (ret != 2)
+   return -1;
+
+   ret = sscanf(size + 6, "%d%*c%d%*c",
+>width, >height);
+
+   if (ret != 2)
+   return -1;
+
+   return ret + 1;
+}
+
+static bool get_visibility(FILE *fid, struct kmstest_resolution *resolution)
+{
+   char tmp[256];
+   struct kmstest_resolution plane;
+   int ret;
+
+   while (fgets(tmp, 256, fid) != NULL) {
+   if (strstr(tmp, "type=OVL") != NULL) {
+   ret = sscanf(tmp + 12, "%d%*c %*s %*s %d%*c%d%*c",
+, , );
+
+   igt_assert_eq(ret, 3);
+
+   if (plane.width > resolution->width)
+   return false;
+   else if (plane.height > resolution->height)
+   return false;
+   else
+   return true;
+   }
+   }
+
+   return false;
+}
+
+bool kmstest_plane_visible(void)
+{
+   char tmp[256];
+   FILE *fid;
+   bool visible = false;
+   struct kmstest_resolution resolution;
+   const char *mode = "r";
+   int ret;
+
+   fid = igt_debugfs_fopen("i915_display_info", mode);
+
+   igt_assert(fid != NULL);
+
+   while (fgets(tmp, 256, fid) != NULL) {
+   if (strstr(tmp, "active=yes") != NULL) {
+   ret = parse_resolution(, tmp);
+   igt_assert_eq(ret, 3);
+   visible = get_visibility(fid, );
+   }
+   }
+
+   fclose(fid);
+
+   return visible;
+}
+
 /*
  * A small modeset API
  */
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 6422adc..4193354 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -132,6 +132,13 @@ struct kmstest_connector_config {
unsigned valid_crtc_idx_mask;
 };
 
+struct kmstest_resolution {
+   int id;
+   int width;
+   int height;
+};
+
+
 /**
  * kmstest_force_connector_state:
  * @FORCE_CONNECTOR_UNSPECIFIED: Unspecified
@@ -177,6 +184,8 @@ uint32_t kmstest_dumb_create(int fd, int width, int height, 
int bpp,
 
 void *kmstest_dumb_map_buffer(int fd, uint32_t handle, uint64_t size,
  unsigned prot);
+unsigned int kmstest_get_vblank(int fd, int pipe, unsigned int flags);
+bool kmstest_plane_visible(void);
 
 /*
  * A small modeset API
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 65e0792..c593e49 100644
---

[Intel-gfx] [PATCH CI run 3/3] drm/i915: Adding the parsing logic for the i2c element

[Mika Kahola]

New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.

v2: Add i2c_put_adapter call(Jani), rebase

v3: corrected the retry loop(Jani), rebase

v4 by Jani:
 - don't put the adapter if get fails
  - print an error message if all retries exhausted
   - use a for loop
- fix warnings for unused variables

v5 by Jani:
 - rebase on the skip i2c element patch

v6: by Jani:
 - ignore the gmbus i2c elements (Ville)

v7: by Deepak
 - Use the i2c port number which is read from ACPI
based on the resource id.

v8: by Mika
 - rebase

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: vkorjani <vikas.korj...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 78 +-
 1 file changed, 76 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a4cbe68..7fe57c2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -1004,9 +1004,83 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
 
 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 {
-   DRM_DEBUG_KMS("Skipping I2C element execution\n");
+   struct drm_i915_private *dev_priv = 
intel_dsi->base.base.dev->dev_private;
+   struct i2c_adapter *adapter;
+   int ret, i;
+   u8 reg_offset, payload_size;
+   struct i2c_msg msg;
+   struct acpi_i2c_data_node *i2c_entry = NULL;
+   u8 *transmit_buffer;
+   u8 flag, resource_id, bus_number;
+   u16 slave_add;
+   u8 count = 0;
+
+   flag = *data++;
+   resource_id = *data++;
+   bus_number = *data++;
+   slave_add = *(u16 *)(data);
+   data += 2;
+   reg_offset = *data++;
+   payload_size = *data++;
+
+   if (resource_id == 0xff || bus_number == 0xff) {
+   DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
+ resource_id, bus_number);
+   goto out;
+   }
+
+   /* Parse the list and get the required i2c bus number */
+   list_for_each_entry(i2c_entry, _priv->acpi_i2c_list,
+   head) {
+   if (count == resource_id) {
+   /* override the busnumber */
+   bus_number = i2c_entry->i2c_bus_number;
+   break;
+   }
+   count++;
+   }
+
+   /*
+* Since the i2c bus number indexing in BIOS starts from 1
+* decrementing the bus number which we are reading.
+*/
+   bus_number--;
 
-   return data + *(data + 6) + 7;
+   adapter = i2c_get_adapter(bus_number);
+   if (!adapter) {
+   DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
+   goto out;
+   }
+
+   transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+   if (!transmit_buffer)
+   goto out_put;
+
+   transmit_buffer[0] = reg_offset;
+   memcpy(_buffer[1], data, payload_size);
+
+   msg.addr = slave_add;
+   msg.flags = 0;
+   msg.len = payload_size + 1;
+   msg.buf = _buffer[0];
+
+   for (i = 0; i < 6; i++) {
+   ret = i2c_transfer(adapter, , 1);
+   if (ret == 1)
+   goto out_free;
+   else if (ret == -EAGAIN)
+   usleep_range(1000, 2500);
+   else
+   break;
+   }
+
+   DRM_ERROR("i2c transfer failed: %d\n", ret);
+out_free:
+   kfree(transmit_buffer);
+out_put:
+   i2c_put_adapter(adapter);
+out:
+   return data + payload_size;
 }
 
 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
-- 
2.7.4

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[Intel-gfx] [PATCH CI run 0/3] MIPI/DSI display support for APL

[Mika Kahola]

Test MIPI/DSI display suspend/resume cycle on Apollolake.

Jani Nikula (1):
  drm/i915/bxt: add bxt dsi gpio element support

Mika Kahola (2):
  drm/i915: Get the i2c bus number from the ACPI
  drm/i915: Adding the parsing logic for the i2c element

 drivers/gpu/drm/i915/i915_drv.c|   2 +
 drivers/gpu/drm/i915/i915_drv.h|  10 +
 drivers/gpu/drm/i915/intel_acpi.c  |  59 +++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 745 -
 4 files changed, 813 insertions(+), 3 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH CI run 2/3] drm/i915: Get the i2c bus number from the ACPI

[Mika Kahola]

Currently for executing the i2c MIPI sequence, we are
relaying on the i2c bus bunmber which is specified in the
VBT. But there are cases where different Fab versions of
the board will drive the same chip with different i2c port,
in which case the i2c bus number from the VBT cant be relied
on. To overcome this the i2c bus number is read from the
BIOS acpi table; BIOS can detect the Fab version in runtime
and will store the correct i2c bus number in the ACPI table.

v2 by Deepak:
 - Reading the i2c from the ACPI and storing them in list

v3 by Mika:
 - rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c   |  2 ++
 drivers/gpu/drm/i915/i915_drv.h   | 10 +++
 drivers/gpu/drm/i915/intel_acpi.c | 59 +++
 3 files changed, 71 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4f0e56d..563756e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -580,6 +580,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
intel_register_dsm_handler();
 
+   intel_acpi_find_i2c(dev_priv);
+
ret = vga_switcheroo_register_client(pdev, _switcheroo_ops, false);
if (ret)
goto cleanup_vga_client;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 006914c..0a6ad9f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -33,6 +33,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -1778,6 +1779,12 @@ struct intel_wm_config {
bool sprites_scaled;
 };
 
+struct acpi_i2c_data_node {
+   struct list_head head;
+   int i2c_bus_number;
+   int i2c_slave_address;
+};
+
 struct drm_i915_private {
struct drm_device drm;
 
@@ -1870,6 +1877,8 @@ struct drm_i915_private {
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
 
+   struct list_head acpi_i2c_list;
+
/* LVDS info */
bool no_aux_handshake;
 
@@ -3444,6 +3453,7 @@ static inline int intel_opregion_get_panel_type(struct 
drm_i915_private *dev)
 #ifdef CONFIG_ACPI
 extern void intel_register_dsm_handler(void);
 extern void intel_unregister_dsm_handler(void);
+extern acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv);
 #else
 static inline void intel_register_dsm_handler(void) { return; }
 static inline void intel_unregister_dsm_handler(void) { return; }
diff --git a/drivers/gpu/drm/i915/intel_acpi.c 
b/drivers/gpu/drm/i915/intel_acpi.c
index eb638a1..1b18c89 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -110,6 +110,65 @@ static void intel_dsm_platform_mux_info(void)
ACPI_FREE(pkg);
 }
 
+static int i2c_acpi_get_name(struct acpi_resource *ares, void *data)
+{
+   struct drm_i915_private *dev_priv = data;
+   struct acpi_resource_i2c_serialbus *sb;
+   unsigned int val;
+   char *resource;
+   int error;
+
+
+   if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
+   sb = >data.i2c_serial_bus;
+
+   if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
+   struct acpi_i2c_data_node *i2c_entry = NULL;
+
+   resource = sb->resource_source.string_ptr;
+   resource = strstr(resource, "I2C");
+   error = kstrtouint(resource+3, 0, );
+   if (error)
+   return error;
+
+   i2c_entry = kzalloc(sizeof(struct acpi_i2c_data_node),
+   GFP_NOWAIT);
+   i2c_entry->i2c_bus_number = val;
+   i2c_entry->i2c_slave_address = sb->slave_address;
+
+   list_add_tail(_entry->head,
+   _priv->acpi_i2c_list);
+   }
+   }
+
+   return 1;
+}
+
+acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv)
+{
+   struct pci_dev *pdev = dev_priv->drm.pdev;
+   struct list_head resource_list;
+   struct acpi_device *adev;
+   acpi_handle dhandle;
+
+   dhandle = ACPI_HANDLE(>dev);
+   if (!dhandle)
+   return false;
+
+   if (acpi_bus_get_device(dhandle, ))
+   return AE_OK;
+   if (acpi_bus_get_status(adev) || !adev->status.present)
+   return AE_OK;
+
+   INIT_LIST_HEAD(_list);
+   INIT_LIST_HEAD(_priv->acpi_i2c_list);
+   acpi_dev_get_resources(adev, _list,
+   i2c_acpi_get_name, dev_priv);
+   acpi_dev_free_resource_list(_list);
+
+   return AE_OK;
+}
+
 static bool intel_dsm_

[Intel-gfx] [PATCH CI run 1/3] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

From: Jani Nikula <jani.nik...@intel.com>

Use a table similar to vlv to check for accepted gpio indexes. For now,
add all, but this list should be trimmed down. Use managed gpio request,
which will be automatically released when the driver is detached.

Cc: Mika Kahola <mika.kah...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 667 -
 1 file changed, 666 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 9f279a3..a4cbe68 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -113,6 +114,636 @@ static struct gpio_map vlv_gpio_table[] = {
 #define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8 
+ 4)
 #define  CHV_GPIO_CFGLOCK  (1 << 31)
 
+#define BXT_HV_DDI0_DDC_SDA_PIN187
+#define BXT_HV_DDI0_DDC_SCL_PIN188
+#define BXT_HV_DDI1_DDC_SDA_PIN189
+#define BXT_HV_DDI1_DDC_SCL_PIN190
+#define BXT_DBI_SDA_PIN191
+#define BXT_DBI_SCL_PIN192
+#define BXT_PANEL0_VDDEN_PIN   193
+#define BXT_PANEL0_BKLTEN_PIN  194
+#define BXT_PANEL0_BKLTCTL_PIN 195
+#define BXT_PANEL1_VDDEN_PIN   196
+#define BXT_PANEL1_BKLTEN_PIN  197
+#define BXT_PANEL1_BKLTCTL_PIN 198
+#define BXT_DBI_CSX_PIN199
+#define BXT_DBI_RESX_PIN   200
+#define BXT_GP_INTD_DSI_TE1_PIN201
+#define BXT_GP_INTD_DSI_TE2_PIN202
+#define BXT_USB_OC0_B_PIN  203
+#define BXT_USB_OC1_B_PIN  204
+#define BXT_MEX_WAKE0_B_PIN205
+#define BXT_MEX_WAKE1_B_PIN206
+#define BXT_EMMC0_CLK_PIN  156
+#define BXT_EMMC0_D0_PIN   157
+#define BXT_EMMC0_D1_PIN   158
+#define BXT_EMMC0_D2_PIN   159
+#define BXT_EMMC0_D3_PIN   160
+#define BXT_EMMC0_D4_PIN   161
+#define BXT_EMMC0_D5_PIN   162
+#define BXT_EMMC0_D6_PIN   163
+#define BXT_EMMC0_D7_PIN   164
+#define BXT_EMMC0_CMD_PIN  165
+#define BXT_SDIO_CLK_PIN   166
+#define BXT_SDIO_D0_PIN167
+#define BXT_SDIO_D1_PIN168
+#define BXT_SDIO_D2_PIN169
+#define BXT_SDIO_D3_PIN170
+#define BXT_SDIO_CMD_PIN   171
+#define BXT_SDCARD_CLK_PIN 172
+#define BXT_SDCARD_D0_PIN  173
+#define BXT_SDCARD_D1_PIN  174
+#define BXT_SDCARD_D2_PIN  175
+#define BXT_SDCARD_D3_PIN  176
+#define BXT_SDCARD_CD_B_PIN177
+#define BXT_SDCARD_CMD_PIN 178
+#define BXT_SDCARD_LVL_CLK_FB_PIN  179
+#define BXT_SDCARD_LVL_CMD_DIR_PIN 180
+#define BXT_SDCARD_LVL_DAT_DIR_PIN 181
+#define BXT_EMMC0_STROBE_PIN   182
+#define BXT_SDIO_PWR_DOWN_B_PIN183
+#define BXT_SDCARD_PWR_DOWN_B_PIN  184
+#define BXT_SDCARD_LVL_SEL_PIN 185
+#define BXT_SDCARD_LVL_WP_PIN  186
+#define BXT_LPSS_I2C0_SDA_PIN  124
+#define BXT_LPSS_I2C0_SCL_PIN  125
+#define BXT_LPSS_I2C1_SDA_PIN  126
+#define BXT_LPSS_I2C1_SCL_PIN  127
+#define BXT_LPSS_I2C2_SDA_PIN  128
+#define BXT_LPSS_I2C2_SCL_PIN  129
+#define BXT_LPSS_I2C3_SDA_PIN  130
+#define BXT_LPSS_I2C3_SCL_PIN  131
+#define BXT_LPSS_I2C4_SDA_PIN  132
+#define BXT_LPSS_I2C4_SCL_PIN  133
+#define BXT_LPSS_I2C5_SDA_PIN  134
+#define BXT_LPSS_I2C5_SCL_PIN  135
+#define BXT_LPSS_I2C6_SDA_PIN  136
+#define BXT_LPSS_I2C6_SCL_PIN  137
+#define BXT_LPSS_I2C7_SDA_PIN  138
+#define BXT_LPSS_I2C7_SCL_PIN  139
+#define BXT_ISH_I2C0_SDA_PIN   140
+#define BXT_ISH_I2C0_SCL_PIN   141
+#define BXT_ISH_I2C1_SDA_PIN   142
+#define BXT_ISH_I2C1_SCL_PIN   143
+#define BXT_ISH_I2C2_SDA_PIN   144
+#define BXT_ISH_I2C2_SCL_PIN   145
+#define BXT_ISH_GPIO_0_PIN 146
+#define BXT_ISH_GPIO_1_PIN 147
+#define BXT_ISH_GPIO_2_PIN 148
+#define BXT_ISH_GPIO_3_PIN 149
+#define BXT_ISH_GPIO_4_PIN 150
+#define BXT_ISH_GPIO_5_PIN 151
+#define BXT_ISH_GPIO_6_PIN 152
+#define BXT_ISH_GPIO_7_PIN 153
+#define BXT_ISH_GPIO_8_PIN 154
+#define BXT_ISH_GPIO_9_PIN 155
+#define BXT_AVS_I2S1_MCLK_PIN  74
+#define BXT_AVS_I2S1_BCLK_PIN  75
+#define BXT_AVS_I2S1_WS_SYNC_PIN   76
+#define BXT_AVS_I2S1_SDI_PIN   77
+#define BXT_AVS_I2S1_SDO_P

[Intel-gfx] [PATCH i-g-t] tests/kms_plane_lowres: Plane visibility after atomic modesets

[Mika Kahola]

Testcase for plane visibility after atomic modesets. The idea of the test
is the following:

 - draw a blue screen with high resolution
 - enable a yellow plane, visible, in lower-left corner
 - set a new lower resolution mode (1024x768) that makes plane invisible
 - check from debugfs 'i915_display_info' that the plane is invisible
 - switch back to higher resolution mode
 - check from debugfs 'i915_display_info' that the plane is visible again
 - repeat number of iterations, default 64

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources   |   1 +
 tests/kms_plane_lowres.c | 424 +++
 2 files changed, 425 insertions(+)
 create mode 100644 tests/kms_plane_lowres.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index debe3df..9ebdc44 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -109,6 +109,7 @@ TESTS_progs_M = \
kms_pipe_crc_basic \
kms_plane \
kms_plane_multiple \
+   kms_plane_lowres \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
new file mode 100644
index 000..6735a3b
--- /dev/null
+++ b/tests/kms_plane_lowres.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with a plane by switching 
between high and low resolutions");
+
+#define MAX_CRCS  1
+#define SIZE256
+#define LOOP_FOREVER -1
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[2];
+   struct igt_fb fb[2];
+} data_t;
+
+typedef struct {
+   int id;
+   int width;
+   int height;
+} res_t;
+
+/* Command line parameters. */
+struct {
+   int iterations;
+} opt = {
+   .iterations = 64,
+};
+
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pipe > 0)
+   return DRM_VBLANK_SECONDARY;
+   else
+   return 0;
+}
+
+static unsigned int get_vblank(int fd, int pipe, unsigned int flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe) | flags;
+   if (drmIoctl(fd, DRM_IOCTL_WAIT_VBLANK, ))
+   return 0;
+
+   return vbl.reply.sequence;
+}
+
+static int parse_resolution(res_t *resolution, char *info)
+{
+   char size[32];
+   int ret;
+
+   ret = sscanf(info + 4, "%d%*c %*s %*s %*s %s%*c",
+>id, size);
+
+   if (ret != 2)
+   return -1;
+
+   ret = sscanf(size + 6, "%d%*c%d%*c",
+>width, >height);
+
+   if (ret != 2)
+   return -1;
+
+   return ret + 1;
+}
+
+static bool get_visibility(FILE *fid, res_t *resolution)
+{
+   char tmp[256];
+   res_t plane;
+   int ret;
+
+   while (fgets(tmp, 256, fid) != NULL) {
+   if (strstr(tmp, "type=OVL") != NULL) {
+   ret = sscanf(tmp + 12, "%d%*c %*s %*s %d%*c%d%*c",
+, , );
+
+   igt_assert_eq(ret, 3);
+
+   if (plane.width > resolution->width)
+   return false;
+   else if (plane.height > resolution->height)
+   return false;
+   else
+   return true;
+   }
+   }
+
+   

Re: [Intel-gfx] [PATCH v5 3/3] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

Tested-by: Mika Kahola <mika.kah...@intel.com>

On Tue, 2016-04-26 at 13:27 +0300, Jani Nikula wrote:
> Request the GPIO by index through the consumer API. For now, use a
> quick
> hack to store the already requested ones, simply because I have no
> idea
> whether this actually works or not, and I have no way to test it.
> 
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28
> +++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f122484bedfc..aefcc19968e0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -300,6 +301,31 @@ static void chv_exec_gpio(struct
> drm_i915_private *dev_priv,
>   mutex_unlock(_priv->sb_lock);
>  }
>  
> +static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> +   u8 gpio_source, u8 gpio_index, bool value)
> +{
> + /* XXX: this table is a quick ugly hack. */
> + static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
> + struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
> +
> + if (!gpio_desc) {
> + gpio_desc = devm_gpiod_get_index(dev_priv->dev->dev,
> +  NULL, gpio_index,
> +  value ?
> GPIOD_OUT_LOW :
> +  GPIOD_OUT_HIGH);
> +
> + if (IS_ERR_OR_NULL(gpio_desc)) {
> + DRM_ERROR("GPIO index %u request failed
> (%ld)\n",
> +   gpio_index, PTR_ERR(gpio_desc));
> + return;
> + }
> +
> + bxt_gpio_table[gpio_index] = gpio_desc;
> + }
> +
> + gpiod_set_value(gpio_desc, value);
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const
> u8 *data)
>  {
>   struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -326,7 +352,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
> *intel_dsi, const u8 *data)
>   else if (IS_CHERRYVIEW(dev_priv))
>   chv_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
>   else
> - DRM_DEBUG_KMS("GPIO element not supported on this
> platform\n");
> + bxt_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
>  
>   return data;
>  }
-- 
Mika Kahola - Intel OTC

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t v7] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for several iterations to maximize coverage

v7: Unify reference crc grabbing for atomic and legacy tests (Maarten)

v6: Rename test_planes() to prepare_planes() (Maarten)
When grabbing reference crc, keep framebuffer and crc enabled for
atomic mode setting. (Maarten)
Fix crc collection for legacy modesetting (Maarten)

v5: Remove limit for max number of iterations and add possibility to
loop forever (Daniel)
Remove IN_RANGE() macro (Maarten)
Remove log file and show random number seed on screen instead (Maarten)
Split legacy and atomic plane tests on own functions (Maarten)
remove test_atomic() function and pass test mode info as
parameter (Maarten)
Use bigger rectangle size (256x256) for non-cursor planes and
smaller (128x128) size for cursor plane (Maarten)

v4: For atomic test enable crc capturing before entering into a
iteration loop. After each iteration, check that page flip
didn't take no more than 1 vblank, fetch all crc's and check
the values.

Introduce new command line parameter for the number of iterations.
The test run from 1 to 256 iterations.

v3: Cleanup by removing separate plane array
For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
Grab crc by using igt_pipe_crc_get_crc instead of igt_pipe_crc_collect_crc
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 494 +
 2 files changed, 495 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d081c3..ffd59c1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..bedee16
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define MAX_CRCS  1
+#define SIZE_PLANE  256
+#define SIZE_CURSOR 128
+#define LOOP_FOREVER -1
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[IGT_MAX_PLANES];
+   struct igt_fb fb[IGT_MAX_PLANES];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   int iterations;
+   bool user_seed;
+   int seed;
+} opt = {
+   .iterations = 64,
+   .user_seed = false,
+   .seed = 1,
+};
+
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   

Re: [Intel-gfx] [PATCH i-g-t v6] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

On Tue, 2016-11-08 at 14:14 +0100, Maarten Lankhorst wrote:
> Op 08-11-16 om 12:54 schreef Mika Kahola:
> > 
> > This is a testcase with multiple planes. The idea here is the
> > following
> > 
> >  - draw a uniform frame with blue color
> >  - grab crc for reference
> >  - put planes randomly on top with the same blue color
> >  - punch holes with black color into the primary framebuffer
> >  - ideally the planes should cover these holes so that the output
> > is the
> >    identical to reference crc
> >  - composite all with one ioctl call
> >  - grab crc and verify that the reference crc is equal
> >  - repeat this for several iterations to maximize coverage
> > 
> > v6: Rename test_planes() to prepare_planes() (Maarten)
> > When grabbing reference crc, keep framebuffer and crc enabled
> > for
> > atomic mode setting. (Maarten)
> > Fix crc collection for legacy modesetting (Maarten)
> > 
> > v5: Remove limit for max number of iterations and add possibility
> > to
> > loop forever (Daniel)
> > Remove IN_RANGE() macro (Maarten)
> > Remove log file and show random number seed on screen instead
> > (Maarten)
> > Split legacy and atomic plane tests on own functions (Maarten)
> > remove test_atomic() function and pass test mode info as
> > parameter (Maarten)
> > Use bigger rectangle size (256x256) for non-cursor planes and
> > smaller (128x128) size for cursor plane (Maarten)
> > 
> > v4: For atomic test enable crc capturing before entering into a
> > iteration loop. After each iteration, check that page flip
> > didn't take no more than 1 vblank, fetch all crc's and check
> > the values.
> > 
> > Introduce new command line parameter for the number of
> > iterations.
> > The test run from 1 to 256 iterations.
> > 
> > v3: Cleanup by removing separate plane array
> > For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
> > Grab crc by using igt_pipe_crc_get_crc instead of
> > igt_pipe_crc_collect_crc
> > Rename nplanes variable to max_planes
> > To optimize test execution, run iterations after the modeset
> > 
> > v2: Keep a logfile on random number seeds per subtest that are not
> > skipped
> > due to unmet test requirements
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/kms_plane_multiple.c | 501
> > +
> >  2 files changed, 502 insertions(+)
> >  create mode 100644 tests/kms_plane_multiple.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d081c3..ffd59c1 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> >     kms_pipe_color \
> >     kms_pipe_crc_basic \
> >     kms_plane \
> > +   kms_plane_multiple \
> >     kms_properties \
> >     kms_psr_sink_crc \
> >     kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..f316488
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,501 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TO

[Intel-gfx] [PATCH i-g-t v6] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for several iterations to maximize coverage

v6: Rename test_planes() to prepare_planes() (Maarten)
When grabbing reference crc, keep framebuffer and crc enabled for
atomic mode setting. (Maarten)
Fix crc collection for legacy modesetting (Maarten)

v5: Remove limit for max number of iterations and add possibility to
loop forever (Daniel)
Remove IN_RANGE() macro (Maarten)
Remove log file and show random number seed on screen instead (Maarten)
Split legacy and atomic plane tests on own functions (Maarten)
remove test_atomic() function and pass test mode info as
parameter (Maarten)
Use bigger rectangle size (256x256) for non-cursor planes and
smaller (128x128) size for cursor plane (Maarten)

v4: For atomic test enable crc capturing before entering into a
iteration loop. After each iteration, check that page flip
didn't take no more than 1 vblank, fetch all crc's and check
the values.

Introduce new command line parameter for the number of iterations.
The test run from 1 to 256 iterations.

v3: Cleanup by removing separate plane array
For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
Grab crc by using igt_pipe_crc_get_crc instead of igt_pipe_crc_collect_crc
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 501 +
 2 files changed, 502 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d081c3..ffd59c1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..f316488
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define MAX_CRCS  1
+#define SIZE_PLANE  256
+#define SIZE_CURSOR 128
+#define LOOP_FOREVER -1
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[IGT_MAX_PLANES];
+   struct igt_fb fb[IGT_MAX_PLANES];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   int iterations;
+   bool user_seed;
+   int seed;
+} opt = {
+   .iterations = 64,
+   .user_seed = false,
+   .seed = 1,
+};
+
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pi

Re: [Intel-gfx] [PATCH i-g-t v5] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

Thanks for the review. 

On Mon, 2016-11-07 at 14:04 +0100, Maarten Lankhorst wrote:
> Op 02-11-16 om 10:32 schreef Mika Kahola:
> > 
> > This is a testcase with multiple planes. The idea here is the
> > following
> > 
> >  - draw a uniform frame with blue color
> >  - grab crc for reference
> >  - put planes randomly on top with the same blue color
> >  - punch holes with black color into the primary framebuffer
> >  - ideally the planes should cover these holes so that the output
> > is the
> >    identical to reference crc
> >  - composite all with one ioctl call
> >  - grab crc and verify that the reference crc is equal
> >  - repeat this for dozen iterations to maximize coverage
> > 
> > v5: Remove limit for max number of iterations and add possibility
> > to
> > loop forever (Daniel)
> > Remove IN_RANGE() macro (Maarten)
> > Remove log file and show random number seed on screen instead
> > (Maarten)
> > Split legacy and atomic plane tests on own functions (Maarten)
> > remove test_atomic() function and pass test mode info as
> > parameter (Maarten)
> > Use bigger rectangle size (256x256) for non-cursor planes and
> > smaller (128x128) size for cursor plane (Maarten)
> > 
> > v4: For atomic test enable crc capturing before entering into a
> > iteration loop. After each iteration, check that page flip
> > didn't take no more than 1 vblank, fetch all crc's and check
> > the values.
> > 
> > Introduce new command line parameter for the number of
> > iterations.
> > The test run from 1 to 256 iterations.
> > 
> > v3: Cleanup by removing separate plane array
> > For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
> > Grab crc by using igt_pipe_crc_get_crc instead of
> > igt_pipe_crc_collect_crc
> > Rename nplanes variable to max_planes
> > To optimize test execution, run iterations after the modeset
> > 
> > v2: Keep a logfile on random number seeds per subtest that are not
> > skipped
> > due to unmet test requirements
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/kms_plane_multiple.c | 506
> > +
> >  2 files changed, 507 insertions(+)
> >  create mode 100644 tests/kms_plane_multiple.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d081c3..ffd59c1 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> >     kms_pipe_color \
> >     kms_pipe_crc_basic \
> >     kms_plane \
> > +   kms_plane_multiple \
> >     kms_properties \
> >     kms_psr_sink_crc \
> >     kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..d13ce1c
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,506 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "igt.h"
> >

[Intel-gfx] [PATCH i-g-t v5] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for dozen iterations to maximize coverage

v5: Remove limit for max number of iterations and add possibility to
loop forever (Daniel)
Remove IN_RANGE() macro (Maarten)
Remove log file and show random number seed on screen instead (Maarten)
Split legacy and atomic plane tests on own functions (Maarten)
remove test_atomic() function and pass test mode info as
parameter (Maarten)
Use bigger rectangle size (256x256) for non-cursor planes and
smaller (128x128) size for cursor plane (Maarten)

v4: For atomic test enable crc capturing before entering into a
iteration loop. After each iteration, check that page flip
didn't take no more than 1 vblank, fetch all crc's and check
the values.

Introduce new command line parameter for the number of iterations.
The test run from 1 to 256 iterations.

v3: Cleanup by removing separate plane array
For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
Grab crc by using igt_pipe_crc_get_crc instead of igt_pipe_crc_collect_crc
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 506 +
 2 files changed, 507 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d081c3..ffd59c1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..d13ce1c
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define MAX_CRCS  1
+#define SIZE_PLANE  256
+#define SIZE_CURSOR 128
+#define LOOP_FOREVER -1
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[IGT_MAX_PLANES];
+   struct igt_fb fb[IGT_MAX_PLANES];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   int iterations;
+   bool user_seed;
+   int seed;
+} opt = {
+   .iterations = 64,
+   .user_seed = false,
+   .seed = 1,
+};
+
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pipe > 0)
+   return DRM_VBLANK_SECONDARY;
+   else
+   return 0;
+}
+
+static unsigned int get_vblank(int fd, int pipe, unsigned int flags)
+{
+   union drm_wait_vblank vbl;
+
+   mems

Re: [Intel-gfx] [PATCH i-g-t v4] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

On Tue, 2016-11-01 at 09:25 +0100, Maarten Lankhorst wrote:
> Op 20-10-16 om 11:27 schreef Mika Kahola:
> > 
> > This is a testcase with multiple planes. The idea here is the
> > following
> > 
> >  - draw a uniform frame with blue color
> >  - grab crc for reference
> >  - put planes randomly on top with the same blue color
> >  - punch holes with black color into the primary framebuffer
> >  - ideally the planes should cover these holes so that the output
> > is the
> >    identical to reference crc
> >  - composite all with one ioctl call
> >  - grab crc and verify that the reference crc is equal
> >  - repeat this for dozen iterations to maximize coverage
> > 
> > v4: For atomic test enable crc capturing before entering into a
> > iteration loop. After each iteration, check that page flip
> > didn't take no more than 1 vblank, fetch all crc's and check
> > the values.
> > 
> > Introduce new command line parameter for the number of
> > iterations.
> > The test run from 1 to 256 iterations.
> > 
> > v3: Cleanup by removing separate plane array
> > For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
> > Grab crc by using igt_pipe_crc_get_crc instead of
> > igt_pipe_crc_collect_crc
> > Rename nplanes variable to max_planes
> > To optimize test execution, run iterations after the modeset
> > 
> > v2: Keep a logfile on random number seeds per subtest that are not
> > skipped
> > due to unmet test requirements
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/kms_plane_multiple.c | 475
> > +
> >  2 files changed, 476 insertions(+)
> >  create mode 100644 tests/kms_plane_multiple.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d081c3..ffd59c1 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> >     kms_pipe_color \
> >     kms_pipe_crc_basic \
> >     kms_plane \
> > +   kms_plane_multiple \
> >     kms_properties \
> >     kms_psr_sink_crc \
> >     kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..a18cdff
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,475 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "igt.h"
> > +#include "drmtest.h"
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple
> > planes ");
> > +
> > +#define MAX_CRCS 1
> > +#define SIZE 128
> > +
> > +#define IN_RANGE(X, MIN, MAX) ((X) < (MIN) || (X) > (MAX) ? 16 :
> > X)
> 16 or MAX? anyway it's only used in one place, so might as well
> remove the macro.
> > 
> > +typedef struct {
> > +   float red;
> > +   float green;
> > +   float blue;

Re: [Intel-gfx] [PATCH i-g-t v4] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

On Mon, 2016-10-24 at 10:28 +0200, Daniel Vetter wrote:
> On Thu, Oct 20, 2016 at 12:27:23PM +0300, Mika Kahola wrote:
> > 
> > This is a testcase with multiple planes. The idea here is the
> > following
> > 
> >  - draw a uniform frame with blue color
> >  - grab crc for reference
> >  - put planes randomly on top with the same blue color
> >  - punch holes with black color into the primary framebuffer
> >  - ideally the planes should cover these holes so that the output
> > is the
> >    identical to reference crc
> >  - composite all with one ioctl call
> >  - grab crc and verify that the reference crc is equal
> >  - repeat this for dozen iterations to maximize coverage
> > 
> > v4: For atomic test enable crc capturing before entering into a
> > iteration loop. After each iteration, check that page flip
> > didn't take no more than 1 vblank, fetch all crc's and check
> > the values.
> > 
> > Introduce new command line parameter for the number of
> > iterations.
> > The test run from 1 to 256 iterations.
> This seems real low. Screens run at usuall 50-60Hz, which means you
> just
> allow for a few seconds. I'd say for a normal validation run timing
> it to
> be 1 second (for each subtest) is a reasonable start.
> 
> But for the knob we probably want to make this virtually unlimited,
> e.g.
> -1 == never stop. This would be useful for chasing hard-to-reproduct
> underruns and errors: Run testcase with unlimited iterations, it will
> die
> as soon as the first error shows up. Then try with next hack/debug
> trick
> until the test survives for hours and it all looks good ;-)
> 
I was thinking this unlimited option too but then I thought it would be
safer if the test would stop at some point. Anyway, I can add this
option to the test.
 

> For the testcode itself I think it'd be good if at least Ville and
> Maarten
> review it, since this will be the groundwork for adding all kinds of
> atomic tests (rotation, yuv, scaling, anything else really).
> -Daniel
> 
> > 
> > 
> > v3: Cleanup by removing separate plane array
> > For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
> > Grab crc by using igt_pipe_crc_get_crc instead of
> > igt_pipe_crc_collect_crc
> > Rename nplanes variable to max_planes
> > To optimize test execution, run iterations after the modeset
> > 
> > v2: Keep a logfile on random number seeds per subtest that are not
> > skipped
> > due to unmet test requirements
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/kms_plane_multiple.c | 475
> > +
> >  2 files changed, 476 insertions(+)
> >  create mode 100644 tests/kms_plane_multiple.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d081c3..ffd59c1 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> >     kms_pipe_color \
> >     kms_pipe_crc_basic \
> >     kms_plane \
> > +   kms_plane_multiple \
> >     kms_properties \
> >     kms_psr_sink_crc \
> >     kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..a18cdff
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,475 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT S

[Intel-gfx] [PATCH i-g-t v4] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for dozen iterations to maximize coverage

v4: For atomic test enable crc capturing before entering into a
iteration loop. After each iteration, check that page flip
didn't take no more than 1 vblank, fetch all crc's and check
the values.

Introduce new command line parameter for the number of iterations.
The test run from 1 to 256 iterations.

v3: Cleanup by removing separate plane array
For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
Grab crc by using igt_pipe_crc_get_crc instead of igt_pipe_crc_collect_crc
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 475 +
 2 files changed, 476 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d081c3..ffd59c1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..a18cdff
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define MAX_CRCS 1
+#define SIZE 128
+
+#define IN_RANGE(X, MIN, MAX) ((X) < (MIN) || (X) > (MAX) ? 16 : X)
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[IGT_MAX_PLANES];
+   struct igt_fb fb[IGT_MAX_PLANES];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   unsigned iterations;
+   bool user_seed;
+   int seed;
+   bool user_logfile;
+   char logfile[SIZE];
+} opt = {
+   .iterations = 16,
+   .user_seed = false,
+   .seed = 1,
+   .user_logfile = false,
+   .logfile = "kms_plane_multiple.log",
+};
+
+static inline uint32_t pipe_select(int pipe)
+{
+   if (pipe > 1)
+   return pipe << DRM_VBLANK_HIGH_CRTC_SHIFT;
+   else if (pipe > 0)
+   return DRM_VBLANK_SECONDARY;
+   else
+   return 0;
+}
+
+static unsigned get_vblank(int fd, int pipe, unsigned flags)
+{
+   union drm_wait_vblank vbl;
+
+   memset(, 0, sizeof(vbl));
+   vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe) | flags;
+   if (drmIoctl(fd, DRM_IOCTL_WAIT_VBLANK, ))
+   return 0;
+
+   return vbl.reply.sequence;
+}
+
+static int logwrite(const char *testname)
+{
+   time_t curr_time;
+   FILE *fid;
+   char *time_str;
+
+   f

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

On Mon, 2016-10-17 at 16:30 +0200, Daniel Vetter wrote:
> On Mon, Oct 17, 2016 at 02:28:37PM +0300, Mika Kahola wrote:
> > 
> > +   for (int i = 0; i < iterations; i++) {
> > +   igt_info("%d/%d: Testing connector %s using pipe
> > %s with %d planes\n",
> > +    i+1, iterations, igt_output_name(output),
> > +    kmstest_pipe_name(pipe), max_planes);
> > +
> > +   test_init(data, pipe);
> > +
> > +   test_grab_crc(data, output, pipe, , tiling,
> > +     _crc);
> > +
> > +   test_planes(data, pipe, , tiling, max_planes,
> > output);
> > +
> > +   if (test_atomic) {
> > +   igt_display_commit_atomic(>display,
> > +     DRM_MODE_PAGE_FL
> > IP_EVENT,
> > +     >display);
> > +   } else
> > +   igt_display_commit2(>display,
> > COMMIT_LEGACY);
> > +
> > +   igt_pipe_crc_start(data->pipe_crc);
> > +   n = igt_pipe_crc_get_crcs(data->pipe_crc, 1,
> > );
> > +   igt_assert_eq(n, 1);
> > +   igt_pipe_crc_stop(data->pipe_crc);
> Comment on testing method here: With atomic we don't just require
> that the
> result looks good at the end, but also that _every_ frame is perfect.
> That
> means you need a slightly different test sequence:
> 
> 1. Enable crc capture.
> 
> 2. Create a new atomic state (randomized, whatever) which should in
> the
> end still result in the same screen contents using the punchout box
> trick.
> This depends upon the exact subtest.
> 
> 3. Commit the state from step 2.
> 
> 4. Wait to make sure the atomic commit has completed. If you do an
> async
> commit, that means waiting for the flip_event to get signalled
> (didn't see
> code for that anywhere).
> 
> 5. Fetch all the crc values (if there's not a bug in your code or in
> the
> kernel it should be just 1) and make sure they are _all_ the right
> value.
> Your code here only grabs 1 crc after the atomic commit completed,
> which
> means if there's tearing or underruns you'll miss them. Which means
> it
> won't actually validate the crucial feature for which we've created
> atomic!
That's true, I missed that one. I'll make modification on the test
sequence and spin another round of this test.

Cheers,
Mika

> 
> 6. Go back to 2.
> 
> 7. After enough loops, stop crc capturing.
> 
> Note that this is the loop for ALLOW_MODESET==false atomic commits,
> i.e.
> where every atomic commit should take at most 1 vblank interval. If
> any of
> the commits take longer than that, there's a bug in either the kernel
> or
> your testcase. Note that crc_start alone has a few vblank waits (due
> to
> crc bugs on some platforms) which will break this.
> 
> Cheers, Daniel
> 
> > 
> > +
> > +   igt_assert_crc_equal(_crc, crc);
> > +
> > +   test_fini(data, output, max_planes);
> > +   }
> > +}
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for dozen iterations to maximize coverage

v3: Cleanup by removing separate plane array
For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
Grab crc by using igt_pipe_crc_get_crc instead of igt_pipe_crc_collect_crc
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 423 +
 2 files changed, 424 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d081c3..ffd59c1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..0cb7552
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define SIZE 128
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *plane[IGT_MAX_PLANES];
+   struct igt_fb fb[IGT_MAX_PLANES];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   bool user_seed;
+   int seed;
+   bool user_logfile;
+   char logfile[SIZE];
+} opt = {
+   .user_seed = false,
+   .seed = 1,
+   .user_logfile = false,
+   .logfile = "kms_plane_multiple.log",
+};
+
+
+static int logwrite(const char *testname)
+{
+   time_t curr_time;
+   FILE *fid;
+   char *time_str;
+
+   fid = fopen(opt.logfile, "a");
+
+   if (fid == NULL) {
+   igt_debug("Could not open file %s\n", opt.logfile);
+   return -1;
+   }
+
+   curr_time = time(NULL);
+
+   time_str = ctime(_time);
+   time_str[strlen(time_str)-1] = '\0';
+
+   fprintf(fid, "%s: kms_plane_multiple --run-subtest %s --seed %d\n",
+   time_str, testname, opt.seed);
+
+   fclose(fid);
+
+   return 0;
+}
+
+/*
+ * Common code across all tests, acting on data_t
+ */
+static void test_init(data_t *data, enum pipe pipe)
+{
+   data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+}
+
+static void test_fini(data_t *data, igt_output_t *output, int max_planes)
+{
+   igt_plane_set_fb(data->plane[IGT_PLANE_PRIMARY], NULL);
+
+   for (int i = IGT_PLANE_2; i <= max_planes; i++)
+   igt_plane_set_fb(data->plane[i], NULL);
+
+   /* reset the constraint on the pipe */
+   igt_output_set_pipe(output, PIPE_ANY);
+
+   igt_pipe_crc_

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

On Wed, 2016-10-12 at 14:54 +0200, Maarten Lankhorst wrote:
> Op 07-10-16 om 13:45 schreef Mika Kahola:
> > 
> > This is a testcase with multiple planes. The idea here is the
> > following
> > 
> >  - draw a uniform frame with blue color
> >  - grab crc for reference
> >  - put planes randomly on top with the same blue color
> >  - punch holes with black color into the primary framebuffer
> >  - ideally the planes should cover these holes so that the output
> > is the
> >    identical to reference crc
> >  - composite all with one ioctl call
> >  - grab crc and verify that the reference crc is equal
> >  - repeat this for dozen iterations to maximize coverage
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  tests/Makefile.sources |   1 +
> >  tests/kms_plane_multiple.c | 332
> > +
> >  2 files changed, 333 insertions(+)
> >  create mode 100644 tests/kms_plane_multiple.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 598ec6f..aed0f3a 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> >     kms_pipe_color \
> >     kms_pipe_crc_basic \
> >     kms_plane \
> > +   kms_plane_multiple \
> >     kms_properties \
> >     kms_psr_sink_crc \
> >     kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..153d6d1
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,332 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "igt.h"
> > +#include "drmtest.h"
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define SIZE 128
> > +
> > +typedef struct {
> > +   float red;
> > +   float green;
> > +   float blue;
> > +} color_t;
> > +
> > +typedef struct {
> > +   int drm_fd;
> > +   igt_display_t display;
> > +   igt_pipe_crc_t *pipe_crc;
> > +   igt_plane_t *primary;
> > +   igt_plane_t *sprite[IGT_MAX_PLANES-1];
> > +   struct igt_fb primary_fb;
> > +   struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
> Single array, instead of primary/sprite separate? See also below for
> index change..
Indeed, it does look cleaner that way.
> > 
> > +} data_t;
> > +
> > +typedef struct {
> > +   data_t *data;
> > +   igt_crc_t reference_crc;
> > +} test_position_t;
> > +
> > +/*
> > + * Common code across all tests, acting on data_t
> > + */
> > +static void test_init(data_t *data, enum pipe pipe)
> > +{
> > +   data->pipe_crc = igt_pipe_crc_new(pipe,
> > INTEL_PIPE_CRC_SOURCE_AUTO);
> > +}
> > +
> > +static void test_fini(data_t *data, igt_output_t *output, int
> > nplanes)
> > +{
> > +   igt_plane_set_fb(data->primary, NULL);
> > +
> > +   for (int i = 0; i < nplanes; i++)
> > +   igt_plane_set_fb(data->sprite[i], NULL);
> > +
&g

[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for dozen iterations to maximize coverage

v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/kms_plane_multiple.c | 421 +
 1 file changed, 421 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..cafd409
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
+
+#define SIZE 128
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *primary;
+   igt_plane_t *sprite[IGT_MAX_PLANES-1];
+   struct igt_fb primary_fb;
+   struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/* Command line parameters. */
+struct {
+   bool user_seed;
+   int seed;
+   bool user_logfile;
+   char logfile[SIZE];
+} opt = {
+   .user_seed = false,
+   .seed = 1,
+   .user_logfile = false,
+   .logfile = "kms_plane_multiple.log",
+};
+
+
+static int logwrite(const char *testname)
+{
+   time_t curr_time;
+   FILE *fid;
+   char *time_str;
+
+   fid = fopen(opt.logfile, "a");
+
+   if (fid == NULL) {
+   igt_debug("Could not open file %s\n", opt.logfile);
+   return -1;
+   }
+
+   curr_time = time(NULL);
+
+   time_str = ctime(_time);
+   time_str[strlen(time_str)-1] = '\0';
+
+   fprintf(fid, "%s: kms_plane_multiple --run-subtest %s --seed %d\n",
+   time_str, testname, opt.seed);
+
+   fclose(fid);
+
+   return 0;
+}
+
+/*
+ * Common code across all tests, acting on data_t
+ */
+static void test_init(data_t *data, enum pipe pipe)
+{
+   data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+}
+
+static void test_fini(data_t *data, igt_output_t *output, int nplanes)
+{
+   igt_plane_set_fb(data->primary, NULL);
+
+   for (int i = 0; i < nplanes; i++)
+   igt_plane_set_fb(data->sprite[i], NULL);
+
+   /* reset the constraint on the pipe */
+   igt_output_set_pipe(output, PIPE_ANY);
+
+   igt_pipe_crc_free(data->pipe_crc);
+}
+
+static void
+test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
+ color_t *color, uint64_t tiling, int commit,
+ igt_crc_t *crc /* out */)
+{
+   struct igt_fb fb;
+   drmModeModeInfo *mode;
+   igt_plane_t *primary;
+
+   igt_output_set_pipe(output, pipe);
+
+   primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+
+   mode = igt_output_get_mode(output);
+
+   igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+   DRM_FORMAT_XRGB,

[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Mika Kahola]

This is a testcase with multiple planes. The idea here is the following

 - draw a uniform frame with blue color
 - grab crc for reference
 - put planes randomly on top with the same blue color
 - punch holes with black color into the primary framebuffer
 - ideally the planes should cover these holes so that the output is the
   identical to reference crc
 - composite all with one ioctl call
 - grab crc and verify that the reference crc is equal
 - repeat this for dozen iterations to maximize coverage

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_plane_multiple.c | 332 +
 2 files changed, 333 insertions(+)
 create mode 100644 tests/kms_plane_multiple.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 598ec6f..aed0f3a 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -105,6 +105,7 @@ TESTS_progs_M = \
kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
+   kms_plane_multiple \
kms_properties \
kms_psr_sink_crc \
kms_render \
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
new file mode 100644
index 000..153d6d1
--- /dev/null
+++ b/tests/kms_plane_multiple.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIZE 128
+
+typedef struct {
+   float red;
+   float green;
+   float blue;
+} color_t;
+
+typedef struct {
+   int drm_fd;
+   igt_display_t display;
+   igt_pipe_crc_t *pipe_crc;
+   igt_plane_t *primary;
+   igt_plane_t *sprite[IGT_MAX_PLANES-1];
+   struct igt_fb primary_fb;
+   struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
+} data_t;
+
+typedef struct {
+   data_t *data;
+   igt_crc_t reference_crc;
+} test_position_t;
+
+/*
+ * Common code across all tests, acting on data_t
+ */
+static void test_init(data_t *data, enum pipe pipe)
+{
+   data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+}
+
+static void test_fini(data_t *data, igt_output_t *output, int nplanes)
+{
+   igt_plane_set_fb(data->primary, NULL);
+
+   for (int i = 0; i < nplanes; i++)
+   igt_plane_set_fb(data->sprite[i], NULL);
+
+   /* reset the constraint on the pipe */
+   igt_output_set_pipe(output, PIPE_ANY);
+
+   igt_pipe_crc_free(data->pipe_crc);
+}
+
+static void
+test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
+ color_t *color, uint64_t tiling, int commit,
+ igt_crc_t *crc /* out */)
+{
+   struct igt_fb fb;
+   drmModeModeInfo *mode;
+   igt_plane_t *primary;
+
+   igt_output_set_pipe(output, pipe);
+
+   primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+
+   mode = igt_output_get_mode(output);
+
+   igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+   DRM_FORMAT_XRGB,
+   LOCAL_DRM_FORMAT_MOD_NONE,
+   color->red, color->green, color->blue,
+   );
+
+   igt_plane_set_fb(primary, );
+
+   igt_display_commit2(>display, commit);
+
+   igt_wait_for_vblank(data->drm_fd, pipe);
+
+   igt_pipe_crc_collect_crc(data->pipe_crc, crc);
+
+   igt_plane_set_fb(primary, NULL);
+
+   igt_display_commit2(>display, commit);
+
+   igt_remove_fb(data->drm_fd, );
+}
+
+/*
+ * Multiple plane position test.
+ *   - We start by grabbing a reference CRC of a full blue fb being scanned
+ * out on the primary plane
+ *   - Then we scannout number of planes:
+ *  * the primary p

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions

[Mika Kahola]

 int gen9_init_workarounds(struct
> intel_engine_cs *engine)
>   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>     GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>  
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>   WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>     GEN9_DG_MIRROR_FIX_ENABLE);
>  
> - /*
> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
> */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
>   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
>     GEN9_RHWO_OPTIMIZATION_DISABLE);
>   /*
> @@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct
> intel_engine_cs *engine)
>      GEN8_LQSC_RO_PERF_DIS);
>  
>   /* WaEnableGapsTsvCreditFix:skl */
> - if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
This seems to be related to revision C0 rather than A0 or B0. Maybe we
should move this part to the patch that handles C0 revision? 

> - I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL)
> |
> -    GEN9_GAPS_TSV_CREDIT_DISA
> BLE));
> - }
> -
> - /* WaDisablePowerCompilerClockGating:skl */
> - if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
> - WA_SET_BIT_MASKED(HIZ_CHICKEN,
> -   BDW_HIZ_POWER_COMPILER_CLOCK_GATIN
> G_DISABLE);
> + I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> +    GEN9_GAPS_TSV_CREDIT_DISABLE));
>  
>   /* WaBarrierPerformanceFixDisable:skl */
>   if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
-- 
Mika Kahola - Intel OTC

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[Intel-gfx] [PATCH] drm: Fix DisplayPort branch device ID

[Mika Kahola]

Fix missing parameter description for DisplayPort branch device ID.
This fixes warning of "No description found for parameter 'id[6]'" when
creating documentation by 'make htmldocs'.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index a536514..0ad20f1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -517,6 +517,7 @@ EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 /**
  * drm_dp_downstream_id() - identify branch device
  * @aux: DisplayPort AUX channel
+ * @id: DisplayPort branch device id
  *
  * Returns branch device id on success or NULL on failure
  */
-- 
2.7.4

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Re: [Intel-gfx] [drm-intel:for-linux-next 6/12] htmldocs: drivers/gpu/drm/drm_dp_helper.c:523: warning: No description found for parameter 'id[6]'

[Mika Kahola]

I'll fix this.

Cheers,
Mika

On Fri, 2016-09-16 at 10:53 +0300, Jani Nikula wrote:
> Mika, please send in the documentation fix.
> 
> BR,
> Jani.
> 
> 
> On Fri, 16 Sep 2016, kbuild test robot 
> wrote:
> > 
> > tree:   git://anongit.freedesktop.org/drm-intel for-linux-next
> > head:   80209e5f2c42c491ec5f4a63705b4377b407587c
> > commit: 266d783baaf5f34a5bea3b56489f091451a89767 [6/12] drm: Read
> > DP branch device id
> > reproduce: make htmldocs
> > 
> > All warnings (new ones prefixed by >>):
> > 
> >    drivers/gpu/drm/drm_modes.c:693: warning: No description found
> > for parameter 'bus_flags'
> > > 
> > > > 
> > > > drivers/gpu/drm/drm_dp_helper.c:523: warning: No description
> > > > found for parameter 'id[6]'
> >    drivers/gpu/drm/drm_dp_helper.c:524: warning: No description
> > found for parameter 'id[6]'
> >    drivers/gpu/drm/drm_plane_helper.c:248: warning: No description
> > found for parameter 'dst'
> >    drivers/gpu/drm/drm_plane_helper.c:248: warning: Excess function
> > parameter 'dest' description in 'drm_plane_helper_check_update'
> >    drivers/gpu/drm/drm_plane_helper.c:247: warning: No description
> > found for parameter 'dst'
> >    drivers/gpu/drm/drm_plane_helper.c:247: warning: Excess function
> > parameter 'dest' description in 'drm_plane_helper_check_update'
> >    drivers/gpu/drm/drm_crtc.c:1270: WARNING: Inline literal start-
> > string without end-string.
> >    drivers/gpu/drm/drm_crtc.c:1385: WARNING: Inline literal start-
> > string without end-string.
> >    include/drm/drm_crtc.h:1202: WARNING: Inline literal start-
> > string without end-string.
> >    include/drm/drm_crtc.h:1255: WARNING: Inline literal start-
> > string without end-string.
> >    include/drm/drm_crtc.h:1268: WARNING: Inline literal start-
> > string without end-string.
> >    include/drm/drm_crtc.h:1272: WARNING: Inline literal start-
> > string without end-string.
> >    drivers/gpu/drm/drm_irq.c:718: WARNING: Option list ends without
> > a blank line; unexpected unindent.
> >    drivers/gpu/drm/drm_fb_helper.c:2195: WARNING: Inline emphasis
> > start-string without end-string.
> >    drivers/gpu/drm/drm_simple_kms_helper.c:141: WARNING: Inline
> > literal start-string without end-string.
> >    include/drm/drm_gem.h:212: WARNING: Inline emphasis start-string 
> > without end-string.
> >    drivers/gpu/drm/i915/i915_vgpu.c:176: WARNING: Literal block
> > ends without a blank line; unexpected unindent.
> >    drivers/gpu/drm/i915/intel_audio.c:54: WARNING: Inline emphasis
> > start-string without end-string.
> >    drivers/gpu/drm/i915/intel_audio.c:54: WARNING: Inline emphasis
> > start-string without end-string.
> >    drivers/gpu/drm/i915/intel_guc_fwif.h:159: WARNING: Block quote
> > ends without a blank line; unexpected unindent.
> >    drivers/gpu/drm/i915/intel_guc_fwif.h:178: WARNING: Enumerated
> > list ends without a blank line; unexpected unindent.
> >    Documentation/gpu/drm-kms.rst:13: WARNING: Could not lex
> > literal_block as "C". Highlighting skipped.
> >    Documentation/gpu/drm-kms-helpers.rst:16: WARNING: Could not lex
> > literal_block as "C". Highlighting skipped.
> >    Documentation/gpu/i915.rst:57: WARNING: Could not lex
> > literal_block as "C". Highlighting skipped.
> > 
> > vim +523 drivers/gpu/drm/drm_dp_helper.c
> > 
> >    507  case DP_DS_16BPC:
> >    508  return 16;
> >    509  }
> >    510  default:
> >    511  return 0;
> >    512  }
> >    513  }
> >    514  EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
> >    515  
> >    516  /**
> >    517   * drm_dp_downstream_id() - identify branch device
> >    518   * @aux: DisplayPort AUX channel
> >    519   *
> >    520   * Returns branch device id on success or NULL on
> > failure
> >    521   */
> >    522  int drm_dp_downstream_id(struct drm_dp_aux *aux, char
> > id[6])
> >  > 523  {
> >    524  return drm_dp_dpcd_read(aux, DP_BRANCH_ID,
> > id, 6);
> >    525  }
> >    526  EXPORT_SYMBOL(drm_dp_downstream_id);
> >    527  
> >    528  /*
> >    529   * I2C-over-AUX implementation
> >    530   */
> >    531  
> > 
> > ---
> > 0-DAY kernel test infrastructureOpen Source
> > Technology Center
> > https://lists.01.org/pipermail/kbuild-all   Intel
> > Corporation
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Re: [Intel-gfx] [PATCH v6 1/6] drm/i915: Fallback to lower link rate and lane count during link training

[Mika Kahola]

On Thu, 2016-09-15 at 17:03 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel EQ.
> In case of Channel EQ failures, it should fallback to
> lower link rate and lane count and start the CR phase again.
> 
> v6:
> * Do not split quoted string across line (Mika Kahola)
> v5:
> * Reset the link rate index to the max link rate index
> before lowering the lane count (Jani Nikula)
> * Use the paradigm for loop in intel_dp_link_rate_index
> v4:
> * Fixed the link rate fallback loop (Manasi Navare)
> v3:
> * Fixed some rebase issues (Mika Kahola)
> v2:
> * Add a helper function to return index of requested link rate
> into common_rates array
> * Changed the link rate fallback loop to make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 111
> +++---
>  drivers/gpu/drm/i915/intel_dp.c   |  15 
>  drivers/gpu/drm/i915/intel_dp_link_training.c |  12 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +-
>  4 files changed, 130 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 8065a5f..826d9f7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1637,19 +1637,18 @@ void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>   }
>  }
>  
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
>   int link_rate, uint32_t
> lane_count,
> - struct intel_shared_dpll *pll,
> - bool link_mst)
> + struct intel_shared_dpll *pll)
>  {
>   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>   struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>  
>   intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> -  link_mst);
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_edp_panel_on(intel_dp);
> +  false);
> +
> + intel_edp_panel_on(intel_dp);
>  
>   intel_ddi_clk_select(encoder, pll);
>   intel_prepare_dp_ddi_buffers(encoder);
> @@ -1660,6 +1659,28 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_dp_stop_link_train(intel_dp);
>  }
>  
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + int link_rate, uint32_t
> lane_count,
> + struct intel_shared_dpll *pll,
> + bool link_mst)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_shared_dpll_config tmp_pll_config;
> +
> + /* Disable the PLL and obtain the PLL for Link Training
> +  * that starts with highest link rate and lane count.
> +  */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate a
> hotplug */
> + if (!intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst))
> + drm_kms_helper_hotplug_event(encoder->base.dev);
> + pll->config = tmp_pll_config;
> +}
> +
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>     bool has_hdmi_sink,
>     struct drm_display_mode
> *adjusted_mode,
> @@ -1693,20 +1714,26 @@ static void intel_ddi_pre_enable(struct
> intel_encoder *intel_encoder,
>   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>   int type = intel_encoder->type;
>  
> - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + if (type == INTEL_OUTPUT_EDP)
> + intel_ddi_pre_enable_edp(intel_encoder,
> + crtc->config->port_clock,
> + crtc->config->lane_count,
> + crtc->

Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Change the placement of some static functions in intel_dp.c

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Thu, 2016-09-15 at 17:04 -0700, Manasi Navare wrote:
> These static helper functions are required to be used within upfront
> link training related functions so they need to be placed at the top
> of the file. It also changes macro dev to dev_priv.
> 
> v3:
> * Add cleanup to other patch (Mika Kahola)
> v2:
> * Dont move around functions declared in intel_drv.h (Rodrigo Vivi)
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 150 
> 
>  1 file changed, 75 insertions(+), 75 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 65b4559..61d71fa 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -213,6 +213,81 @@ intel_dp_downstream_max_dotclock(struct intel_dp
> *intel_dp)
>   return max_dotclk;
>  }
>  
> +static int
> +intel_dp_sink_rates(struct intel_dp *intel_dp, const int
> **sink_rates)
> +{
> + if (intel_dp->num_sink_rates) {
> + *sink_rates = intel_dp->sink_rates;
> + return intel_dp->num_sink_rates;
> + }
> +
> + *sink_rates = default_rates;
> +
> + return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> +}
> +
> +static int
> +intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
> +{
> + struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> + struct drm_device *dev = dig_port->base.base.dev;
> + int size;
> +
> + if (IS_BROXTON(dev)) {
> + *source_rates = bxt_rates;
> + size = ARRAY_SIZE(bxt_rates);
> + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + *source_rates = skl_rates;
> + size = ARRAY_SIZE(skl_rates);
> + } else {
> + *source_rates = default_rates;
> + size = ARRAY_SIZE(default_rates);
> + }
> +
> + /* This depends on the fact that 5.4 is last value in the
> array */
> + if (!intel_dp_source_supports_hbr2(intel_dp))
> + size--;
> +
> + return size;
> +}
> +
> +static int intersect_rates(const int *source_rates, int source_len,
> +    const int *sink_rates, int sink_len,
> +    int *common_rates)
> +{
> + int i = 0, j = 0, k = 0;
> +
> + while (i < source_len && j < sink_len) {
> + if (source_rates[i] == sink_rates[j]) {
> + if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
> + return k;
> + common_rates[k] = source_rates[i];
> + ++k;
> + ++i;
> + ++j;
> + } else if (source_rates[i] < sink_rates[j]) {
> + ++i;
> + } else {
> + ++j;
> + }
> + }
> + return k;
> +}
> +
> +static int intel_dp_common_rates(struct intel_dp *intel_dp,
> +  int *common_rates)
> +{
> + const int *source_rates, *sink_rates;
> + int source_len, sink_len;
> +
> + sink_len = intel_dp_sink_rates(intel_dp, _rates);
> + source_len = intel_dp_source_rates(intel_dp, _rates);
> +
> + return intersect_rates(source_rates, source_len,
> +    sink_rates, sink_len,
> +    common_rates);
> +}
> +
>  static enum drm_mode_status
>  intel_dp_mode_valid(struct drm_connector *connector,
>   struct drm_display_mode *mode)
> @@ -1281,19 +1356,6 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>   intel_dp->aux.transfer = intel_dp_aux_transfer;
>  }
>  
> -static int
> -intel_dp_sink_rates(struct intel_dp *intel_dp, const int
> **sink_rates)
> -{
> - if (intel_dp->num_sink_rates) {
> - *sink_rates = intel_dp->sink_rates;
> - return intel_dp->num_sink_rates;
> - }
> -
> - *sink_rates = default_rates;
> -
> - return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> -}
> -
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> @@ -1310,31 +1372,6 @@ bool intel_dp_source_supports_hbr2(struct
> intel_dp *intel_dp)
>   return false;
>  }
>  
> -static int
> -intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
> -{
> - struct intel_digital_port *dig_port =
&

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Code cleanup to use dev_priv and INTEL_GEN

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Thu, 2016-09-15 at 17:04 -0700, Manasi Navare wrote:
> Replace dev with dev_priv and INTEL_INFO with INTEL_GEN
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 61d71fa..8061e32 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -230,13 +230,13 @@ static int
>  intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
>  {
>   struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
>   int size;
>  
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
>   *source_rates = bxt_rates;
>   size = ARRAY_SIZE(bxt_rates);
> - } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>   *source_rates = skl_rates;
>   size = ARRAY_SIZE(skl_rates);
>   } else {
> @@ -1359,14 +1359,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
>  
>   /* WaDisableHBR2:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0))
>   return false;
>  
> - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> IS_BROADWELL(dev) ||
> - (INTEL_INFO(dev)->gen >= 9))
> + if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> + IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
>   return true;
>   else
>   return false;
-- 
Mika Kahola - Intel OTC

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Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Change the placement of some static functions in intel_dp.c

[Mika Kahola]

DisableHBR2:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
> + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0))
>   return false;
>  
> - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> IS_BROADWELL(dev) ||
> - (INTEL_INFO(dev)->gen >= 9))
> + if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> + IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
>   return true;
>   else
>   return false;
>  }
>  
> -static int
> -intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
> -{
> - struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> - int size;
> -
> - if (IS_BROXTON(dev)) {
> - *source_rates = bxt_rates;
> - size = ARRAY_SIZE(bxt_rates);
> - } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> - *source_rates = skl_rates;
> - size = ARRAY_SIZE(skl_rates);
> - } else {
> - *source_rates = default_rates;
> - size = ARRAY_SIZE(default_rates);
> - }
> -
> - /* This depends on the fact that 5.4 is last value in the
> array */
> - if (!intel_dp_source_supports_hbr2(intel_dp))
> - size--;
> -
> - return size;
> -}
> -
>  static void
>  intel_dp_set_clock(struct intel_encoder *encoder,
>      struct intel_crtc_state *pipe_config)
> @@ -1343,43 +1380,6 @@ intel_dp_set_clock(struct intel_encoder
> *encoder,
>   }
>  }
>  
> -static int intersect_rates(const int *source_rates, int source_len,
> -    const int *sink_rates, int sink_len,
> -    int *common_rates)
> -{
> - int i = 0, j = 0, k = 0;
> -
> - while (i < source_len && j < sink_len) {
> - if (source_rates[i] == sink_rates[j]) {
> - if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
> - return k;
> - common_rates[k] = source_rates[i];
> - ++k;
> - ++i;
> - ++j;
> - } else if (source_rates[i] < sink_rates[j]) {
> - ++i;
> -     } else {
> - ++j;
> - }
> - }
> - return k;
> -}
> -
> -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> -  int *common_rates)
> -{
> - const int *source_rates, *sink_rates;
> - int source_len, sink_len;
> -
> - sink_len = intel_dp_sink_rates(intel_dp, _rates);
> - source_len = intel_dp_source_rates(intel_dp, _rates);
> -
> - return intersect_rates(source_rates, source_len,
> -    sink_rates, sink_len,
> -    common_rates);
> -}
> -
>  static void snprintf_int_array(char *str, size_t len,
>      const int *array, int nelem)
>  {
-- 
Mika Kahola - Intel OTC

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Re: [Intel-gfx] [PATCH v5 1/5] drm/i915: Fallback to lower link rate and lane count during link training

[Mika Kahola]

On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel EQ.
> In case of Channel EQ failures, it should fallback to
> lower link rate and lane count and start the CR phase again.
> 
> v5:
> * Reset the link rate index to the max link rate index
> before lowering the lane count (Jani Nikula)
> * Use the paradigm for loop in intel_dp_link_rate_index
> v4:
> * Fixed the link rate fallback loop (Manasi Navare)
> v3:
> * Fixed some rebase issues (Mika Kahola)
> v2:
> * Add a helper function to return index of requested link rate
> into common_rates array
> * Changed the link rate fallback loop to make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 112
> +++---
>  drivers/gpu/drm/i915/intel_dp.c   |  15 
>  drivers/gpu/drm/i915/intel_dp_link_training.c |  12 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +-
>  4 files changed, 131 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 8065a5f..4d3a931 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1637,19 +1637,18 @@ void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>   }
>  }
>  
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
>   int link_rate, uint32_t
> lane_count,
> - struct intel_shared_dpll *pll,
> - bool link_mst)
> + struct intel_shared_dpll *pll)
>  {
>   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>   struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>  
>   intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> -  link_mst);
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_edp_panel_on(intel_dp);
> +  false);
> +
> + intel_edp_panel_on(intel_dp);
>  
>   intel_ddi_clk_select(encoder, pll);
>   intel_prepare_dp_ddi_buffers(encoder);
> @@ -1660,6 +1659,28 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_dp_stop_link_train(intel_dp);
>  }
>  
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + int link_rate, uint32_t
> lane_count,
> + struct intel_shared_dpll *pll,
> + bool link_mst)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_shared_dpll_config tmp_pll_config;
> +
> + /* Disable the PLL and obtain the PLL for Link Training
> +  * that starts with highest link rate and lane count.
> +  */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate a
> hotplug */
> + if (!intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst))
> + drm_kms_helper_hotplug_event(encoder->base.dev);
> + pll->config = tmp_pll_config;
> +}
> +
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>     bool has_hdmi_sink,
>     struct drm_display_mode
> *adjusted_mode,
> @@ -1693,20 +1714,26 @@ static void intel_ddi_pre_enable(struct
> intel_encoder *intel_encoder,
>   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>   int type = intel_encoder->type;
>  
> - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + if (type == INTEL_OUTPUT_EDP)
> + intel_ddi_pre_enable_edp(intel_encoder,
> + crtc->config->port_clock,
> + crtc->config->lane_count,
> + crtc->config->shared_dpll);
> +
> + if (type == INTEL_OUTPUT_DP)
>     

Re: [Intel-gfx] [PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

[Mika Kahola]

On Fri, 2016-09-09 at 12:09 +0300, Ville Syrjälä wrote:
> On Fri, Sep 09, 2016 at 10:45:27AM +0300, Mika Kahola wrote:
> > 
> > On Thu, 2016-09-08 at 15:48 +0300, Ville Syrjälä wrote:
> > > 
> > > On Wed, Aug 17, 2016 at 01:49:49PM +0300, Mika Kahola wrote:
> > > > 
> > > > 
> > > > Respect max TMDS clock frequency from DPCD for active
> > > > DP to HDMI adapters.
> > > > 
> > > > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_drv.h  |  3 +++
> > > >  drivers/gpu/drm/i915/intel_hdmi.c | 27
> > > > +++
> > > >  2 files changed, 30 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 1c700b0..b7fd551 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -817,6 +817,9 @@ struct intel_hdmi {
> > > >     i915_reg_t hdmi_reg;
> > > >     int ddc_bus;
> > > >     struct {
> > > > +   int max_tmds_clock;
> > > > +   } dp_to_hdmi;
> > > > +   struct {
> > > >     enum drm_dp_dual_mode_type type;
> > > >     int max_tmds_clock;
> > > >     } dp_dual_mode;
> > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > index 4df9f38..1469d00 100644
> > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > @@ -1204,6 +1204,9 @@ static int hdmi_port_clock_limit(struct
> > > > intel_hdmi *hdmi,
> > > >     int max_tmds_clock =
> > > > intel_hdmi_source_max_tmds_clock(to_i915(dev));
> > > >  
> > > >     if (respect_downstream_limits) {
> > > > +   if (hdmi->dp_to_hdmi.max_tmds_clock)
> > > > +   max_tmds_clock = min(max_tmds_clock,
> > > > +    hdmi-
> > > > > 
> > > > > dp_to_hdmi.max_tmds_clock);
> > > >     if (hdmi->dp_dual_mode.max_tmds_clock)
> > > >     max_tmds_clock = min(max_tmds_clock,
> > > >      hdmi-
> > > > > 
> > > > > dp_dual_mode.max_tmds_clock);
> > > > @@ -1373,11 +1376,33 @@ intel_hdmi_unset_edid(struct
> > > > drm_connector
> > > > *connector)
> > > >     intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
> > > >     intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
> > > >  
> > > > +   intel_hdmi->dp_to_hdmi.max_tmds_clock = 0;
> > > > +
> > > >     kfree(to_intel_connector(connector)->detect_edid);
> > > >     to_intel_connector(connector)->detect_edid = NULL;
> > > >  }
> > > >  
> > > >  static void
> > > > +intel_hdmi_dp_adapter_detect(struct drm_connector *connector)
> > > > +{
> > > > +   struct intel_hdmi *intel_hdmi =
> > > > intel_attached_hdmi(connector);
> > > > +   struct intel_digital_port *intel_dig_port =
> > > > +   hdmi_to_dig_port(intel_hdmi);
> > > > +   struct intel_dp *intel_dp = _dig_port->dp;
> > > > +   int type = intel_dp->downstream_ports[0] &
> > > > DP_DS_PORT_TYPE_MASK;
> > > > +
> > > > +   if (type != DP_DS_PORT_TYPE_HDMI)
> > > > +   return;
> > > > +
> > > > +   intel_hdmi->dp_to_hdmi.max_tmds_clock =
> > > > +   drm_dp_downstream_max_clock(intel_dp->dpcd,
> > > > +   intel_dp-
> > > > > 
> > > > > downstream_ports);
> > > Poets driven by intel_hdmi don't have DPCD, so I don't know what
> > > this
> > > is supposed to achieve.
> > My understanding is that these HDMI adapters has DPCD and therefore
> > I
> > placed this function. In addition, I think we should respect the
> > clocks
> > if the adapter provides that information.
> Only stuff driven by intel_dp has DPCD.
All right. Then this patch can be discarded. Or maybe I move this stuff
into

[Intel-gfx] [PATCH v9 03/12] drm: Helper to read max clock rate

[Mika Kahola]

Helper routine to read out maximum supported pixel rate
for DisplayPort legay VGA converter or TMDS clock rate
for other digital legacy converters. The helper returns
clock rate in kHz.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 33 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 031c4d3..7497490 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -439,6 +439,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct 
drm_dp_link *link)
 }
 EXPORT_SYMBOL(drm_dp_link_configure);
 
+/**
+ * drm_dp_downstream_max_clock() - extract branch device max
+ * pixel rate for legacy VGA
+ * converter or max TMDS clock
+ * rate for others
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max clock in kHz on success or 0 if max clock not defined
+ */
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   return port_cap[1] * 8 * 1000;
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   return port_cap[1] * 2500;
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_clock);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0d84046..60dd9dc 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -815,6 +815,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
2.7.4

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[Intel-gfx] [PATCH v9 05/12] drm: Read DP branch device id

[Mika Kahola]

Read DisplayPort branch device id string.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 12 
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 14e8ea0..01ee7af 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -514,6 +514,18 @@ int drm_dp_downstream_max_bpc(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 
+/**
+ * drm_dp_downstream_id() - identify branch device
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns branch device id on success or NULL on failure
+ */
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
+{
+   return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
+}
+EXPORT_SYMBOL(drm_dp_downstream_id);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f3d1424..faea76b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,7 @@
 #define DP_SOURCE_OUI  0x300
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
+#define DP_BRANCH_ID0x503
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
@@ -819,6 +820,7 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  const u8 port_cap[4]);
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
2.7.4

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[Intel-gfx] [PATCH v9 01/12] drm: Add missing DP downstream port types

[Mika Kahola]

Add missing DisplayPort downstream port types. The introduced
new port types are DP++ and Wireless.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 include/drm/drm_dp_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 63b8bd5..ba9731e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -211,6 +211,8 @@
 # define DP_DS_PORT_TYPE_DVI   2
 # define DP_DS_PORT_TYPE_HDMI  3
 # define DP_DS_PORT_TYPE_NON_EDID  4
+# define DP_DS_PORT_TYPE_DP_DUALMODE5
+# define DP_DS_PORT_TYPE_WIRELESS   6
 # define DP_DS_PORT_HPD(1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-- 
2.7.4

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[Intel-gfx] [PATCH v9 06/12] drm/i915: Cleanup DisplayPort AUX channel initialization

[Mika Kahola]

Let's remove reference to "struct intel_connector *connector"
in intel_dp_aux_init() function as it is no longer required.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 75ac62f..c69ad13 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1243,7 +1243,7 @@ intel_dp_aux_fini(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
+intel_dp_aux_init(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->port;
@@ -5624,7 +5624,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->interlace_allowed = true;
connector->doublescan_allowed = 0;
 
-   intel_dp_aux_init(intel_dp, intel_connector);
+   intel_dp_aux_init(intel_dp);
 
INIT_DELAYED_WORK(_dp->panel_vdd_work,
  edp_panel_vdd_work);
-- 
2.7.4

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[Intel-gfx] [PATCH v9 09/12] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
v5: Use of intel_dp->downstream_ports to read out port capabilities.
Code restructuring (Ville)
v6: Move DP branch device check to drm_dp_helper.c (Daniel)
v7: Cleanup as suggested by Ville

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7428c72..8f17c88 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10;
 }
 
+static int
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int max_dotclk = dev_priv->max_dotclk_freq;
+   int ds_max_dotclk;
+
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_VGA)
+   return max_dotclk;
+
+   ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   if (ds_max_dotclk != 0)
+   max_dotclk = min(max_dotclk, ds_max_dotclk);
+
+   return max_dotclk;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
-   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+   int max_dotclk;
+
+   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
-- 
2.7.4

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[Intel-gfx] [PATCH v9 08/12] drm/i915: Read DP branch device SW revision

[Mika Kahola]

SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register fields 0x50A
and 0x50B.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print SW revision info to dmesg (Ville)
v4: commit message fix (Jim Bride)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 20 
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bb0417c..7428c72 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1438,6 +1438,25 @@ static void intel_dp_print_hw_revision(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
 }
 
+static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev[2];
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_SW_REV, , 2);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4332,6 +4351,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp_probe_oui(intel_dp);
 
intel_dp_print_hw_revision(intel_dp);
+   intel_dp_print_sw_revision(intel_dp);
 
intel_dp_configure_mst(intel_dp);
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 19ac599..215202f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -447,6 +447,7 @@
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
 #define DP_BRANCH_HW_REV0x509
+#define DP_BRANCH_SW_REV0x50A
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
2.7.4

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[Intel-gfx] [PATCH v9 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

[Mika Kahola]

Respect max TMDS clock frequency from DPCD for active
DP to HDMI adapters.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  3 +++
 drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7868d5c..16374a1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -823,6 +823,9 @@ struct intel_hdmi {
i915_reg_t hdmi_reg;
int ddc_bus;
struct {
+   int max_tmds_clock;
+   } dp_to_hdmi;
+   struct {
enum drm_dp_dual_mode_type type;
int max_tmds_clock;
} dp_dual_mode;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index c51073f..1066114 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1220,6 +1220,9 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
 
if (respect_downstream_limits) {
+   if (hdmi->dp_to_hdmi.max_tmds_clock)
+   max_tmds_clock = min(max_tmds_clock,
+hdmi->dp_to_hdmi.max_tmds_clock);
if (hdmi->dp_dual_mode.max_tmds_clock)
max_tmds_clock = min(max_tmds_clock,
 hdmi->dp_dual_mode.max_tmds_clock);
@@ -1390,11 +1393,33 @@ intel_hdmi_unset_edid(struct drm_connector *connector)
intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
 
+   intel_hdmi->dp_to_hdmi.max_tmds_clock = 0;
+
kfree(to_intel_connector(connector)->detect_edid);
to_intel_connector(connector)->detect_edid = NULL;
 }
 
 static void
+intel_hdmi_dp_adapter_detect(struct drm_connector *connector)
+{
+   struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+   struct intel_digital_port *intel_dig_port =
+   hdmi_to_dig_port(intel_hdmi);
+   struct intel_dp *intel_dp = _dig_port->dp;
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_HDMI)
+   return;
+
+   intel_hdmi->dp_to_hdmi.max_tmds_clock =
+   drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   DRM_DEBUG_KMS("DP HDMI adaptor detected (max TMDS clock : %d kHz\n",
+ intel_hdmi->dp_to_hdmi.max_tmds_clock);
+}
+
+static void
 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
 {
struct drm_i915_private *dev_priv = to_i915(connector->dev);
@@ -1454,6 +1479,8 @@ intel_hdmi_set_edid(struct drm_connector *connector)
 
intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
 
+   intel_hdmi_dp_adapter_detect(connector);
+
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
 
to_intel_connector(connector)->detect_edid = edid;
-- 
2.7.4

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[Intel-gfx] [PATCH v9 11/12] drm: Add DP branch device info on debugfs

[Mika Kahola]

Read DisplayPort branch device info from through debugfs
interface.

v2: use drm_dp_helper routines to collect data
v3: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v4: move DP branch device info to function 'intel_dp_branch_device_info()'
v5: initial step to move debugging info from intel_dp. to drm_dp_helper.c 
(Daniel)
v6: read hw and sw revision without using specific drm_dp_helper routines
v7: indentation fixes (Jim Bride)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 85 +
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ++
 include/drm/drm_dp_helper.h |  2 +
 3 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 01ee7af..a536514 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -526,6 +526,91 @@ int drm_dp_downstream_id(struct drm_dp_aux *aux, char 
id[6])
 }
 EXPORT_SYMBOL(drm_dp_downstream_id);
 
+/**
+ * drm_dp_downstream_debug() - debug DP branch devices
+ * @m: pointer for debugfs file
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @aux: DisplayPort AUX channel
+ *
+ */
+void drm_dp_downstream_debug(struct seq_file *m,
+const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4], struct drm_dp_aux *aux)
+{
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+DP_DETAILED_CAP_INFO_AVAILABLE;
+   int clk;
+   int bpc;
+   char id[6];
+   int len;
+   uint8_t rev[2];
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+DP_DWN_STRM_PORT_PRESENT;
+
+   seq_printf(m, "\tDP branch device present: %s\n",
+  branch_device ? "yes" : "no");
+
+   if (!branch_device)
+   return;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_DP:
+   seq_puts(m, "\t\tType: DisplayPort\n");
+   break;
+   case DP_DS_PORT_TYPE_VGA:
+   seq_puts(m, "\t\tType: VGA\n");
+   break;
+   case DP_DS_PORT_TYPE_DVI:
+   seq_puts(m, "\t\tType: DVI\n");
+   break;
+   case DP_DS_PORT_TYPE_HDMI:
+   seq_puts(m, "\t\tType: HDMI\n");
+   break;
+   case DP_DS_PORT_TYPE_NON_EDID:
+   seq_puts(m, "\t\tType: others without EDID support\n");
+   break;
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   seq_puts(m, "\t\tType: DP++\n");
+   break;
+   case DP_DS_PORT_TYPE_WIRELESS:
+   seq_puts(m, "\t\tType: Wireless\n");
+   break;
+   default:
+   seq_puts(m, "\t\tType: N/A\n");
+   }
+
+   drm_dp_downstream_id(aux, id);
+   seq_printf(m, "\t\tID: %s\n", id);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, [0], 1);
+   if (len > 0)
+   seq_printf(m, "\t\tHW: %d.%d\n",
+  (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, , 2);
+   if (len > 0)
+   seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
+
+   if (detailed_cap_info) {
+   clk = drm_dp_downstream_max_clock(dpcd, port_cap);
+
+   if (clk > 0) {
+   if (type == DP_DS_PORT_TYPE_VGA)
+   seq_printf(m, "\t\tMax dot clock: %d kHz\n", 
clk);
+   else
+   seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", 
clk);
+   }
+
+   bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
+
+   if (bpc > 0)
+   seq_printf(m, "\t\tMax bpc: %d\n", bpc);
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_debug);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 02b627e..44fab14 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2851,6 +2851,9 @@ static void intel_dp_info(struct seq_file *m,
seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
intel_panel_info(m, _connector->panel);
+
+   drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
+   _dp->aux);
 }
 
 static void intel_hdmi_info(struct seq_file *m,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 21520

[Intel-gfx] [PATCH v9 10/12] drm/i915: Update bits per component for display info

[Mika Kahola]

DisplayPort branch device may define max supported bits per
component. Update display info based on this value if bpc
is defined.

v2: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v3: Fill bpc for connector's display info in separate
drm_dp_helper function (Daniel)
v4: remove updating bpc for display info as it may be overridden
when parsing EDID. Instead, check bpc for DP branch device
during compute_config
v5: Indentation fixes (Jim Bride)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8f17c88..69cee9b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1524,6 +1524,20 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, 
int port_clock,
}
 }
 
+int intel_dp_compute_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
+{
+   int bpp, bpc;
+
+   bpp = pipe_config->pipe_bpp;
+   bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, 
intel_dp->downstream_ports);
+
+   if (bpc > 0)
+   bpp = min(bpp, 3*bpc);
+
+   return bpp;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1590,7 +1604,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 * bpc in between. */
-   bpp = pipe_config->pipe_bpp;
+   bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
if (is_edp(intel_dp)) {
 
/* Get bpp from vbt only for panels that dont have bpp in edid 
*/
-- 
2.7.4

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[Intel-gfx] [PATCH v9 07/12] drm/i915: Read DP branch device HW revision

[Mika Kahola]

HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print HW revision info to dmesg (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c69ad13..bb0417c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1419,6 +1419,25 @@ static void intel_dp_print_rates(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
+static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev;
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_HW_REV, , 1);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4312,6 +4331,8 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
 
intel_dp_probe_oui(intel_dp);
 
+   intel_dp_print_hw_revision(intel_dp);
+
intel_dp_configure_mst(intel_dp);
 
if (intel_dp->is_mst) {
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index faea76b..19ac599 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -446,6 +446,7 @@
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
+#define DP_BRANCH_HW_REV0x509
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
2.7.4

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[Intel-gfx] [PATCH v9 02/12] drm: Drop VGA from bpc definitions

[Mika Kahola]

Drop "VGA" from bits per component definitions as these
are also used by other standards such as DVI, HDMI,
DP++.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 include/drm/drm_dp_helper.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ba9731e..0d84046 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -216,11 +216,11 @@
 # define DP_DS_PORT_HPD(1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-# define DP_DS_VGA_MAX_BPC_MASK(3 << 0)
-# define DP_DS_VGA_8BPC0
-# define DP_DS_VGA_10BPC   1
-# define DP_DS_VGA_12BPC   2
-# define DP_DS_VGA_16BPC   3
+# define DP_DS_MAX_BPC_MASK(3 << 0)
+# define DP_DS_8BPC0
+# define DP_DS_10BPC   1
+# define DP_DS_12BPC   2
+# define DP_DS_16BPC   3
 
 /* link configuration */
 #defineDP_LINK_BW_SET  0x100
-- 
2.7.4

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[Intel-gfx] [PATCH v9 04/12] drm: Helper to read max bits per component

[Mika Kahola]

Helper routine to read out maximum supported bits per
component for DisplayPort legay converters.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 42 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 7497490..14e8ea0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -472,6 +472,48 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
 
+/**
+ * drm_dp_downstream_max_bpc() - extract branch device max
+ *   bits per component
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max bpc on success or 0 if max bpc not defined
+ */
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+   int bpc;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
+
+   switch (bpc) {
+   case DP_DS_8BPC:
+   return 8;
+   case DP_DS_10BPC:
+   return 10;
+   case DP_DS_12BPC:
+   return 12;
+   case DP_DS_16BPC:
+   return 16;
+   }
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 60dd9dc..f3d1424 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -817,6 +817,8 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
2.7.4

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[Intel-gfx] [PATCH v9 00/12] drm/i915: DP branch devices

[Mika Kahola]

Prep work for DP branch device handling

This series of patches reads DPCD register 0x80h for receiver
capabilities for DP branch devices. The branch device types are
converters for the following standards

 - DP to VGA
 - DP to DVI
 - DP to HDMI
 - DP++ dual mode
 - Wireless WiGig
 
DPCD register defines max pixel rate for VGA dongles. This
check is carried out during mode validation. 

[1] git://github.com/mkahola/drm-intel-mika.git dp_branch_device

v2: DPCD register read outs moved to drm (Ville, Daniel)
v3: Max pixel rate computation moved to drm (Daniel)
v4: Use of drm_dp_helper routines to collect data (Ville)
v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville)
v6: Rebase and i915_debugfs cleanup
v7: Structure cleanups and initial step to move DP debugging info to 
drm_dp_helpers
v8: Cleanups and TMDS clock frequency check for HDMI adapter
v9: Indentation fixes (Jim Bride)

Mika Kahola (12):
  drm: Add missing DP downstream port types
  drm: Drop VGA from bpc definitions
  drm: Helper to read max clock rate
  drm: Helper to read max bits per component
  drm: Read DP branch device id
  drm/i915: Cleanup DisplayPort AUX channel initialization
  drm/i915: Read DP branch device HW revision
  drm/i915: Read DP branch device SW revision
  drm/i915: Check pixel rate for DP to VGA dongle
  drm/i915: Update bits per component for display info
  drm: Add DP branch device info on debugfs
  drm/i915: Check TMDS clock DP to HDMI dongle

 drivers/gpu/drm/drm_dp_helper.c | 172 
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +
 drivers/gpu/drm/i915/intel_dp.c |  88 +-
 drivers/gpu/drm/i915/intel_drv.h|   3 +
 drivers/gpu/drm/i915/intel_hdmi.c   |  27 ++
 include/drm/drm_dp_helper.h |  22 +++--
 6 files changed, 306 insertions(+), 9 deletions(-)

-- 
2.7.4

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Re: [Intel-gfx] [PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

[Mika Kahola]

On Thu, 2016-09-08 at 15:48 +0300, Ville Syrjälä wrote:
> On Wed, Aug 17, 2016 at 01:49:49PM +0300, Mika Kahola wrote:
> > 
> > Respect max TMDS clock frequency from DPCD for active
> > DP to HDMI adapters.
> > 
> > Signed-off-by: Mika Kahola <mika.kah...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h  |  3 +++
> >  drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 1c700b0..b7fd551 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -817,6 +817,9 @@ struct intel_hdmi {
> >     i915_reg_t hdmi_reg;
> >     int ddc_bus;
> >     struct {
> > +   int max_tmds_clock;
> > +   } dp_to_hdmi;
> > +   struct {
> >     enum drm_dp_dual_mode_type type;
> >     int max_tmds_clock;
> >     } dp_dual_mode;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 4df9f38..1469d00 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1204,6 +1204,9 @@ static int hdmi_port_clock_limit(struct
> > intel_hdmi *hdmi,
> >     int max_tmds_clock =
> > intel_hdmi_source_max_tmds_clock(to_i915(dev));
> >  
> >     if (respect_downstream_limits) {
> > +   if (hdmi->dp_to_hdmi.max_tmds_clock)
> > +   max_tmds_clock = min(max_tmds_clock,
> > +    hdmi-
> > >dp_to_hdmi.max_tmds_clock);
> >     if (hdmi->dp_dual_mode.max_tmds_clock)
> >     max_tmds_clock = min(max_tmds_clock,
> >      hdmi-
> > >dp_dual_mode.max_tmds_clock);
> > @@ -1373,11 +1376,33 @@ intel_hdmi_unset_edid(struct drm_connector
> > *connector)
> >     intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
> >     intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
> >  
> > +   intel_hdmi->dp_to_hdmi.max_tmds_clock = 0;
> > +
> >     kfree(to_intel_connector(connector)->detect_edid);
> >     to_intel_connector(connector)->detect_edid = NULL;
> >  }
> >  
> >  static void
> > +intel_hdmi_dp_adapter_detect(struct drm_connector *connector)
> > +{
> > +   struct intel_hdmi *intel_hdmi =
> > intel_attached_hdmi(connector);
> > +   struct intel_digital_port *intel_dig_port =
> > +   hdmi_to_dig_port(intel_hdmi);
> > +   struct intel_dp *intel_dp = _dig_port->dp;
> > +   int type = intel_dp->downstream_ports[0] &
> > DP_DS_PORT_TYPE_MASK;
> > +
> > +   if (type != DP_DS_PORT_TYPE_HDMI)
> > +   return;
> > +
> > +   intel_hdmi->dp_to_hdmi.max_tmds_clock =
> > +   drm_dp_downstream_max_clock(intel_dp->dpcd,
> > +   intel_dp-
> > >downstream_ports);
> Poets driven by intel_hdmi don't have DPCD, so I don't know what this
> is supposed to achieve.
My understanding is that these HDMI adapters has DPCD and therefore I
placed this function. In addition, I think we should respect the clocks
if the adapter provides that information.

> 
> > 
> > +
> > +   DRM_DEBUG_KMS("DP HDMI adaptor detected (max TMDS clock :
> > %d kHz\n",
> > +     intel_hdmi->dp_to_hdmi.max_tmds_clock);
> > +}
> > +
> > +static void
> >  intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector,
> > bool has_edid)
> >  {
> >     struct drm_i915_private *dev_priv = to_i915(connector-
> > >dev);
> > @@ -1438,6 +1463,8 @@ intel_hdmi_set_edid(struct drm_connector
> > *connector, bool force)
> >  
> >     intel_hdmi_dp_dual_mode_detect(connector, edid !=
> > NULL);
> >  
> > +   intel_hdmi_dp_adapter_detect(connector);
> > +
> >     intel_display_power_put(dev_priv,
> > POWER_DOMAIN_GMBUS);
> >     }
> >  
> > -- 
> > 1.9.1
-- 
Mika Kahola - Intel OTC

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Re: [Intel-gfx] [PATCH v13 13/14] drm/i915/dp: Enable Upfront link training for typeC DP support on HSW/BDW/SKL/BXT (DDI platforms)

[Mika Kahola]

On Wed, 2016-09-07 at 11:28 -0700, Manasi Navare wrote:
> From: Durgadoss R <durgados...@intel.com>
> 
> To support USB type C alternate DP mode, the display driver needs to
> know the number of lanes required by the DP panel as well as number
> of lanes that can be supported by the type-C cable. Sometimes, the
> type-C cable may limit the bandwidth even if Panel can support
> more lanes. To address these scenarios, the display driver will
> start link training with max lanes, and if that fails, the driver
> falls back to x2 lanes; and repeats this procedure for all
> bandwidth/lane configurations.
> 
> * Since link training is done before modeset only the port
>   (and not pipe/planes) and its associated PLLs are enabled.
> * On DP hotplug: Directly start link training on the DP encoder.
> * On Connected boot scenarios: When booted with an LFP and a DP,
>   sometimes BIOS brings up DP. In these cases, we disable the
>   crtc and then do upfront link training; and bring it back up.
> * All local changes made for upfront link training are reset
>   to their previous values once it is done; so that the
>   subsequent modeset is not aware of these changes.
> 
> Changes since v12:
> * Fix Rebase issues (Mika Kahola)
> Changes since v11:
> * Change the fallback link rate logic (Manasi)
> Changes since v10:
> * Use the ddi link train function that loops through all the link
> rates
> and lane counts starting from the highest supported (Manasi)
> * For upfront link training, set the upfront flag so that the link
> can
> be disabled after caching upfront values (Manasi)
> Changes since v9:
> * Change the macros to use dev_priv in place of dev (David Weinehall)
> Changes since v8:
> * Reset upfront lane count and link rate values on HPD
> for DP connector physical disconnect (Manasi)
> Changes since v7:
> * Move the upfront link training to intel_dp_mode_valid()
>   to avoid a race condition with DP MST sideband comms. (Ville)
> Changes since v6:
> * Fix some initialization bugs on link_rate (Jim Bride)
> * Use link_rate (and not link_bw) for upfront (Ville)
> * Make intel_dp_upfront*() as a vfunc (Ander)
> * The train_set_valid variable in intel_dp was removed due to
>   issues in fast link training. So, to indicate the link train
>   status, move the channel_eq inside intel_dp.
> Changes since v5:
> * Moved retry logic in upfront to intel_dp.c so that it
>   can be used for all platforms.
> Changes since v4:
> * Removed usage of crtc_state in upfront link training;
>   Hence no need to find free crtc to do upfront now.
> * Re-enable crtc if it was disabled for upfront.
> * Use separate variables to track max lane count
>   and link rate found by upfront, without modifying
>   the original DPCD read from panel.
> Changes since v3:
> * Fixed a return value on BXT check
> * Reworked on top of bxt_ddi_pll_select split from Ander
> * Renamed from ddi_upfront to bxt_upfront since the
>   upfront logic includes BXT specific functions for now.
> Changes since v2:
> * Rebased on top of latest dpll_mgr.c code and
>   latest HPD related clean ups.
> * Corrected return values from upfront (Ander)
> * Corrected atomic locking for upfront in intel_dp.c (Ville)
> Changes since v1:
> *  all pll related functions inside ddi.c
> 
> Signed-off-by: Durgadoss R <durgados...@intel.com>
> Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  |  21 +-
>  drivers/gpu/drm/i915/intel_dp.c   | 376
> +++---
>  drivers/gpu/drm/i915/intel_dp_link_training.c |   1 -
>  drivers/gpu/drm/i915/intel_drv.h  |  14 +-
>  4 files changed, 310 insertions(+), 102 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index da2b804..b32f7ba 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1673,7 +1673,8 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   pll->config.crtc_mask = 0;
>  
>   /* If Link Training fails, send a uevent to generate a
> hotplug */
> - if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst)))
> + if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst,
> +    false)))
>   drm_kms_helper_hotplug_event(encoder->base.dev);
>   pll->config = tmp_pll_config;
>  }
> @@ -2460,7 +2461,7 @@ intel_ddi_get_link_dpll(struct intel_dp
> *intel_dp, int clock)
>  
>  bool
>  intel_ddi_link_train(struct intel_dp *intel_dp, int max_link_rate,
>

Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Wed, 2016-09-07 at 13:53 +0300, Mika Kahola wrote:
> On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> > 
> > From: Jim Bride <jim.br...@linux.intel.com>
> > 
> > Add upfront link training to intel_dp_mst_mode_valid() so that we
> > know
> > topology constraints before we validate the legality of modes to be
> > checked.
> > Call the function that loops through the link rates and lane counts
> > starting from highest supported link rate and lane count for
> > training
> > the link in compliance with DP spec
> > 
> > v2:
> > * Rebased on new revision of link training patch (Manasi Navare)
> > 
> > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |  9 ++---
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 74
> > +++--
> >  drivers/gpu/drm/i915/intel_drv.h|  3 ++
> >  3 files changed, 61 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 7794180..0c7674f 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -131,7 +131,7 @@ static void vlv_steal_power_sequencer(struct
> > drm_device *dev,
> >       enum pipe pipe);
> >  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> >  
> > -static int
> > +int
> >  intel_dp_max_link_bw(struct intel_dp  *intel_dp)
> >  {
> >     int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
> > @@ -150,7 +150,7 @@ intel_dp_max_link_bw(struct
> > intel_dp  *intel_dp)
> >     return max_link_bw;
> >  }
> >  
> > -static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> >  {
> >     struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> >     u8 temp, source_max, sink_max;
> > @@ -312,8 +312,7 @@ static int intersect_rates(const int
> > *source_rates, int source_len,
> >     return k;
> >  }
> >  
> > -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> > -    int *common_rates)
> > +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> > *common_rates)
> >  {
> >     const int *source_rates, *sink_rates;
> >     int source_len, sink_len;
> > @@ -336,7 +335,7 @@ static int intel_dp_common_rates(struct
> > intel_dp
> > *intel_dp,
> >        common_rates);
> >  }
> >  
> > -static bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> > +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> >  {
> >     struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> >     struct intel_encoder *intel_encoder = _dig_port-
> > >base;
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index 54a9d76..98d45a4 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -41,21 +41,30 @@ static bool intel_dp_mst_compute_config(struct
> > intel_encoder *encoder,
> >     int bpp;
> >     int lane_count, slots;
> >     const struct drm_display_mode *adjusted_mode =
> > _config-
> > > 
> > > base.adjusted_mode;
> > -   int mst_pbn;
> > +   int mst_pbn, common_len;
> > +   int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> >  
> >     pipe_config->dp_encoder_is_mst = true;
> >     pipe_config->has_pch_encoder = false;
> > -   bpp = 24;
> > +
> >     /*
> > -    * for MST we always configure max link bw - the spec
> > doesn't
> > -    * seem to suggest we should do otherwise.
> > +    * For MST we always configure for the maximum trainable
> > link bw -
> > +    * the spec doesn't seem to suggest we should do
> > otherwise.  The
> > +    * calls to intel_dp_max_lane_count() and
> > intel_dp_common_rates()
> > +    * both take successful upfront link training into
> > account,
> > and
> > +    * return the DisplayPort max supported values in the
> > event
> > that
> > +    * upfront link training was not done.
> >      */
> > -   lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> > +   lane_count = intel_dp_max_lane_count(intel_dp);
&

Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST

[Mika Kahola]

On Wed, 2016-09-07 at 09:40 -0700, Jim Bride wrote:
> On Wed, Sep 07, 2016 at 01:53:31PM +0300, Mika Kahola wrote:
> > 
> > On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> > > 
> > > From: Jim Bride <jim.br...@linux.intel.com>
> > > 
> > > Add upfront link training to intel_dp_mst_mode_valid() so that we
> > > know
> > > topology constraints before we validate the legality of modes to
> > > be
> > > checked.
> > > Call the function that loops through the link rates and lane
> > > counts
> > > starting from highest supported link rate and lane count for
> > > training
> > > the link in compliance with DP spec
> > > 
> > > v2:
> > > * Rebased on new revision of link training patch (Manasi Navare)
> > > 
> > > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > > Signed-off-by: Jim Bride <jim.br...@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c |  9 ++---
> > >  drivers/gpu/drm/i915/intel_dp_mst.c | 74
> > > +++--
> > >  drivers/gpu/drm/i915/intel_drv.h|  3 ++
> > >  3 files changed, 61 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 7794180..0c7674f 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -131,7 +131,7 @@ static void vlv_steal_power_sequencer(struct
> > > drm_device *dev,
> > >     enum pipe pipe);
> > >  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > >  
> > > -static int
> > > +int
> > >  intel_dp_max_link_bw(struct intel_dp  *intel_dp)
> > >  {
> > >   int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
> > > @@ -150,7 +150,7 @@ intel_dp_max_link_bw(struct
> > > intel_dp  *intel_dp)
> > >   return max_link_bw;
> > >  }
> > >  
> > > -static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > > +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > >  {
> > >   struct intel_digital_port *intel_dig_port =
> > > dp_to_dig_port(intel_dp);
> > >   u8 temp, source_max, sink_max;
> > > @@ -312,8 +312,7 @@ static int intersect_rates(const int
> > > *source_rates, int source_len,
> > >   return k;
> > >  }
> > >  
> > > -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> > > -  int *common_rates)
> > > +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> > > *common_rates)
> > >  {
> > >   const int *source_rates, *sink_rates;
> > >   int source_len, sink_len;
> > > @@ -336,7 +335,7 @@ static int intel_dp_common_rates(struct
> > > intel_dp
> > > *intel_dp,
> > >      common_rates);
> > >  }
> > >  
> > > -static bool intel_dp_upfront_link_train(struct intel_dp
> > > *intel_dp)
> > > +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> > >  {
> > >   struct intel_digital_port *intel_dig_port =
> > > dp_to_dig_port(intel_dp);
> > >   struct intel_encoder *intel_encoder = _dig_port-
> > > >base;
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > index 54a9d76..98d45a4 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > @@ -41,21 +41,30 @@ static bool
> > > intel_dp_mst_compute_config(struct
> > > intel_encoder *encoder,
> > >   int bpp;
> > >   int lane_count, slots;
> > >   const struct drm_display_mode *adjusted_mode =
> > > _config-
> > > > 
> > > > base.adjusted_mode;
> > > - int mst_pbn;
> > > + int mst_pbn, common_len;
> > > + int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> > >  
> > >   pipe_config->dp_encoder_is_mst = true;
> > >   pipe_config->has_pch_encoder = false;
> > > - bpp = 24;
> > > +
> > >   /*
> > > -  * for MST we always configure max link bw - the spec
> > > doesn't
> > > -  * seem to suggest we should do otherwise.
> > > +  * For MST we always configure for the maximum trainable
> > > link bw -
> > > +  * the spec doesn't seem to

Re: [Intel-gfx] [PATCH v4 11/14] drm/i915: Fallback to lower link rate and lane count during link training

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Wed, 2016-09-07 at 17:30 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel EQ.
> In case of Channel EQ failures, it should fallback to
> lower link rate and lane count and start the CR phase again.
> 
> v4:
> * Fixed the link rate fallback loop (Manasi Navare)
> v3:
> * Fixed some rebase issues (Mika Kahola)
> v2:
> * Add a helper function to return index of requested link rate
> into common_rates array
> * Changed the link rate fallback loop to make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 109
> +++---
>  drivers/gpu/drm/i915/intel_dp.c   |  15 
>  drivers/gpu/drm/i915/intel_dp_link_training.c |  12 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +-
>  4 files changed, 128 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 25e7973..1278daa 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1634,19 +1634,18 @@ void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>   }
>  }
>  
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
>   int link_rate, uint32_t
> lane_count,
> - struct intel_shared_dpll *pll,
> - bool link_mst)
> + struct intel_shared_dpll *pll)
>  {
>   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>   struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>  
>   intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> -  link_mst);
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_edp_panel_on(intel_dp);
> +  false);
> +
> + intel_edp_panel_on(intel_dp);
>  
>   intel_ddi_clk_select(encoder, pll);
>   intel_prepare_dp_ddi_buffers(encoder);
> @@ -1657,6 +1656,28 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_dp_stop_link_train(intel_dp);
>  }
>  
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + int link_rate, uint32_t
> lane_count,
> + struct intel_shared_dpll *pll,
> + bool link_mst)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_shared_dpll_config tmp_pll_config;
> +
> + /* Disable the PLL and obtain the PLL for Link Training
> +  * that starts with highest link rate and lane count.
> +  */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate a
> hotplug */
> + if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst)))
> + drm_kms_helper_hotplug_event(encoder->base.dev);
> + pll->config = tmp_pll_config;
> +}
> +
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>     bool has_hdmi_sink,
>     struct drm_display_mode
> *adjusted_mode,
> @@ -1690,20 +1711,26 @@ static void intel_ddi_pre_enable(struct
> intel_encoder *intel_encoder,
>   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>   int type = intel_encoder->type;
>  
> - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + if (type == INTEL_OUTPUT_EDP)
> + intel_ddi_pre_enable_edp(intel_encoder,
> + crtc->config->port_clock,
> + crtc->config->lane_count,
> + crtc->config->shared_dpll);
> +
> + if (type == INTEL_OUTPUT_DP)
>   intel_ddi_pre_enable_dp(intel_encoder,
>   crtc->config-&g

Re: [Intel-gfx] [PATCH v3 9/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Wed, 2016-09-07 at 11:28 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> 
> This function cleans up clock recovery loop in link training
> compliant
> tp Dp Spec 1.2. It tries the clock recovery 5 times for the same
> voltage
> or until max voltage swing is reached and removes the additional non
> compliant retries. This function now returns a boolean values based
> on
> if clock recovery passed or failed.
> 
> v3:
> * Better Debug prints in case of failures (Mika Kahola)
> v2:
> * Rebased on top of new revision of vswing patch (Manasi Navare)
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 60 +--
> 
>  1 file changed, 28 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index b9880cf..80b9326 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -125,12 +125,11 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
>  }
>  
>  /* Enable corresponding port and start training pattern 1 */
> -static void
> +static bool
>  intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  {
> - int i;
>   uint8_t voltage;
> - int voltage_tries, loop_tries;
> + int voltage_tries, max_vswing_tries;
>   uint8_t link_config[2];
>   uint8_t link_bw, rate_select;
>  
> @@ -146,6 +145,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>   if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>   link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>   drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET,
> link_config, 2);
> +
>   if (intel_dp->num_sink_rates)
>   drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
>     _select, 1);
> @@ -161,58 +161,54 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>      DP_TRAINING_PATTERN_1 |
>      DP_LINK_SCRAMBLING_DISABLE))
> {
>   DRM_ERROR("failed to enable link training\n");
> - return;
> + return false;
>   }
>  
> - voltage = 0xff;
> - voltage_tries = 0;
> - loop_tries = 0;
> + voltage_tries = 1;
> + max_vswing_tries = 0;
>   for (;;) {
>   uint8_t link_status[DP_LINK_STATUS_SIZE];
>  
>   drm_dp_link_train_clock_recovery_delay(intel_dp-
> >dpcd);
> +
>   if (!intel_dp_get_link_status(intel_dp,
> link_status)) {
>   DRM_ERROR("failed to get link status\n");
> - break;
> + return false;
>   }
>  
>   if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> >lane_count)) {
>   DRM_DEBUG_KMS("clock recovery OK\n");
> - break;
> + return true;
>   }
>  
> - /* Check to see if we've tried the max voltage */
> - if (intel_dp_link_max_vswing_reached(intel_dp)) {
> - ++loop_tries;
> - if (loop_tries == 5) {
> - DRM_ERROR("too many full retries,
> give up\n");
> - intel_dp_dump_link_status(link_statu
> s);
> - break;
> - }
> - intel_dp_reset_link_train(intel_dp,
> -   DP_TRAINING_PATTER
> N_1 |
> -   DP_LINK_SCRAMBLING
> _DISABLE);
> - voltage_tries = 0;
> - continue;
> + if (voltage_tries == 5) {
> + DRM_DEBUG_KMS("Same voltage tried 5
> times\n");
> + return false;
> + }
> +
> + if (max_vswing_tries == 1) {
> + DRM_DEBUG_KMS("Max Voltage Swing
> reached\n");
> + return false;
>   }
>  
> - /* Check to see if we've tried the same voltage 5
> times */
> - if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
> - ++voltage_tries

Re: [Intel-gfx] [PATCH v3 8/14] drm/i915/dp: Move max. vswing check to it's own function

[Mika Kahola]

This compiler warning is fixed with the next patch of the series.

drivers/gpu/drm/i915/intel_dp_link_training.c: In function
‘intel_dp_link_training_clock_recovery’:
drivers/gpu/drm/i915/intel_dp_link_training.c:131:6: warning: unused
variable ‘i’ [-Wunused-variable]

Therefore,

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Wed, 2016-09-07 at 11:28 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> 
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
> 
> v3:
> Fixed the paranthesis warning (Mika Kahola)
> v2:
> Fixed the Compiler warning (Mika Kahola)
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0deebed..b9880cf 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -112,6 +112,18 @@ intel_dp_update_link_train(struct intel_dp
> *intel_dp)
>   return ret == intel_dp->lane_count;
>  }
>  
> +static bool intel_dp_link_max_vswing_reached(struct intel_dp
> *intel_dp)
> +{
> + int lane;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++)
> + if ((intel_dp->train_set[lane] &
> +  DP_TRAIN_MAX_SWING_REACHED) == 0)
> + return false;
> +
> + return true;
> +}
> +
>  /* Enable corresponding port and start training pattern 1 */
>  static void
>  intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> @@ -170,10 +182,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>   }
>  
>   /* Check to see if we've tried the max voltage */
> - for (i = 0; i < intel_dp->lane_count; i++)
> - if ((intel_dp->train_set[i] &
> DP_TRAIN_MAX_SWING_REACHED) == 0)
> - break;
> - if (i == intel_dp->lane_count) {
> + if (intel_dp_link_max_vswing_reached(intel_dp)) {
>   ++loop_tries;
>   if (loop_tries == 5) {
>   DRM_ERROR("too many full retries,
> give up\n");
-- 
Mika Kahola - Intel OTC

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Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST

[Mika Kahola]

l_encoder *encoder,
>   enum port port = intel_dig_port->port;
>   struct intel_connector *connector =
>   to_intel_connector(conn_state->connector);
> + struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> + struct intel_shared_dpll_config tmp_pll_config;
>   int ret;
>   uint32_t temp;
>   int slots;
> @@ -150,21 +161,23 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>  
>   if (intel_dp->active_mst_links == 0) {
> - intel_ddi_clk_select(_dig_port->base,
> -  pipe_config->shared_dpll);
> -
> - intel_prepare_dp_ddi_buffers(_dig_port->base);
> - intel_dp_set_link_params(intel_dp,
> -  pipe_config->port_clock,
> -  pipe_config->lane_count,
> -  true);
> -
> - intel_ddi_init_dp_buf_reg(_dig_port->base);
>  
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + /* Disable the PLL since we need to acquire the PLL
> +  * based on the link rate in the link training
> sequence
> +  */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate
> a
> +  *hotplug
> +  */
> + if (!(intel_ddi_link_train(intel_dp, pipe_config-
> >port_clock,
> +    pipe_config->lane_count,
> true,
> +    false)))
> + drm_kms_helper_hotplug_event(encoder-
> >base.dev);
> + pll->config = tmp_pll_config;
>  
> - intel_dp_start_link_train(intel_dp);
> - intel_dp_stop_link_train(intel_dp);
>   }
>  
>   ret = drm_dp_mst_allocate_vcpi(_dp->mst_mgr,
> @@ -336,6 +349,27 @@ intel_dp_mst_mode_valid(struct drm_connector
> *connector,
>   struct drm_display_mode *mode)
>  {
>   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> + struct intel_connector *intel_connector =
> to_intel_connector(connector);
> + struct intel_dp *intel_dp = intel_connector->mst_port;
> +
> + if (intel_dp->upfront_link_train && !intel_dp->upfront_done) 
> {
> + bool do_upfront_link_train;
> +
> + do_upfront_link_train = intel_dp-
> >compliance_test_type !=
> + DP_TEST_LINK_TRAINING;
> + if (do_upfront_link_train) {
> + intel_dp->upfront_done =
> + intel_dp_upfront_link_train(intel_dp
> );
> + if (intel_dp->upfront_done) {
> + DRM_DEBUG_KMS("MST upfront trained
> at "
> +   "%d lanes @ %d.",
> +   intel_dp-
> >max_lanes_upfront,
> +   intel_dp-
> >max_link_rate_upfront);
> + } else
> + DRM_DEBUG_KMS("MST upfront link
> training "
> +   "failed.");
Link training has failed and we have a blank screen. Should we throw an
error here? Maybe

return MODE_ERROR;

> + }
> + }
>  
>   /* TODO - validate mode against available PBN for link */
>   if (mode->clock < 1)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a2bbf68..34af3e8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1416,6 +1416,7 @@ void intel_edp_panel_off(struct intel_dp
> *intel_dp);
>  void intel_dp_add_properties(struct intel_dp *intel_dp, struct
> drm_connector *connector);
>  void intel_dp_mst_suspend(struct drm_device *dev);
>  void intel_dp_mst_resume(struct drm_device *dev);
> +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp);
>  int intel_dp_max_link_rate(struct intel_dp *intel_dp);
>  int intel_dp_link_rate_index(struct intel_dp *intel_dp, int
> *common_rates,
>    int link_rate);
> @@ -1448,6 +1449,8 @@ intel_dp_pre_emphasis_max(struct intel_dp
> *intel_dp, uint8_t voltage_swing);
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int
> port_clock,
>      uint8_t *link_bw, uint8_t *rate_select);
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> *common_rates);
> +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp);
>  bool
>  intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
> link_status[DP_LINK_STATUS_SIZE]);
>  
-- 
Mika Kahola - Intel OTC

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Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training

[Mika Kahola]

On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel EQ.
> In case of Channel EQ failures, it should fallback to
> lower link rate and lane count and start the CR phase again.
> 
> v2:
> * Add a helper function to return index of requested link rate
> into common_rates array
> * Changed the link rate fallback loop to make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 125
> +++---
>  drivers/gpu/drm/i915/intel_dp.c   |  15 
>  drivers/gpu/drm/i915/intel_dp_link_training.c |  12 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |   7 +-
>  4 files changed, 145 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 67a6a0b..e38bf4b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1634,19 +1634,18 @@ void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>   }
>  }
>  
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
>   int link_rate, uint32_t
> lane_count,
> - struct intel_shared_dpll *pll,
> - bool link_mst)
> + struct intel_shared_dpll *pll)
>  {
>   struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>   struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>   enum port port = intel_ddi_get_encoder_port(encoder);
>  
>   intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> -  link_mst);
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_edp_panel_on(intel_dp);
> +  false);
> +
> + intel_edp_panel_on(intel_dp);
>  
>   intel_ddi_clk_select(encoder, pll);
>   intel_prepare_dp_ddi_buffers(encoder);
> @@ -1657,6 +1656,29 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_dp_stop_link_train(intel_dp);
>  }
>  
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + int link_rate, uint32_t
> lane_count,
> + struct intel_shared_dpll *pll,
> + bool link_mst)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_shared_dpll_config tmp_pll_config;
> +
> + /* Disable the PLL and obtain the PLL for Link Training
> +  * that starts with highest link rate and lane count.
> +  */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate a
> hotplug */
> + if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst,
> +    false)))
> + drm_kms_helper_hotplug_event(encoder->base.dev);
> + pll->config = tmp_pll_config;
> +}
> +
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>     bool has_hdmi_sink,
>     struct drm_display_mode
> *adjusted_mode,
> @@ -1690,20 +1712,26 @@ static void intel_ddi_pre_enable(struct
> intel_encoder *intel_encoder,
>   struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>   int type = intel_encoder->type;
>  
> - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + if (type == INTEL_OUTPUT_EDP)
> + intel_ddi_pre_enable_edp(intel_encoder,
> + crtc->config->port_clock,
> + crtc->config->lane_count,
> + crtc->config->shared_dpll);
> +
> + if (type == INTEL_OUTPUT_DP)
>   intel_ddi_pre_enable_dp(intel_encoder,
>   crtc->config->port_clock,
>   crtc->config->lane_count,
>   crtc->confi

Re: [Intel-gfx] [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant

[Mika Kahola]

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Fri, 2016-09-02 at 22:05 +0300, Pandiyan, Dhinakaran wrote:
> On Fri, 2016-09-02 at 14:20 +0300, Mika Kahola wrote:
> > 
> > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > > 
> > > Fix the number of tries in channel euqalization link training
> > > sequence
> > > according to DP 1.2 Spec. It returns a boolean depending on
> > > channel
> > > equalization pass or failure.
> > > 
> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com
> > > >
> > > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp_link_training.c | 57 ++---
> > > 
> > > --
> > >  drivers/gpu/drm/i915/intel_drv.h  |  1 +
> > >  2 files changed, 22 insertions(+), 36 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > index 13a0341..07f0159 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > @@ -240,12 +240,12 @@ static u32 intel_dp_training_pattern(struct
> > > intel_dp *intel_dp)
> > >   return training_pattern;
> > >  }
> > >  
> > > -static void
> > > +static bool
> > >  intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >  {
> > > - bool channel_eq = false;
> > > - int tries, cr_tries;
> > > + int tries;
> > >   u32 training_pattern;
> > > + uint8_t link_status[DP_LINK_STATUS_SIZE];
> > >  
> > >   training_pattern = intel_dp_training_pattern(intel_dp);
> > >  
> > > @@ -254,20 +254,11 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >    training_pattern |
> > >    DP_LINK_SCRAMBLING_DISABLE)
> > > ) {
> > >   DRM_ERROR("failed to start channel
> > > equalization\n");
> > > - return;
> > > + return false;
> > >   }
> > >  
> > > - tries = 0;
> > > - cr_tries = 0;
> > > - channel_eq = false;
> > > - for (;;) {
> > > - uint8_t link_status[DP_LINK_STATUS_SIZE];
> > > -
> > > - if (cr_tries > 5) {
> > > - DRM_ERROR("failed to train DP,
> > > aborting\n");
> > > - intel_dp_dump_link_status(link_status);
> > > - break;
> > > - }
> > > + intel_dp->channel_eq_status = false;
> > > + for (tries = 0; tries < 5; tries++) {
> > >  
> > >   drm_dp_link_train_channel_eq_delay(intel_dp-
> > > >dpcd);
> > >   if (!intel_dp_get_link_status(intel_dp,
> > > link_status)) {
> > > @@ -278,44 +269,38 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >   /* Make sure clock is still ok */
> > >   if (!drm_dp_clock_recovery_ok(link_status,
> > >     intel_dp-
> > > >lane_count)) 
> > > {
> > > - intel_dp_link_training_clock_recovery(in
> > > tel_
> > > dp);
> > > - intel_dp_set_link_train(intel_dp,
> > > - training_pattern
> > > |
> > > - DP_LINK_SCRAMBLI
> > > NG_D
> > > ISABLE);
> > > - cr_tries++;
> > > - continue;
> > > + intel_dp_dump_link_status(link_status);
> > > + DRM_DEBUG_KMS("Clock recovery check
> > > failed,
> > > cannot "
> > > +   "continue channel
> > > equalization\n");
> > > + break;
> > >   }
> > This clock recovery check got me thinking. Do we really need to
> > check
> > if clock recovery is still ok within a loop? Could we move this
> > outside
> > the loop and return early if we have failed in clock recovery? One
> > idea
> > that I have in mind is that we wouldn't need to enter in channel
> > equalization if we have failed with clock recovery earlier.
>

Re: [Intel-gfx] [PATCH v2 9/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2

[Mika Kahola]

  if (voltage_tries == 5) {
> - DRM_ERROR("too many voltage retries,
> give up\n");
> - break;
> - }
> - } else
> - voltage_tries = 0;
>   voltage = intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK;
>  
>   /* Update training set as requested by target */
>   intel_get_adjust_train(intel_dp, link_status);
>   if (!intel_dp_update_link_train(intel_dp)) {
>       DRM_ERROR("failed to update link
> training\n");
> - break;
> + return false;
>   }
> +
> + if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) ==
> + voltage)
> + ++voltage_tries;
> + else
> + voltage_tries = 1;
> +
> + if (intel_dp_link_max_vswing_reached(intel_dp))
> + ++max_vswing_tries;
> +
>   }
>  }
>  
-- 
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Re: [Intel-gfx] [PATCH v2 8/14] drm/i915/dp: Move max. vswing check to it's own function

[Mika Kahola]

On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> 
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
> 
> v2:
> Fixed the Compiler warning (Mika Kahola)
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0deebed..b1eee5b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -112,6 +112,18 @@ intel_dp_update_link_train(struct intel_dp
> *intel_dp)
>   return ret == intel_dp->lane_count;
>  }
>  
> +static bool intel_dp_link_max_vswing_reached(struct intel_dp
> *intel_dp)
> +{
> + int lane;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++)
> + if (intel_dp->train_set[lane] &
> + (DP_TRAIN_MAX_SWING_REACHED == 0))
> + return false;
It seems that the parenthesis a misplaced here. I think you meant 

if ((intel_dp->train_set[lane] &
 DP_TRAIN_MAX_SWING_REACHED) == 0)
 
 
> +
> + return true;
> +}
> +
>  /* Enable corresponding port and start training pattern 1 */
>  static void
>  intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> @@ -170,10 +182,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>   }
>  
>   /* Check to see if we've tried the max voltage */
> - for (i = 0; i < intel_dp->lane_count; i++)
> - if ((intel_dp->train_set[i] &
> DP_TRAIN_MAX_SWING_REACHED) == 0)
> - break;
> - if (i == intel_dp->lane_count) {
> + if (intel_dp_link_max_vswing_reached(intel_dp)) {
>   ++loop_tries;
>   if (loop_tries == 5) {
>   DRM_ERROR("too many full retries,
> give up\n");
-- 
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Re: [Intel-gfx] [PATCH 08/14] drm/i915/dp: Move max. vswing check to it's own function

[Mika Kahola]

On Fri, 2016-09-02 at 11:05 +0300, Mika Kahola wrote:
> +1 for this cleanup
> 
> Reviewed-by: Mika Kahola <mika.kah...@intel.com>
Received couple of compiler warnings to be cleaned up

drivers/gpu/drm/i915/intel_dp_link_training.c: In function
‘intel_dp_link_max_vswing_reached’:
drivers/gpu/drm/i915/intel_dp_link_training.c:120:33: warning: suggest
parentheses around comparison in operand of ‘&’ [-Wparentheses]
   if (intel_dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED == 0)
 ^
drivers/gpu/drm/i915/intel_dp_link_training.c: In function
‘intel_dp_link_training_clock_recovery’:
drivers/gpu/drm/i915/intel_dp_link_training.c:130:6: warning: unused
variable ‘i’ [-Wunused-variable]

> 
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > 
> > From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > 
> > Wrap the max. vswing check in a separate function.
> > This makes the clock recovery phase of DP link training cleaner
> > 
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 16 ---
> > -
> >  1 file changed, 12 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 0deebed..9145e5a 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -112,6 +112,17 @@ intel_dp_update_link_train(struct intel_dp
> > *intel_dp)
> >     return ret == intel_dp->lane_count;
> >  }
> >  
> > +static bool intel_dp_link_max_vswing_reached(struct intel_dp
> > *intel_dp)
> > +{
> > +   int lane;
> > +
> > +   for (lane = 0; lane < intel_dp->lane_count; lane++)
> > +   if (intel_dp->train_set[lane] &
> > DP_TRAIN_MAX_SWING_REACHED == 0)
> > +   return false;
> > +
> > +   return true;
> > +}
> > +
> >  /* Enable corresponding port and start training pattern 1 */
> >  static void
> >  intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> > @@ -170,10 +181,7 @@ intel_dp_link_training_clock_recovery(struct
> > intel_dp *intel_dp)
> >     }
> >  
> >     /* Check to see if we've tried the max voltage */
> > -   for (i = 0; i < intel_dp->lane_count; i++)
> > -   if ((intel_dp->train_set[i] &
> > DP_TRAIN_MAX_SWING_REACHED) == 0)
> > -   break;
> > -   if (i == intel_dp->lane_count) {
> > +   if (intel_dp_link_max_vswing_reached(intel_dp)) {
> >     ++loop_tries;
> >     if (loop_tries == 5) {
> >     DRM_ERROR("too many full retries,
> > give up\n");
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Re: [Intel-gfx] [PATCH 12/14] drm/i915: Reverse the loop in intel_dp_compute_config

[Mika Kahola]

On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> While configuring the pipe during modeset, it should loop
> starting from max clock and max lane count reducing the
> lane count and clock in each iteration until the requested mode
> rate is less than or equal to available link BW.
> 
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 9 -
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index dfdbe65..e094b25 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1552,11 +1552,10 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>   for (; bpp >= 6*3; bpp -= 2*3) {
>   mode_rate = intel_dp_link_required(adjusted_mode-
> >crtc_clock,
>      bpp);
> -
> - for (clock = min_clock; clock <= max_clock; clock++)
> {
> - for (lane_count = min_lane_count;
> - lane_count <= max_lane_count;
> - lane_count <<= 1) {
> + for (clock = max_clock; clock >= max_clock; clock--)
The clock should be higher than or equal to min_clock.
> {
> + for (lane_count = max_lane_count;
> +  lane_count >= min_lane_count;
> +  lane_count >>= 1) {
>  
>           link_clock = common_rates[clock];
>   link_avail =
> intel_dp_max_data_rate(link_clock,
-- 
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Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

[Mika Kahola]

5/intel_dp_link_training.c
> @@ -309,9 +309,15 @@ void intel_dp_stop_link_train(struct intel_dp
> *intel_dp)
>   DP_TRAINING_PATTERN_DISABLE);
>  }
>  
> -void
> +bool
>  intel_dp_start_link_train(struct intel_dp *intel_dp)
>  {
> - intel_dp_link_training_clock_recovery(intel_dp);
> - intel_dp_link_training_channel_equalization(intel_dp);
> + bool ret;
> +
> + if (intel_dp_link_training_clock_recovery(intel_dp)) {
> + ret =
> intel_dp_link_training_channel_equalization(intel_dp);
> + if (ret)
> + return true;
> + }
> + return false;
yep, this is what I had in mind when I reviewed the previous patch.

>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e5bc976..342a2d5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1160,6 +1160,8 @@ void intel_ddi_clock_get(struct intel_encoder
> *encoder,
>    struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool
> state);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> +bool intel_ddi_link_train(struct intel_dp *intel_dp, int
> max_link_rate,
> +  uint8_t max_lane_count, bool link_mst);
>  struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp
> *intel_dp,
>     int clock);
>  unsigned int intel_fb_align_height(struct drm_device *dev,
> @@ -1381,7 +1383,7 @@ bool intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
>     int link_rate, uint8_t lane_count,
>     bool link_mst);
> -void intel_dp_start_link_train(struct intel_dp *intel_dp);
> +bool intel_dp_start_link_train(struct intel_dp *intel_dp);
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp);
>  void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
>  void intel_dp_encoder_reset(struct drm_encoder *encoder);
-- 
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Re: [Intel-gfx] [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant

[Mika Kahola]

>   if (!intel_dp_update_link_train(intel_dp)) {
>   DRM_ERROR("failed to update link
> training\n");
>   break;
>   }
> - ++tries;
> + }
> +
> + /* Try 5 times, else fail and try at lower BW */
> + if (tries == 5) {
> + intel_dp_dump_link_status(link_status);
> + DRM_DEBUG_KMS("Channel equalization failed 5
> times\n");
>   }
>  
>   intel_dp_set_idle_link_train(intel_dp);
>  
> - if (channel_eq)
> - DRM_DEBUG_KMS("Channel EQ done. DP Training
> successful\n");
> + return intel_dp->channel_eq_status;
> +
>  }
>  
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index efcd80b..e5bc976 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -878,6 +878,7 @@ struct intel_dp {
>   bool link_mst;
>   bool has_audio;
>   bool detect_done;
> + bool channel_eq_status;
>   enum hdmi_force_audio force_audio;
>   bool limited_color_range;
>   bool color_range_auto;
-- 
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Re: [Intel-gfx] [PATCH 09/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2

[Mika Kahola]

at
there would be separate debug messages when reaching max vswing or
trying out the same voltage for five times.

>  
> - /* Check to see if we've tried the same voltage 5
> times */
> - if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
> - ++voltage_tries;
> - if (voltage_tries == 5) {
> - DRM_ERROR("too many voltage retries,
> give up\n");
> - break;
> - }
> - } else
> - voltage_tries = 0;
>   voltage = intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK;
>  
>   /* Update training set as requested by target */
>   intel_get_adjust_train(intel_dp, link_status);
>   if (!intel_dp_update_link_train(intel_dp)) {
>   DRM_ERROR("failed to update link
> training\n");
> - break;
> + return false;
>   }
> +
> + if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) ==
> + voltage)
> + ++voltage_tries;
> + else
> + voltage_tries = 1;
> +
> + if (intel_dp_link_max_vswing_reached(intel_dp))
> + ++max_vswing_tries;
> +
>   }
>  }
>  
-- 
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Re: [Intel-gfx] [PATCH 08/14] drm/i915/dp: Move max. vswing check to it's own function

[Mika Kahola]

+1 for this cleanup

Reviewed-by: Mika Kahola <mika.kah...@intel.com>

On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> 
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0deebed..9145e5a 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -112,6 +112,17 @@ intel_dp_update_link_train(struct intel_dp
> *intel_dp)
>   return ret == intel_dp->lane_count;
>  }
>  
> +static bool intel_dp_link_max_vswing_reached(struct intel_dp
> *intel_dp)
> +{
> + int lane;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++)
> + if (intel_dp->train_set[lane] &
> DP_TRAIN_MAX_SWING_REACHED == 0)
> + return false;
> +
> + return true;
> +}
> +
>  /* Enable corresponding port and start training pattern 1 */
>  static void
>  intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> @@ -170,10 +181,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
>   }
>  
>   /* Check to see if we've tried the max voltage */
> - for (i = 0; i < intel_dp->lane_count; i++)
> - if ((intel_dp->train_set[i] &
> DP_TRAIN_MAX_SWING_REACHED) == 0)
> - break;
> - if (i == intel_dp->lane_count) {
> + if (intel_dp_link_max_vswing_reached(intel_dp)) {
>   ++loop_tries;
>   if (loop_tries == 5) {
>   DRM_ERROR("too many full retries,
> give up\n");
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Re: [Intel-gfx] [PATCH] drm/i915/dp: add lane_count check in intel_dp_check_link_status

[Mika Kahola]

On Sat, 2016-08-27 at 14:33 +0100, Matthew Auld wrote:
> Currently it's entirely possible to go through the link training step
> without first determining the lane_count, which is silly since we end
> up
> doing a bunch of aux transfers of size = 0, as highlighted by
> WARN_ON(!msg->buffer != !msg->size), and can only ever result in a
> 'failed to update link training' message. This can be observed during
> intel_dp_long_pulse where we can do the link training step, but
> before
> we have had a chance to set the link params. To avoid this we add an
> extra check for the lane_count in intel_dp_check_link_status, which
> should prevent us from doing the link training step prematurely.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=97344
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Signed-off-by: Matthew Auld <matthew.a...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index a3c7dd8..0dbb672 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3927,6 +3927,9 @@ intel_dp_check_link_status(struct intel_dp
> *intel_dp)
>   if (!to_intel_crtc(intel_encoder->base.crtc)->active)
>   return;
>  
> + if (!intel_dp->lane_count)
> + return;
> +
>   /* if link training is requested we should perform it always
> */
>   if ((intel_dp->compliance_test_type ==
> DP_TEST_LINK_TRAINING) ||
>   (!drm_dp_channel_eq_ok(link_status, intel_dp-
> >lane_count))) {

Should we place this check as part drm_dp_helper()'s
drm_dp_channel_eq_ok() routine as this may happen with other than our
i915 driver as well?

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[Intel-gfx] [PATCH v8 11/12] drm: Add DP branch device info on debugfs

[Mika Kahola]

Read DisplayPort branch device info from through debugfs
interface.

v2: use drm_dp_helper routines to collect data
v3: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v4: move DP branch device info to function 'intel_dp_branch_device_info()'
v5: initial step to move debugging info from intel_dp. to drm_dp_helper.c 
(Daniel)
v6: read hw and sw revision without using specific drm_dp_helper routines

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 81 +
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ++
 include/drm/drm_dp_helper.h |  2 +
 3 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 01ee7af..23cd6dc 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -526,6 +526,87 @@ int drm_dp_downstream_id(struct drm_dp_aux *aux, char 
id[6])
 }
 EXPORT_SYMBOL(drm_dp_downstream_id);
 
+/**
+ * drm_dp_downstream_debug() - debug DP branch devices
+ * @m: pointer for debugfs file
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @aux: DisplayPort AUX channel
+ *
+ */
+void drm_dp_downstream_debug(struct seq_file *m, const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4], struct drm_dp_aux *aux)
+{
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+   int clk;
+   int bpc;
+   char id[6];
+   int len;
+   uint8_t rev[2];
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 
DP_DWN_STRM_PORT_PRESENT;
+
+   seq_printf(m, "\tDP branch device present: %s\n", branch_device ? "yes" 
: "no");
+
+   if (!branch_device)
+   return;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_DP:
+   seq_printf(m, "\t\tType: DisplayPort\n");
+   break;
+   case DP_DS_PORT_TYPE_VGA:
+   seq_printf(m, "\t\tType: VGA\n");
+   break;
+   case DP_DS_PORT_TYPE_DVI:
+   seq_printf(m, "\t\tType: DVI\n");
+   break;
+   case DP_DS_PORT_TYPE_HDMI:
+   seq_printf(m, "\t\tType: HDMI\n");
+   break;
+   case DP_DS_PORT_TYPE_NON_EDID:
+   seq_printf(m, "\t\tType: others without EDID support\n");
+   break;
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   seq_printf(m, "\t\tType: DP++\n");
+   break;
+   case DP_DS_PORT_TYPE_WIRELESS:
+   seq_printf(m, "\t\tType: Wireless\n");
+   break;
+   default:
+   seq_printf(m, "\t\tType: N/A\n");
+   }
+
+   drm_dp_downstream_id(aux, id);
+   seq_printf(m, "\t\tID: %s\n", id);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, [0], 1);
+   if (len > 0)
+   seq_printf(m, "\t\tHW: %d.%d\n", (rev[0] & 0xf0) >> 4, rev[0] & 
0xf);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, , 2);
+   if (len > 0)
+   seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
+
+   if (detailed_cap_info) {
+   clk = drm_dp_downstream_max_clock(dpcd, port_cap);
+
+   if (clk > 0) {
+   if (type == DP_DS_PORT_TYPE_VGA)
+   seq_printf(m, "\t\tMax dot clock: %d kHz\n", 
clk);
+   else
+   seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", 
clk);
+   }
+
+   bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
+
+   if (bpc > 0)
+   seq_printf(m, "\t\tMax bpc: %d\n", bpc);
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_debug);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 01ae5ee..90c736f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2923,6 +2923,9 @@ static void intel_dp_info(struct seq_file *m,
seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
intel_panel_info(m, _connector->panel);
+
+   drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
+   _dp->aux);
 }
 
 static void intel_hdmi_info(struct seq_file *m,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 215202f..2a79882 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -823,6 +823,8 @@ int drm_dp_downstream_max_clock(const u8 

[Intel-gfx] [PATCH v8 09/12] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
v5: Use of intel_dp->downstream_ports to read out port capabilities.
Code restructuring (Ville)
v6: Move DP branch device check to drm_dp_helper.c (Daniel)
v7: Cleanup as suggested by Ville

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ffb79..25f459e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10;
 }
 
+static int
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int max_dotclk = dev_priv->max_dotclk_freq;
+   int ds_max_dotclk;
+
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_VGA)
+   return max_dotclk;
+
+   ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   if (ds_max_dotclk != 0)
+   max_dotclk = min(max_dotclk, ds_max_dotclk);;
+
+   return max_dotclk;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
-   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+   int max_dotclk;
+
+   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
-- 
1.9.1

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[Intel-gfx] [PATCH v8 10/12] drm/i915: Update bits per component for display info

[Mika Kahola]

DisplayPort branch device may define max supported bits per
component. Update display info based on this value if bpc
is defined.

v2: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v3: Fill bpc for connector's display info in separate
drm_dp_helper function (Daniel)
v4: remove updating bpc for display info as it may be overridden
when parsing EDID. Instead, check bpc for DP branch device
during compute_config

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 25f459e..17110d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1524,6 +1524,20 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, 
int port_clock,
}
 }
 
+int intel_dp_compute_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
+{
+   int bpp, bpc;
+
+   bpp = pipe_config->pipe_bpp;
+   bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, 
intel_dp->downstream_ports);
+
+   if (bpc > 0)
+   bpp = min(bpp, 3*bpc);
+
+   return bpp;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@@ -1589,7 +1603,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 * bpc in between. */
-   bpp = pipe_config->pipe_bpp;
+   bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
+
if (is_edp(intel_dp)) {
 
/* Get bpp from vbt only for panels that dont have bpp in edid 
*/
-- 
1.9.1

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[Intel-gfx] [PATCH v8 07/12] drm/i915: Read DP branch device HW revision

[Mika Kahola]

HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print HW revision info to dmesg (Ville)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3dab3bf..9aebdf6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1419,6 +1419,25 @@ static void intel_dp_print_rates(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
+static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev;
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_HW_REV, , 1);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4282,6 +4301,8 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
 
intel_dp_probe_oui(intel_dp);
 
+   intel_dp_print_hw_revision(intel_dp);
+
intel_dp_configure_mst(intel_dp);
 
if (intel_dp->is_mst) {
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index faea76b..19ac599 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -446,6 +446,7 @@
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
+#define DP_BRANCH_HW_REV0x509
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
1.9.1

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[Intel-gfx] [PATCH v8 02/12] drm: Drop VGA from bpc definitions

[Mika Kahola]

Drop "VGA" from bits per component definitions as these
are also used by other standards such as DVI, HDMI,
DP++.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 include/drm/drm_dp_helper.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ba9731e..0d84046 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -216,11 +216,11 @@
 # define DP_DS_PORT_HPD(1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-# define DP_DS_VGA_MAX_BPC_MASK(3 << 0)
-# define DP_DS_VGA_8BPC0
-# define DP_DS_VGA_10BPC   1
-# define DP_DS_VGA_12BPC   2
-# define DP_DS_VGA_16BPC   3
+# define DP_DS_MAX_BPC_MASK(3 << 0)
+# define DP_DS_8BPC0
+# define DP_DS_10BPC   1
+# define DP_DS_12BPC   2
+# define DP_DS_16BPC   3
 
 /* link configuration */
 #defineDP_LINK_BW_SET  0x100
-- 
1.9.1

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[Intel-gfx] [PATCH v8 00/12] drm/i915: DP branch devices

[Mika Kahola]

Prep work for DP branch device handling

This series of patches reads DPCD register 0x80h for receiver
capabilities for DP branch devices. The branch device types are
converters for the following standards

 - DP to VGA
 - DP to DVI
 - DP to HDMI
 - DP++ dual mode
 - Wireless WiGig
 
DPCD register defines max pixel rate for VGA dongles. This
check is carried out during mode validation. 

[1] git://github.com/mkahola/drm-intel-mika.git dp_branch_device

v2: DPCD register read outs moved to drm (Ville, Daniel)
v3: Max pixel rate computation moved to drm (Daniel)
v4: Use of drm_dp_helper routines to collect data (Ville)
v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville)
v6: Rebase and i915_debugfs cleanup
v7: Structure cleanups and initial step to move DP debugging info to 
drm_dp_helpers
v8: Cleanups and TMDS clock frequency check for HDMI adapter

Mika Kahola (12):
  drm: Add missing DP downstream port types
  drm: Drop VGA from bpc definitions
  drm: Helper to read max clock rate
  drm: Helper to read max bits per component
  drm: Read DP branch device id
  drm/i915: Cleanup DisplayPort AUX channel initialization
  drm/i915: Read DP branch device HW revision
  drm/i915: Read DP branch device SW revision
  drm/i915: Check pixel rate for DP to VGA dongle
  drm/i915: Update bits per component for display info
  drm: Add DP branch device info on debugfs
  drm/i915: Check TMDS clock DP to HDMI dongle

 drivers/gpu/drm/drm_dp_helper.c | 168 
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +
 drivers/gpu/drm/i915/intel_dp.c |  89 ++-
 drivers/gpu/drm/i915/intel_drv.h|   3 +
 drivers/gpu/drm/i915/intel_hdmi.c   |  27 ++
 include/drm/drm_dp_helper.h |  22 +++--
 6 files changed, 303 insertions(+), 9 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

[Mika Kahola]

Respect max TMDS clock frequency from DPCD for active
DP to HDMI adapters.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  3 +++
 drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c700b0..b7fd551 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -817,6 +817,9 @@ struct intel_hdmi {
i915_reg_t hdmi_reg;
int ddc_bus;
struct {
+   int max_tmds_clock;
+   } dp_to_hdmi;
+   struct {
enum drm_dp_dual_mode_type type;
int max_tmds_clock;
} dp_dual_mode;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 4df9f38..1469d00 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1204,6 +1204,9 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
 
if (respect_downstream_limits) {
+   if (hdmi->dp_to_hdmi.max_tmds_clock)
+   max_tmds_clock = min(max_tmds_clock,
+hdmi->dp_to_hdmi.max_tmds_clock);
if (hdmi->dp_dual_mode.max_tmds_clock)
max_tmds_clock = min(max_tmds_clock,
 hdmi->dp_dual_mode.max_tmds_clock);
@@ -1373,11 +1376,33 @@ intel_hdmi_unset_edid(struct drm_connector *connector)
intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
 
+   intel_hdmi->dp_to_hdmi.max_tmds_clock = 0;
+
kfree(to_intel_connector(connector)->detect_edid);
to_intel_connector(connector)->detect_edid = NULL;
 }
 
 static void
+intel_hdmi_dp_adapter_detect(struct drm_connector *connector)
+{
+   struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+   struct intel_digital_port *intel_dig_port =
+   hdmi_to_dig_port(intel_hdmi);
+   struct intel_dp *intel_dp = _dig_port->dp;
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_HDMI)
+   return;
+
+   intel_hdmi->dp_to_hdmi.max_tmds_clock =
+   drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   DRM_DEBUG_KMS("DP HDMI adaptor detected (max TMDS clock : %d kHz\n",
+ intel_hdmi->dp_to_hdmi.max_tmds_clock);
+}
+
+static void
 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
 {
struct drm_i915_private *dev_priv = to_i915(connector->dev);
@@ -1438,6 +1463,8 @@ intel_hdmi_set_edid(struct drm_connector *connector, bool 
force)
 
intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
 
+   intel_hdmi_dp_adapter_detect(connector);
+
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
}
 
-- 
1.9.1

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[Intel-gfx] [PATCH v8 03/12] drm: Helper to read max clock rate

[Mika Kahola]

Helper routine to read out maximum supported pixel rate
for DisplayPort legay VGA converter or TMDS clock rate
for other digital legacy converters. The helper returns
clock rate in kHz.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 33 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 031c4d3..7497490 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -439,6 +439,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct 
drm_dp_link *link)
 }
 EXPORT_SYMBOL(drm_dp_link_configure);
 
+/**
+ * drm_dp_downstream_max_clock() - extract branch device max
+ * pixel rate for legacy VGA
+ * converter or max TMDS clock
+ * rate for others
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max clock in kHz on success or 0 if max clock not defined
+ */
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   return port_cap[1] * 8 * 1000;
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   return port_cap[1] * 2500;
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_clock);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0d84046..60dd9dc 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -815,6 +815,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 01/12] drm: Add missing DP downstream port types

[Mika Kahola]

Add missing DisplayPort downstream port types. The introduced
new port types are DP++ and Wireless.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 include/drm/drm_dp_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 63b8bd5..ba9731e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -211,6 +211,8 @@
 # define DP_DS_PORT_TYPE_DVI   2
 # define DP_DS_PORT_TYPE_HDMI  3
 # define DP_DS_PORT_TYPE_NON_EDID  4
+# define DP_DS_PORT_TYPE_DP_DUALMODE5
+# define DP_DS_PORT_TYPE_WIRELESS   6
 # define DP_DS_PORT_HPD(1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-- 
1.9.1

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[Intel-gfx] [PATCH v8 08/12] drm/i915: Read DP branch device SW revision

[Mika Kahola]

SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x50A.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print SW revision info to dmesg (Ville)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 20 
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9aebdf6..91ffb79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1438,6 +1438,25 @@ static void intel_dp_print_hw_revision(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
 }
 
+static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev[2];
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_SW_REV, , 2);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4302,6 +4321,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp_probe_oui(intel_dp);
 
intel_dp_print_hw_revision(intel_dp);
+   intel_dp_print_sw_revision(intel_dp);
 
intel_dp_configure_mst(intel_dp);
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 19ac599..215202f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -447,6 +447,7 @@
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
 #define DP_BRANCH_HW_REV0x509
+#define DP_BRANCH_SW_REV0x50A
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
1.9.1

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[Intel-gfx] [PATCH v8 05/12] drm: Read DP branch device id

[Mika Kahola]

Read DisplayPort branch device id string.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 12 
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 14e8ea0..01ee7af 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -514,6 +514,18 @@ int drm_dp_downstream_max_bpc(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 
+/**
+ * drm_dp_downstream_id() - identify branch device
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns branch device id on success or NULL on failure
+ */
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
+{
+   return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
+}
+EXPORT_SYMBOL(drm_dp_downstream_id);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f3d1424..faea76b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,7 @@
 #define DP_SOURCE_OUI  0x300
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
+#define DP_BRANCH_ID0x503
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
@@ -819,6 +820,7 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  const u8 port_cap[4]);
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 09/12] Check pixel rate for DP to VGA dongle

[Mika Kahola]

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
v5: Use of intel_dp->downstream_ports to read out port capabilities.
Code restructuring (Ville)
v6: Move DP branch device check to drm_dp_helper.c (Daniel)
v7: Cleanup as suggested by Ville

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ffb79..25f459e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10;
 }
 
+static int
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int max_dotclk = dev_priv->max_dotclk_freq;
+   int ds_max_dotclk;
+
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_VGA)
+   return max_dotclk;
+
+   ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   if (ds_max_dotclk != 0)
+   max_dotclk = min(max_dotclk, ds_max_dotclk);;
+
+   return max_dotclk;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
-   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+   int max_dotclk;
+
+   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
-- 
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[Intel-gfx] [PATCH v8 04/12] drm: Helper to read max bits per component

[Mika Kahola]

Helper routine to read out maximum supported bits per
component for DisplayPort legay converters.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 42 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 7497490..14e8ea0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -472,6 +472,48 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
 
+/**
+ * drm_dp_downstream_max_bpc() - extract branch device max
+ *   bits per component
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max bpc on success or 0 if max bpc not defined
+ */
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+   int bpc;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
+
+   switch (bpc) {
+   case DP_DS_8BPC:
+   return 8;
+   case DP_DS_10BPC:
+   return 10;
+   case DP_DS_12BPC:
+   return 12;
+   case DP_DS_16BPC:
+   return 16;
+   }
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 60dd9dc..f3d1424 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -817,6 +817,8 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 06/12] drm/i915: Cleanup DisplayPort AUX channel initialization

[Mika Kahola]

Let's remove reference to "struct intel_connector *connector"
in intel_dp_aux_init() function as it is no longer required.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 364db90..3dab3bf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1243,7 +1243,7 @@ intel_dp_aux_fini(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
+intel_dp_aux_init(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->port;
@@ -5598,7 +5598,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->interlace_allowed = true;
connector->doublescan_allowed = 0;
 
-   intel_dp_aux_init(intel_dp, intel_connector);
+   intel_dp_aux_init(intel_dp);
 
INIT_DELAYED_WORK(_dp->panel_vdd_work,
  edp_panel_vdd_work);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 12/12] drm/i915: Check TMDS clock DP to HDMI dongle

[Mika Kahola]

Respect max TMDS clock frequency from DPCD for active
DP to HDMI adapters.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  3 +++
 drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c700b0..b7fd551 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -817,6 +817,9 @@ struct intel_hdmi {
i915_reg_t hdmi_reg;
int ddc_bus;
struct {
+   int max_tmds_clock;
+   } dp_to_hdmi;
+   struct {
enum drm_dp_dual_mode_type type;
int max_tmds_clock;
} dp_dual_mode;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 4df9f38..1469d00 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1204,6 +1204,9 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
 
if (respect_downstream_limits) {
+   if (hdmi->dp_to_hdmi.max_tmds_clock)
+   max_tmds_clock = min(max_tmds_clock,
+hdmi->dp_to_hdmi.max_tmds_clock);
if (hdmi->dp_dual_mode.max_tmds_clock)
max_tmds_clock = min(max_tmds_clock,
 hdmi->dp_dual_mode.max_tmds_clock);
@@ -1373,11 +1376,33 @@ intel_hdmi_unset_edid(struct drm_connector *connector)
intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
 
+   intel_hdmi->dp_to_hdmi.max_tmds_clock = 0;
+
kfree(to_intel_connector(connector)->detect_edid);
to_intel_connector(connector)->detect_edid = NULL;
 }
 
 static void
+intel_hdmi_dp_adapter_detect(struct drm_connector *connector)
+{
+   struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+   struct intel_digital_port *intel_dig_port =
+   hdmi_to_dig_port(intel_hdmi);
+   struct intel_dp *intel_dp = _dig_port->dp;
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_HDMI)
+   return;
+
+   intel_hdmi->dp_to_hdmi.max_tmds_clock =
+   drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   DRM_DEBUG_KMS("DP HDMI adaptor detected (max TMDS clock : %d kHz\n",
+ intel_hdmi->dp_to_hdmi.max_tmds_clock);
+}
+
+static void
 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
 {
struct drm_i915_private *dev_priv = to_i915(connector->dev);
@@ -1438,6 +1463,8 @@ intel_hdmi_set_edid(struct drm_connector *connector, bool 
force)
 
intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
 
+   intel_hdmi_dp_adapter_detect(connector);
+
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
}
 
-- 
1.9.1

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[Intel-gfx] [PATCH v8 10/12] drm/i915: Update bits per component for display info

[Mika Kahola]

DisplayPort branch device may define max supported bits per
component. Update display info based on this value if bpc
is defined.

v2: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v3: Fill bpc for connector's display info in separate
drm_dp_helper function (Daniel)
v4: remove updating bpc for display info as it may be overridden
when parsing EDID. Instead, check bpc for DP branch device
during compute_config

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 25f459e..17110d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1524,6 +1524,20 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, 
int port_clock,
}
 }
 
+int intel_dp_compute_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
+{
+   int bpp, bpc;
+
+   bpp = pipe_config->pipe_bpp;
+   bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, 
intel_dp->downstream_ports);
+
+   if (bpc > 0)
+   bpp = min(bpp, 3*bpc);
+
+   return bpp;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@@ -1589,7 +1603,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 * bpc in between. */
-   bpp = pipe_config->pipe_bpp;
+   bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
+
if (is_edp(intel_dp)) {
 
/* Get bpp from vbt only for panels that dont have bpp in edid 
*/
-- 
1.9.1

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[Intel-gfx] [PATCH v8 11/12] drm: Add DP branch device info on debugfs

[Mika Kahola]

Read DisplayPort branch device info from through debugfs
interface.

v2: use drm_dp_helper routines to collect data
v3: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
v4: move DP branch device info to function 'intel_dp_branch_device_info()'
v5: initial step to move debugging info from intel_dp. to drm_dp_helper.c 
(Daniel)
v6: read hw and sw revision without using specific drm_dp_helper routines

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 81 +
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ++
 include/drm/drm_dp_helper.h |  2 +
 3 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 01ee7af..23cd6dc 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -526,6 +526,87 @@ int drm_dp_downstream_id(struct drm_dp_aux *aux, char 
id[6])
 }
 EXPORT_SYMBOL(drm_dp_downstream_id);
 
+/**
+ * drm_dp_downstream_debug() - debug DP branch devices
+ * @m: pointer for debugfs file
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @aux: DisplayPort AUX channel
+ *
+ */
+void drm_dp_downstream_debug(struct seq_file *m, const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4], struct drm_dp_aux *aux)
+{
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+   int clk;
+   int bpc;
+   char id[6];
+   int len;
+   uint8_t rev[2];
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 
DP_DWN_STRM_PORT_PRESENT;
+
+   seq_printf(m, "\tDP branch device present: %s\n", branch_device ? "yes" 
: "no");
+
+   if (!branch_device)
+   return;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_DP:
+   seq_printf(m, "\t\tType: DisplayPort\n");
+   break;
+   case DP_DS_PORT_TYPE_VGA:
+   seq_printf(m, "\t\tType: VGA\n");
+   break;
+   case DP_DS_PORT_TYPE_DVI:
+   seq_printf(m, "\t\tType: DVI\n");
+   break;
+   case DP_DS_PORT_TYPE_HDMI:
+   seq_printf(m, "\t\tType: HDMI\n");
+   break;
+   case DP_DS_PORT_TYPE_NON_EDID:
+   seq_printf(m, "\t\tType: others without EDID support\n");
+   break;
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   seq_printf(m, "\t\tType: DP++\n");
+   break;
+   case DP_DS_PORT_TYPE_WIRELESS:
+   seq_printf(m, "\t\tType: Wireless\n");
+   break;
+   default:
+   seq_printf(m, "\t\tType: N/A\n");
+   }
+
+   drm_dp_downstream_id(aux, id);
+   seq_printf(m, "\t\tID: %s\n", id);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, [0], 1);
+   if (len > 0)
+   seq_printf(m, "\t\tHW: %d.%d\n", (rev[0] & 0xf0) >> 4, rev[0] & 
0xf);
+
+   len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, , 2);
+   if (len > 0)
+   seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
+
+   if (detailed_cap_info) {
+   clk = drm_dp_downstream_max_clock(dpcd, port_cap);
+
+   if (clk > 0) {
+   if (type == DP_DS_PORT_TYPE_VGA)
+   seq_printf(m, "\t\tMax dot clock: %d kHz\n", 
clk);
+   else
+   seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", 
clk);
+   }
+
+   bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
+
+   if (bpc > 0)
+   seq_printf(m, "\t\tMax bpc: %d\n", bpc);
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_debug);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 01ae5ee..90c736f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2923,6 +2923,9 @@ static void intel_dp_info(struct seq_file *m,
seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
intel_panel_info(m, _connector->panel);
+
+   drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
+   _dp->aux);
 }
 
 static void intel_hdmi_info(struct seq_file *m,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 215202f..2a79882 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -823,6 +823,8 @@ int drm_dp_downstream_max_clock(const u8 

[Intel-gfx] [PATCH v8 09/12] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
v5: Use of intel_dp->downstream_ports to read out port capabilities.
Code restructuring (Ville)
v6: Move DP branch device check to drm_dp_helper.c (Daniel)
v7: Cleanup as suggested by Ville

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ffb79..25f459e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10;
 }
 
+static int
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int max_dotclk = dev_priv->max_dotclk_freq;
+   int ds_max_dotclk;
+
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_VGA)
+   return max_dotclk;
+
+   ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   if (ds_max_dotclk != 0)
+   max_dotclk = min(max_dotclk, ds_max_dotclk);;
+
+   return max_dotclk;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
-   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+   int max_dotclk;
+
+   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
-- 
1.9.1

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[Intel-gfx] [PATCH v8 09/12] Check pixel rate for DP to VGA dongle

[Mika Kahola]

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
v5: Use of intel_dp->downstream_ports to read out port capabilities.
Code restructuring (Ville)
v6: Move DP branch device check to drm_dp_helper.c (Daniel)
v7: Cleanup as suggested by Ville

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ffb79..25f459e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10;
 }
 
+static int
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int max_dotclk = dev_priv->max_dotclk_freq;
+   int ds_max_dotclk;
+
+   int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+
+   if (type != DP_DS_PORT_TYPE_VGA)
+   return max_dotclk;
+
+   ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
+   intel_dp->downstream_ports);
+
+   if (ds_max_dotclk != 0)
+   max_dotclk = min(max_dotclk, ds_max_dotclk);;
+
+   return max_dotclk;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
-   int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+   int max_dotclk;
+
+   max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
-- 
1.9.1

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[Intel-gfx] [PATCH v8 08/12] drm/i915: Read DP branch device SW revision

[Mika Kahola]

SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x50A.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print SW revision info to dmesg (Ville)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 20 
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9aebdf6..91ffb79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1438,6 +1438,25 @@ static void intel_dp_print_hw_revision(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
 }
 
+static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev[2];
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_SW_REV, , 2);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4302,6 +4321,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp_probe_oui(intel_dp);
 
intel_dp_print_hw_revision(intel_dp);
+   intel_dp_print_sw_revision(intel_dp);
 
intel_dp_configure_mst(intel_dp);
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 19ac599..215202f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -447,6 +447,7 @@
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
 #define DP_BRANCH_HW_REV0x509
+#define DP_BRANCH_SW_REV0x50A
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
1.9.1

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[Intel-gfx] [PATCH v8 07/12] drm/i915: Read DP branch device HW revision

[Mika Kahola]

HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.

v2: move drm_dp_ds_revision structure to be part of
drm_dp_link structure (Daniel)
v3: remove dependency to drm_dp_helper but instead parse
DPCD and print HW revision info to dmesg (Ville)

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +
 include/drm/drm_dp_helper.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3dab3bf..9aebdf6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1419,6 +1419,25 @@ static void intel_dp_print_rates(struct intel_dp 
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
+static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
+{
+   uint8_t rev;
+   int len;
+
+   if ((drm_debug & DRM_UT_KMS) == 0)
+   return;
+
+   if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_PRESENT))
+   return;
+
+   len = drm_dp_dpcd_read(_dp->aux, DP_BRANCH_HW_REV, , 1);
+   if (len < 0)
+   return;
+
+   DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 
0xf);
+}
+
 static int rate_to_index(int find, const int *rates)
 {
int i = 0;
@@ -4282,6 +4301,8 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
 
intel_dp_probe_oui(intel_dp);
 
+   intel_dp_print_hw_revision(intel_dp);
+
intel_dp_configure_mst(intel_dp);
 
if (intel_dp->is_mst) {
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index faea76b..19ac599 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -446,6 +446,7 @@
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
 #define DP_BRANCH_ID0x503
+#define DP_BRANCH_HW_REV0x509
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
-- 
1.9.1

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[Intel-gfx] [PATCH v8 06/12] drm/i915: Cleanup DisplayPort AUX channel initialization

[Mika Kahola]

Let's remove reference to "struct intel_connector *connector"
in intel_dp_aux_init() function as it is no longer required.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 364db90..3dab3bf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1243,7 +1243,7 @@ intel_dp_aux_fini(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
+intel_dp_aux_init(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->port;
@@ -5598,7 +5598,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->interlace_allowed = true;
connector->doublescan_allowed = 0;
 
-   intel_dp_aux_init(intel_dp, intel_connector);
+   intel_dp_aux_init(intel_dp);
 
INIT_DELAYED_WORK(_dp->panel_vdd_work,
  edp_panel_vdd_work);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 05/12] drm: Read DP branch device id

[Mika Kahola]

Read DisplayPort branch device id string.

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 12 
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 14e8ea0..01ee7af 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -514,6 +514,18 @@ int drm_dp_downstream_max_bpc(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 
+/**
+ * drm_dp_downstream_id() - identify branch device
+ * @aux: DisplayPort AUX channel
+ *
+ * Returns branch device id on success or NULL on failure
+ */
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
+{
+   return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
+}
+EXPORT_SYMBOL(drm_dp_downstream_id);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f3d1424..faea76b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,7 @@
 #define DP_SOURCE_OUI  0x300
 #define DP_SINK_OUI0x400
 #define DP_BRANCH_OUI  0x500
+#define DP_BRANCH_ID0x503
 
 #define DP_SET_POWER0x600
 # define DP_SET_POWER_D00x1
@@ -819,6 +820,7 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  const u8 port_cap[4]);
+int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 03/12] drm: Helper to read max clock rate

[Mika Kahola]

Helper routine to read out maximum supported pixel rate
for DisplayPort legay VGA converter or TMDS clock rate
for other digital legacy converters. The helper returns
clock rate in kHz.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 33 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 031c4d3..7497490 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -439,6 +439,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct 
drm_dp_link *link)
 }
 EXPORT_SYMBOL(drm_dp_link_configure);
 
+/**
+ * drm_dp_downstream_max_clock() - extract branch device max
+ * pixel rate for legacy VGA
+ * converter or max TMDS clock
+ * rate for others
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max clock in kHz on success or 0 if max clock not defined
+ */
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   return port_cap[1] * 8 * 1000;
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   return port_cap[1] * 2500;
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_clock);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0d84046..60dd9dc 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -815,6 +815,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+   const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 04/12] drm: Helper to read max bits per component

[Mika Kahola]

Helper routine to read out maximum supported bits per
component for DisplayPort legay converters.

v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)

Reviewed-by: Jim Bride <jim.br...@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 42 +
 include/drm/drm_dp_helper.h |  2 ++
 2 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 7497490..14e8ea0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -472,6 +472,48 @@ int drm_dp_downstream_max_clock(const u8 
dpcd[DP_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
 
+/**
+ * drm_dp_downstream_max_bpc() - extract branch device max
+ *   bits per component
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Returns max bpc on success or 0 if max bpc not defined
+ */
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
+{
+   int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
+   bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+   DP_DETAILED_CAP_INFO_AVAILABLE;
+   int bpc;
+
+   if (!detailed_cap_info)
+   return 0;
+
+   switch (type) {
+   case DP_DS_PORT_TYPE_VGA:
+   case DP_DS_PORT_TYPE_DVI:
+   case DP_DS_PORT_TYPE_HDMI:
+   case DP_DS_PORT_TYPE_DP_DUALMODE:
+   bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
+
+   switch (bpc) {
+   case DP_DS_8BPC:
+   return 8;
+   case DP_DS_10BPC:
+   return 10;
+   case DP_DS_12BPC:
+   return 12;
+   case DP_DS_16BPC:
+   return 16;
+   }
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
+
 /*
  * I2C-over-AUX implementation
  */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 60dd9dc..f3d1424 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -817,6 +817,8 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct 
drm_dp_link *link);
 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
+int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4]);
 
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
-- 
1.9.1

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