As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
pll programming (Gustavo)
Clear calibration banks for both lanes (Gustavo)
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 266 +++---
.../gpu/drm/i915
based on changes in BSpec consolidated table
v3: Rename intel_c20_read() to intel_c20_sram_read() (Gustavo)
Use context and correct MPLLA reg bit to select if MPLLA is in
use or not (Gustavo)
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display
Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5
two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
64603
Cc: Matt Atwood
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
d
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 139 ++
1 file changed
programming (Khaled)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
interrupts
Imre Deak (1):
drm/i915/mtl: TypeC HPD live status query
Mika Kahola (15):
drm/i915/mtl: Add DP rates
drm/i915/mtl: Create separate reg file for PICA registers
drm/i915/mtl: Add support for PM DEMAND
drm/i915/mtl: C20 PLL programming
drm/i915/mtl: C20 HW readout
drm/i915/mtl
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
tcss power request with correct parameter.
v3: Use de variant for register wait (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117 ++-
2 files changed, 114 insertions(+), 5 deletions
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 136
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915
based on changes in BSpec consolidated table
v3: Rename intel_c20_read() to intel_c20_sram_read() (Gustavo)
Use context and correct MPLLA reg bit to select if MPLLA is in
use or not (Gustavo)
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display
Calculate port clock with C20 phy.
v2: Initialize parameters
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 65
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to
two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
pll programming (Gustavo)
Clear calibration banks for both lanes (Gustavo)
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 266 +++---
.../gpu/drm/i915
programming (Khaled)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43
Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
table updates
PICA hotplug handling updates
v4: Initialize parameters for C20 port clock calculation
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Gustavo Sousa (1):
drm/i915/mtl: Define mask
Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
na Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 6 +
.../drm/i915/display/intel_displ
tcss power request with correct parameter.
v3: Use de variant for register wait (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117 ++-
2 files changed, 114 insertions(+), 5 deletions
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
based on changes in BSpec consolidated table
v3: Rename intel_c20_read() to intel_c20_sram_read() (Gustavo)
Use context and correct MPLLA reg bit to select if MPLLA is in
use or not (Gustavo)
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 136
pll programming (Gustavo)
Clear calibration banks for both lanes (Gustavo)
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 266 +++---
.../gpu/drm/i915
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
programming (Khaled)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 65 insertions(+), 5 deletions
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
table updates
PICA hotplug handling updates
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak (1):
drm/i915/mtl
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
tcss power request with correct parameter.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-20-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
Link:
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-17-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-16-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Link:
https://patchwork.freedesktop.org/patch
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-15-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++-
drivers/gpu/drm/i915/display
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-14-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-12-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++
1 file changed, 10 insertions
based on changes in BSpec consolidated table
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-10-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 495 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-11-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Link
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.
two times of level 1 preemphasis 0.
Fix this in the driver code as well.
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-7-mika.kah...
with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika
() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-5-mika.kah...@intel.com
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-3-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-2-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file
PHY programming support for PICA C10 and C20 Type-C chips.
v2: Move intel_cx0_reg_defs.h to intel_cx0_phy_regs.h (Jani)
Move pmdemand as part of intel_display structure
PLL table updates
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 31 -
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 4 +++
.../drm/i915/display
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 115 ++-
2 files changed, 112 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display
-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 143 --
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 6 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
3 files changed, 33 insertions(+), 5 deletions
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 139
with something more general purpose.
Bspec: 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 168 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
() with port instead of phy (Lucas)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1090 +
drivers/gpu/drm
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to
Create a separate file to store registers for PICA chips
C10 and C20.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display
PHY programming support for C10 and C20 Type-C chips. This series
includes fixes for previously sent C10 series.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Gustavo Sousa (1):
drm/i915/mtl
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
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