Re: [Intel-gfx] [PATCH v7 3/5] drm/i915: Check pixel rate for DP to VGA dongle

On Thu, 2016-08-11 at 12:56 +0200, Daniel Vetter wrote: > On Thu, Aug 11, 2016 at 01:51:42PM +0300, Ville Syrjälä wrote: > > On Thu, Aug 11, 2016 at 12:43:39PM +0300, Mika Kahola wrote: > > > On Thu, 2016-08-11 at 10:18 +0300, Ville Syrjälä wrote: > > > > On Mon, Au

Re: [Intel-gfx] [PATCH v7 3/5] drm/i915: Check pixel rate for DP to VGA dongle

On Thu, 2016-08-11 at 10:18 +0300, Ville Syrjälä wrote: > On Mon, Aug 08, 2016 at 04:00:28PM +0300, Mika Kahola wrote: > > Filter out a mode that exceeds the max pixel rate setting > > for DP to VGA dongle. This is defined in DPCD register 0x81 > > if detailed cap info i.e.

Re: [Intel-gfx] [PATCH v7 1/5] drm: Read DP branch device HW revision

On Thu, 2016-08-11 at 10:10 +0300, Ville Syrjälä wrote: > On Mon, Aug 08, 2016 at 04:00:26PM +0300, Mika Kahola wrote: > > HW revision is mandatory field for DisplayPort branch > > devices. This is defined in DPCD register field 0x509. > > But what do we want to do wit

[Intel-gfx] [PATCH] drm/i915: Cleanup DisplayPort AUX channel initialization

Let's remove reference to "struct intel_connector *connector" from intel_dp_aux_init() function as it is no longer required. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --g

[Intel-gfx] [PATCH v7 4/5] drm: Update bits per component for display info

(Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 24 drivers/gpu/drm/i915/intel_dp.c | 3 +++ include/drm/drm_dp_helper.h | 4 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_help

[Intel-gfx] [PATCH v7 5/5] drm: Add DP branch device info on debugfs

to move debugging info from intel_dp. to drm_dp_helper.c (Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 80 + drivers/gpu/drm/i915/i915_debugfs.c | 2 + include/drm/drm_dp_helper.h | 2 + 3

[Intel-gfx] [PATCH v7 3/5] drm/i915: Check pixel rate for DP to VGA dongle

lle) v6: Move DP branch device check to drm_dp_helper.c (Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu

[Intel-gfx] [PATCH v7 0/5] drm/i915: DP branch devices

routines to collect data (Ville) v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville) v6: Rebase and i915_debugfs cleanup v7: Structure cleanups and initial step to move DP debugging info to drm_dp_helpers Mika Kahola (5): drm: Read DP branch device HW revision drm: Read DP

[Intel-gfx] [PATCH v7 2/5] drm: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v7 1/5] drm: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. v2: move drm_dp_ds_revision structure to be part of drm_dp_link structure (Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c

Re: [Intel-gfx] [PATCH v6 09/10] drm/i915: Update bits per component for display info

On Tue, 2016-07-12 at 15:51 +0200, Daniel Vetter wrote: > On Wed, Jul 06, 2016 at 02:04:53PM +0300, Mika Kahola wrote: > > DisplayPort branch device may define max supported bits per > > component. Update display info based on this value if bpc > > is defined. > >

Re: [Intel-gfx] [PATCH v6 08/10] drm/i915: Check pixel rate for DP to VGA dongle

On Tue, 2016-07-12 at 15:50 +0200, Daniel Vetter wrote: > On Wed, Jul 06, 2016 at 02:04:52PM +0300, Mika Kahola wrote: > > Filter out a mode that exceeds the max pixel rate setting > > for DP to VGA dongle. This is defined in DPCD register 0x81 > > if detailed cap info i.e.

Re: [Intel-gfx] [PATCH v6 06/10] drm: Read DP branch device HW revision

On Tue, 2016-07-12 at 15:54 +0200, Daniel Vetter wrote: > On Wed, Jul 06, 2016 at 02:04:50PM +0300, Mika Kahola wrote: > > HW revision is mandatory field for DisplayPort branch > > devices. This is defined in DPCD register field 0x509. > > > > Signed-off-by: Mika Ka

[Intel-gfx] [PATCH v6 06/10] drm: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 21 + include/drm/drm_dp_helper.h | 7 +++ 2 files chang

[Intel-gfx] [PATCH v6 10/10] drm/i915: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data v3: cleanup to match the drm_dp_helper.c patches introduced earlier in this series v4: move DP branch device info to function 'intel_dp_branch_device_info()' Signed-off-by: Mika

[Intel-gfx] [PATCH v6 08/10] drm/i915: Check pixel rate for DP to VGA dongle

lle) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ffa43ec..76a654e 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH v6 00/10] drm/i915: DP branch devices

rate computation moved to drm (Daniel) v4: Use of drm_dp_helper routines to collect data (Ville) v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville) v6: Rebase and i915_debugfs cleanup Mika Kahola (10): drm: Add missing DP downstream port types drm: Drop VGA from bpc

[Intel-gfx] [PATCH v6 03/10] drm: Helper to read max clock rate

) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 33 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 0

[Intel-gfx] [PATCH v6 09/10] drm/i915: Update bits per component for display info

DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. v2: cleanup to match the drm_dp_helper.c patches introduced earlier in this series Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/dr

[Intel-gfx] [PATCH v6 05/10] drm: Read DP branch device id

Read DisplayPort branch device id string. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 12 include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/g

[Intel-gfx] [PATCH v6 07/10] drm: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 21 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 23 inse

[Intel-gfx] [PATCH v6 02/10] drm: Drop VGA from bpc definitions

Drop "VGA" from bits per component definitions as these are also used by other standards such as DVI, HDMI, DP++. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --g

[Intel-gfx] [PATCH v6 01/10] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_he

[Intel-gfx] [PATCH v6 04/10] drm: Helper to read max bits per component

Helper routine to read out maximum supported bits per component for DisplayPort legay converters. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/g

[Intel-gfx] [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature

: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Reviewed-by: Jani Nikula <jani.nik...@intel.com> Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 --- drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++

[Intel-gfx] [PATCH] drm/i915: Revert DisplayPort fast link training feature

It has been turned out that in some HW combination the DisplayPort fast link training feature caused screen flickering. Let's revert this feature for now until we can ensure that the feature works for all platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika

[Intel-gfx] [PATCH v5 07/10] drm: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 21 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 23 inse

[Intel-gfx] [PATCH v5 03/10] drm: Helper to read max clock rate

) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 33 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index e

[Intel-gfx] [PATCH v5 01/10] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_he

[Intel-gfx] [PATCH v5 10/10] drm/i915: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data v3: cleanup to match the drm_dp_helper.c patches introduced earlier in this series Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_deb

[Intel-gfx] [PATCH v5 08/10] drm/i915: Check pixel rate for DP to VGA dongle

lle) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f97cd53..3b09230 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH v5 05/10] drm: Read DP branch device id

Read DisplayPort branch device id string. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 12 include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/g

[Intel-gfx] [PATCH v5 09/10] drm/i915: Update bits per component for display info

DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. v2: cleanup to match the drm_dp_helper.c patches introduced earlier in this series Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/dr

[Intel-gfx] [PATCH v5 02/10] drm: Drop VGA from bpc definitions

Drop "VGA" from bits per component definitions as these are also used by other standards such as DVI, HDMI, DP++. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --g

[Intel-gfx] [PATCH v5 06/10] drm: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 21 + include/drm/drm_dp_helper.h | 7 +++ 2 files chang

[Intel-gfx] [PATCH v5 04/10] drm: Helper to read max bits per component

Helper routine to read out maximum supported bits per component for DisplayPort legay converters. v2: Return early if detailed port cap info is not available. Replace if-else ladder with switch-case (Ville) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/g

[Intel-gfx] [PATCH v5 00/10] drm/i915: DP branch devices

(Daniel) v4: Use of drm_dp_helper routines to collect data (Ville) v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville) Mika Kahola (10): drm: Add missing DP downstream port types drm: Drop VGA from bpc definitions drm: Helper to read max clock rate drm: Helper to read

Re: [Intel-gfx] [PATCH v4 05/11] drm: Helper to read max bits per component

On Thu, 2016-06-09 at 11:02 +0300, Ville Syrjälä wrote: > On Mon, Jun 06, 2016 at 04:29:07PM +0300, Mika Kahola wrote: > > Helper routine to read out maximum supported bits per > > component for DisplayPort legay converters. > > > > Signed-off-by: Mika Ka

[Intel-gfx] [PATCH v4 07/11] drm: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 21 + include/drm/drm_dp_helper.h | 7 +++ 2 files chang

[Intel-gfx] [PATCH v4 11/11] drm/i915: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. v2: use drm_dp_helper routines to collect data Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 66 + 1 file changed, 66 insertions(+) diff

[Intel-gfx] [PATCH v4 02/11] drm: Read DP downstream port capabilities

Read DisplayPort downstream port capabilities. Depending on the DP port the capabilities are defined in length of 1 byte or 4 bytes depending if the detailed capability information is available. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v4 05/11] drm: Helper to read max bits per component

Helper routine to read out maximum supported bits per component for DisplayPort legay converters. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 31 +++ include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 33 inse

[Intel-gfx] [PATCH v4 06/11] drm: Read DP branch device id

Read DisplayPort branch device id string. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 12 include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/g

[Intel-gfx] [PATCH v4 04/11] drm: Helper to read max clock rate

Helper routine to read out maximum supported pixel rate for DisplayPort legay VGA converter or TMDS clock rate for other digital legacy converters. The helper returns clock rate in kHz. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v4 03/11] drm: Helper to read DP branch device type

-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 14 ++ include/drm/drm_dp_helper.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index c4149fd..7d3b245 100644 --- a/drivers/g

[Intel-gfx] [PATCH v4 09/11] drm/i915: Check pixel rate for DP to VGA dongle

and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.

[Intel-gfx] [PATCH v4 01/11] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_he

[Intel-gfx] [PATCH v4 10/11] drm/i915: Update bits per component for display info

DisplayPort branch device may define max supported bits per component. Update display info based on this value if bpc is defined. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 12 1 file changed, 12 insertions(+) diff --git a/drive

[Intel-gfx] [PATCH v4 08/11] drm: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 22 ++ include/drm/drm_dp_helper.h | 4 +++- 2 files chang

[Intel-gfx] [PATCH v4 00/11] drm/i915: DP branch devices

(Daniel) v4: Use of drm_dp_helper routines to collect data (Ville) Mika Kahola (11): drm: Add missing DP downstream port types drm: Read DP downstream port capabilities drm: Helper to read DP branch device type drm: Helper to read max clock rate drm: Helper to read max bits per component drm

Re: [Intel-gfx] [PATCH] drm/i915: Extract physical display dimensions from VBT

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2016-05-31 at 12:08 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The VBT has these mysterious H/V image sizes as part of the display > timings. Looking at

[Intel-gfx] [PATCH v3 11/12] drm/i915: Read DP branch device SW revision

SW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x50A. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 5 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 7 insertions(+) diff

[Intel-gfx] [PATCH v3 07/12] drm: Compute max pixel rate for DP sink

For DP branch devices DPCD register may define the max supported pixel rate for VGA dongles. This patch adds a check if DPCD register value is less than current setting for pixel rate. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v3 10/12] drm/i915: Read DP branch device HW revision

HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 5 + include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 7 insertions(+) diff

[Intel-gfx] [PATCH v3 06/12] drm: Read DPCD receiver capability for DP to Wireless Converter

active Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 7 +++ include/drm/drm_dp_helper.h | 13 + 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index f98e4be..2

[Intel-gfx] [PATCH v3 09/12] drm/i915: Read DP branch device id

Read device ID for DisplayPort branch devices. The device ID is defined in DPCD register 0x503 and it is mandatory field for DP branch devices. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 6 ++ include/drm/drm_dp_helper.h | 2 ++ 2

[Intel-gfx] [PATCH v3 04/12] drm: Read DPCD receiver capability for DP to HDMI converter

pass through - support for conversion from YCBCR444 to YCBCR422 - support for conversion from YCBCR444 to YCBCR420 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 8 include/drm/drm_dp_helper.h | 19 +++ 2 files chang

[Intel-gfx] [PATCH v3 05/12] drm: Read DPCD receiver capability for DP++

Read from DPCD receiver capability field for the DP++ devices. The features are - max TMDS charachter clock - max bits per component - support for conversion from 3D frame sequential to frame pack Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v3 12/12] drm/i915: Add DP branch device info on debugfs

Read DisplayPort branch device info from through debugfs interface. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 37 + 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/d

[Intel-gfx] [PATCH v3 03/12] drm: Read DPCD receiver capability for DP to DVI converter

Read from DPCD receiver capability field for the following features: - max TMDS clock rate - max bits per component - single or dual link support - high color depth support Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 5 + inclu

[Intel-gfx] [PATCH v3 08/12] drm/i915: Check pixel rate for DP to VGA dongle

rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 7 +++ 1 file chan

[Intel-gfx] [PATCH v3 02/12] drm: Read DPCD receiver capability for DP to VGA converter

Read from DPCD receiver capability field the max allowed pixel clock and bits per component for DP to VGA converter. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 46 drivers/gpu/drm/i915/intel_drv.

[Intel-gfx] [PATCH v3 00/12] drm/i915: DP branch devices

(Ville, Daniel) v3: Max pixel rate computation moved to drm (Daniel) Mika Kahola (12): drm: Add missing DP downstream port types drm: Read DPCD receiver capability for DP to VGA converter drm: Read DPCD receiver capability for DP to DVI converter drm: Read DPCD receiver capability for DP to HDMI

[Intel-gfx] [PATCH v3 01/12] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_he

[Intel-gfx] [PATCH v2 3/7] drm: Read DPCD receiver capability for DP to DVI converter

Read from DPCD receiver capability field for the following features: - max TMDS clock rate - max bits per component - single or dual link support - high color depth support Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 5 + inclu

[Intel-gfx] [PATCH v2 5/7] drm: Read DPCD receiver capability for DP++

Read from DPCD receiver capability field for the DP++ devices. The features are - max TMDS charachter clock - max bits per component - support for conversion from 3D frame sequential to frame pack Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.

[Intel-gfx] [PATCH v2 7/7] drm/i915: Check pixel rate for DP to VGA dongle

rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/dr

[Intel-gfx] [PATCH v2 1/7] drm: Add missing DP downstream port types

Add missing DisplayPort downstream port types. The introduced new port types are DP++ and Wireless. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_he

[Intel-gfx] [PATCH v2 6/7] drm: Read DPCD receiver capability for DP to Wireless Converter

active Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 7 +++ include/drm/drm_dp_helper.h | 13 + 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index f98e4be..2

[Intel-gfx] [PATCH v2 2/7] drm: Read DPCD receiver capability for DP to VGA converter

Read from DPCD receiver capability field the max allowed pixel clock and bits per component for DP to VGA converter. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 46 drivers/gpu/drm/i915/intel_drv.

[Intel-gfx] [PATCH v2 0/7] drm/i915: DP branch devices

defines max pixel rate for VGA dongles. This check is carried out during mode validation. Acronyms: DFPDownstream-Facing Port v2: DPCD register read outs moved to drm (Ville, Daniel) Mika Kahola (7): drm: Add missing DP downstream port types drm: Read DPCD receiver capability for DP

[Intel-gfx] [PATCH v2 4/7] drm: Read DPCD receiver capability for DP to HDMI converter

pass through - support for conversion from YCBCR444 to YCBCR422 - support for conversion from YCBCR444 to YCBCR420 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 8 include/drm/drm_dp_helper.h | 19 +++ 2 files chang

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

On Tue, 2016-05-03 at 16:28 +0200, Daniel Vetter wrote: > On Tue, May 03, 2016 at 04:23:34PM +0300, Ville Syrjälä wrote: > > On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote: > > > Prep work to improve DP branch device handling. > > > > > > Filter o

[Intel-gfx] [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

rate divided by 8 in MP/s. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 34 ++ drivers/gpu/drm/i915/intel_drv.h | 9 + 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drive

[Intel-gfx] [PATCH 2/3] drm: Add DP port types from DP 1.3 specification

DP specification 1.3 defines DP downstream ports for DP++ and wireless devices. Let's add these to port definitions. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- include/drm/drm_dp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/inclu

[Intel-gfx] [PATCH 0/3] drm/i915: DP branch devices

This series of patches reads either pixel rate or TMDS clock rate from DPCD. Pixel rate is defined for DP to VGA dongles and TMDS clock rate for others except wireless dongle. The mode that requires either higher pixel rate or TMDS clock rate are filtered out during the mode validity check. Mika

[Intel-gfx] [PATCH 3/3] drm/i915: Check HDMI TMDS clock rate from DPCD

Read TMDS clock rate from DPCD for HDMI to filter out modes that might require higher TMDS clock rate than supported. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix comments about GMBUSFREQ register

s/Programmng/Programming With this nitpick fixed, this is Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2016-04-26 at 19:46 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The comment about GMBUSFREQ

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use cached cdclk value in i915_audio_component_get_cdclk_freq()

Looks reasonable. Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2016-04-26 at 19:46 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > No point in reading the cdclk out from the hardware every single time >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

Indeed, BSpec says that this register should be programmed by CD clock minus one. Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2016-04-26 at 19:46 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Update CD

[Intel-gfx] [PATCH v3] drm/i915: Fix eDP low vswing for Broadwell

the DDI translations table for DP instead of eDP (low vswing) table. v2: Combine two if statements into one (Jani) v3: Change dev_priv->edp_low_vswing to use dev_priv->vbt.edp.low_vswing Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94087 Signed-off-by: Mika Kahola <mika.kah...@

Re: [Intel-gfx] [RESEND FOR CI PATCH v2] drm/i915: Fix eDP low vswing for Broadwell

CI hasn't catch this patch for testing? On Wed, 2016-04-13 at 12:11 +0300, Mika Kahola wrote: > It was noticed on bug #94087 that module parameter > i915.edp_vswing=2 that should override the VBT setting > to use default voltage swing (400 mV) was not applied > for Broadwell. >

[Intel-gfx] [PATCH] drm/i915: Cache DisplayPort link signal levels

is trained until the signal levels of previus link training is achieved and clock recovery is achieved. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 1 + drivers/gpu/dr

[Intel-gfx] [RESEND FOR CI PATCH v2] drm/i915: Fix eDP low vswing for Broadwell

the DDI translations table for DP instead of eDP (low vswing) table. v2: Combine two if statements into one (Jani) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94087 Signed-off-by: Mika Kahola <mika.kah...@intel.com> Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix eDP low vswing for Broadwell

On Mon, 2016-04-11 at 16:30 +0300, Ville Syrjälä wrote: > On Thu, Mar 17, 2016 at 12:23:10PM +0200, Mika Kahola wrote: > > It was noticed on bug #94087 that module parameter > > i915.edp_vswing=2 that should override the VBT setting > > to use default voltage swing (40

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support

atic inline enum port intel_dsi_seq_port_to_port(u8 port) > { > return port ? PORT_C : PORT_A; > @@ -305,6 +936,40 @@ static void chv_exec_gpio(struct drm_i915_private > *dev_priv, > mutex_unlock(_priv->sb_lock); > } > > +static void bxt_exec_gpio(struct drm_i915_private *dev_priv, > + u8 gpio_source, u8 gpio_index, u8 action) > +{ > + struct bxt_gpio_map *map = NULL; > + unsigned int gpio; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(bxt_gpio_table); i++) { > + if (gpio_index == bxt_gpio_table[i].gpio_index) { > + map = _gpio_table[i]; > + break; > + } > + } > + > + if (!map) { > + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); > + return; > + } > + > + gpio = map->gpio_number; > + > + if (!map->requested) { > + int ret = devm_gpio_request_one(dev_priv->dev->dev, gpio, > + GPIOF_DIR_OUT, "MIPI DSI"); > + if (ret) { > + DRM_ERROR("unable to request GPIO %u (%d)\n", gpio, > ret); > + return; > + } > + map->requested = true; > + } > + > + gpio_set_value(gpio, action); > +} > + > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -330,7 +995,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi > *intel_dsi, const u8 *data) > else if (IS_CHERRYVIEW(dev_priv)) > chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); > else > - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > + bxt_exec_gpio(dev_priv, gpio_source, gpio_index, action); Should we check for BXT platform here before entering to gpio routine and if not BXT in question leave the debug message as is? > return data; > } -- Mika Kahola - Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Fix eDP low vswing for Broadwell

the DDI translations table for DP instead of eDP (low vswing) table. v2: Combine two if statements into one (Jani) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94087 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 12 ++-- 1 file c

Re: [Intel-gfx] [PATCH] drm/i915: Fix eDP low vswing for Broadwell

On Wed, 2016-03-16 at 11:49 +0200, Jani Nikula wrote: > On Wed, 16 Mar 2016, Mika Kahola <mika.kah...@intel.com> wrote: > > [ text/plain ] > > It was noticed on bug #94087 that module parameter > > i915.edp_vswing=2 that should override the VBT setting > > to

[Intel-gfx] [PATCH] drm/i915: Fix eDP low vswing for Broadwell

the DDI translations table for DP instead of eDP (low vswing) table. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94087 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff

Re: [Intel-gfx] [PATCH] drm/i915: Add delay on DPCD reads

On Tue, 2016-03-15 at 14:26 +0100, Daniel Vetter wrote: > On Tue, Mar 15, 2016 at 01:38:58PM +0200, Mika Kahola wrote: > > Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326 > > DP to VGA adapter. Having said that, I haven't noticed a need for > > addition

[Intel-gfx] [PATCH] drm/i915: Add delay on DPCD reads

Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326 DP to VGA adapter. Having said that, I haven't noticed a need for additional delay between DPCD reads on other DP-VGA dongles. While at it, let's replace mdelay() with usleep_range() routine. Signed-off-by: Mika Kahola

Re: [Intel-gfx] [PATCH 1/3 V2] drm/i915: Using the bpp value wrt the pixel format

e...@intel.com> > > Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com> > > Signed-off-by: Ramalingam C <ramalinga...@intel.com> Tested-by: Mika Kahola <mika.kah...@intel.com> Tested on BYT, Asus T100 > Reviewed-by: Jani Nikula <jani.nik...@int

[Intel-gfx] [PATCH] drm/i915: Skip DDI PLL selection for DSI

Skip DDI PLL selection if display type is DSI/MIPI. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/dr

Re: [Intel-gfx] [PATCH] drm/i915/BXT: Configure DSI after enabling DSI pll

On Wed, 2016-02-03 at 11:27 +0200, Jani Nikula wrote: > On Wed, 03 Feb 2016, "Thulasimani, Sivakumar" > wrote: > > just realized that intel_dsi_init is not called from setup outputs for > > BXT. is this expected ? > > if so when is it expected to be added ? > >

Re: [Intel-gfx] [PATCH] drm/i915/BXT: Configure DSI after enabling DSI pll

On Wed, 2016-02-03 at 11:28 +0200, Jani Nikula wrote: > On Tue, 02 Feb 2016, Ramalingam C wrote: > > We need to enable DSI PLL before configuring the DSI registers. > > > > Signed-off-by: Ramalingam C > > --- > > drivers/gpu/drm/i915/intel_dsi.c |

Re: [Intel-gfx] [PATCH] drm/i915/BXT: Configure DSI after enabling DSI pll

This change is needed to enable DSI/MIPI display on BXT Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2016-02-02 at 23:21 +0530, Ramalingam C wrote: > We need to enable DSI PLL before configuring the DSI registers. > > Signed-off-by: Ramalingam C <rama

[Intel-gfx] [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check

. V2: - removed computation for max DOT clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk renamed as max_dotclk Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/d

[Intel-gfx] [PATCH v4 0/6] Check pixel clock when setting mode

is renamed as max_dotclk throughout the whole series Mika Kahola (6): drm/i915: DisplayPort pixel clock check drm/i915: HDMI pixel clock check drm/i915: DisplayPort-MST pixel clock check drm/i915: SDVO pixel clock check drm/i915: CRT pixel clock check drm/i915: TV pixel clock check d

[Intel-gfx] [PATCH v4 3/6] drm/i915: DisplayPort-MST pixel clock check

MST. V2: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp_mst.c | 5 + 1 file changed, 5 insertions(+) diff

[Intel-gfx] [PATCH v4 4/6] drm/i915: SDVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_sdvo.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/g

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