[Intel-gfx] [PATCH 12/14] drm/i915: BDW clock change support

rate. v2: Grab rps.hw_lock around sandybridge_pcode_write() v3: Rebase due to power well vs. .global_resources() reordering Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v4: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 09/14] drm/i915: Don't enable IPS when pixel rate exceeds 95%

cdclk insted of the current cdclk Tested-by: Timo Aaltonen tjaal...@ubuntu.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497 Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v4: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 05/14] drm/i915: Cache current cdclk frequency in dev_priv

to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 40 +++- 2 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm

[Intel-gfx] [PATCH 03/14] drm/i915: Add cdclk extraction for g33, g965gm and g4x

. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com V2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c | 183 ++- 2 files changed, 185 insertions

[Intel-gfx] [PATCH 04/14] drm/i915: Warn when cdclk for the platforms is not known

. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 08/14] drm/i915: Store max cdclk value in dev_priv

ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 20 +++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers

[Intel-gfx] [PATCH 07/14] drm/i915: Unify ilk and hsw .get_aux_clock_divider

ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 23 +++ 1 file changed, 3 insertions

[Intel-gfx] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that have been reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches include modifications to drm/i915: Fix i855_get_display_clock_speed() drm/i915: Fix 852GM/GMV cdclk

[Intel-gfx] [PATCH 01/14] drm/i915: Fix i855 get_display_clock_speed

Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 11 --- drivers/gpu/drm/i915/intel_display.c | 15 --- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 10/14] drm/i915: HSW cdclk support

ville.syrj...@linux.intel.com v3: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c | 140 ++- 2 files changed, 140 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 06/14] drm/i915: Use cached cdclk value

Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 13/14] drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 09f3518..d79421a

[Intel-gfx] [PATCH 14/14] drm/i915: Modeset global_pipes() update

-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 70 +--- 1 file changed, 32 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d79421a..f199faa 100644

[Intel-gfx] [PATCH 02/14] drm/i915: Fix 852GM/GMV cdclk

-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 71123c7

Re: [Intel-gfx] All sort of cdclk stuff

Hi, I forgot to update authorships. I'll fix this and resend the patch series. Thanks for pointing this out! -Mika- On Wed, 2015-04-15 at 14:16 +0100, Damien Lespiau wrote: Hi Mika, On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote: This patch series rebases Ville's original

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

for the update Mika. The issue will be that audio plays faster or slower than normal. i.e it will be 1x or 1x. can you confirm if audible sound plays after CD Clock change at 1x speed ? regards, Sivakumar On 4/14/2015 12:06 PM, Mika Kahola wrote: I tested this patch with the audio in place

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

I tested this patch with the audio in place. With this setup in my HSW machine I can hear the pink noise played back with DP-HDMI cable attatched. speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7 Cheers, Mika On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote: where

[Intel-gfx] (no subject)

This series is revised based on Jani's good comments. In this series the patch which read out DP link training parameters from VBT is discarded as based on the comments that I received. Files changed: drivers/gpu/drm/i915/intel_dp.c drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 1/2] drm/i915: DP link training optimization

training parameters are set to zero and training is restarted. V2: - flag that indicates if DP link is trained and valid renamed from 'link_trained' to 'train_set_valid' - removed routine 'intel_dp_reuse_link_train' Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 2/2] drm/i915: DP link training optimization

This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote: At Fri, 10 Apr 2015 16:27:39 +0300, Mika Kahola wrote: On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote: At Thu, 9 Apr 2015 15:51:27 +0200, Daniel Vetter wrote: On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

:52 +0200, Daniel Vetter wrote: On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote: Definitely a good idea to check the audio part as well if there is a doubt that by changing CD clock the audio would fail. I can check this and I'll get back once I have the results. We force

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote: On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote: I did some testing on audio part with HDMI-HDMI and DP-HDMI cables connected to my Haswell box. Before applying the patch I tested as a reference with the latest -nightly (04

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

Definitely a good idea to check the audio part as well if there is a doubt that by changing CD clock the audio would fail. I can check this and I'll get back once I have the results. Cheers, Mika On Tue, Apr 07, 2015 at 02:06:50PM +0530, Sivakumar Thulasimani wrote: where can i check this

[Intel-gfx] [PATCH 19/19] drm/i915: Modeset global_pipes() update

routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' v3: - Let's take a step back and not remove the routines 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' from newly introduced routine 'intel_calc_cdclk()' (based on Ville's comment) Signed-off-by: Mika Kahola mika.kah

Re: [Intel-gfx] [PATCH 19/19] drm/i915: Modeset global_pipes() update

On Tue, Mar 31, 2015 at 05:45:56PM +0300, Ville Syrjälä wrote: On Tue, Mar 31, 2015 at 02:14:23PM +0300, Mika Kahola wrote: Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()' into one function 'intel_modeset_global_pipes()' Signed-off-by: Mika Kahola mika.kah

[Intel-gfx] [PATCH 19/19] drm/i915: Modeset global_pipes() update

routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 191 --- 1 file changed, 88 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] All sort of cdclk stuff

()' -- Mika Kahola, Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 12/19] drm/i915: Unify ilk and hsw .get_aux_clock_divider

ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 23 +++ 1 file changed, 3 insertions

[Intel-gfx] [PATCH 10/19] drm/i915: Cache current cdclk frequency in dev_priv

Rather that extracting the current cdclk freuqncy every time someone wants to know it, cache the current value and use that. VLV/CHV already stored a cached value there so just expand that to cover all platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika

[Intel-gfx] [PATCH 13/19] drm/i915: Store max cdclk value in dev_priv

ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 20 +++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers

[Intel-gfx] [PATCH 14/19] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk

cdclk insted of the current cdclk Tested-by: Timo Aaltonen tjaal...@ubuntu.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497 Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 31

[Intel-gfx] [PATCH 11/19] drm/i915: Use cached cdclk value

Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 17/19] drm/i915: BDW clock change support

rate. v2: Grab rps.hw_lock around sandybridge_pcode_write() v3: Rebase due to power well vs. .global_resources() reordering v4: Rebase due to .global_resources() reordering for BDW Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers

[Intel-gfx] [PATCH 19/19] drm/i915: Modeset global_pipes() update

Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()' into one function 'intel_modeset_global_pipes()' Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 89 +--- 1 file changed, 41 insertions(+), 48

[Intel-gfx] [PATCH 18/19] drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 736df3e..5ed40df

[Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

to .global_resources() reordering for Haswell Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c | 161 ++- 2 files changed, 161 insertions

[Intel-gfx] [PATCH 16/19] drm/i915: Add IS_BDW_ULX

We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 01/19] drm/i915: Return more precise cdclk for gen2/3

Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's not clear if these are accurate frquencies or just in the ballpark, but without docs this is the best we can do. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com

[Intel-gfx] [PATCH 02/19] drm/i915: Fix i855 get_display_clock_speed

Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 11 --- drivers/gpu/drm/i915/intel_display.c | 15 --- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 04/19] drm/i915: Add cdclk extraction for g33, g965gm and g4x

. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c | 186 ++- 2 files changed, 185 insertions(+), 4 deletions(-) diff

[Intel-gfx] [PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed

Unify the HSW/BDW/SKL cdclk extraction code to conform to the same .get_display_clock_speed() mold that all the other platforms use. v2: Update due to SKL code getting added Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers

[Intel-gfx] [PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider

Now that we are extracting the cdclk frequency on ILK-IVB we can also simplify ilk_get_aux_clock_divider() to calculate the divider based on cdclk instead of hardcoding the values. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com

[Intel-gfx] [PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz

couldn't verify what the BIOS used, so this notion is purely based on our current code, Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 3/3] drm/i915: DP link training optimization

This patch adds fast link training support if BDB version is equal or higher than 182 and the feature is supported in VBT. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 4 drivers/gpu/drm/i915/intel_bios.h

[Intel-gfx] [PATCH 2/3] drm/i915: DP link training optimization

Generalization to cover DP case Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9497eb6..abf8c7d 100644 --- a/drivers

[Intel-gfx] [PATCH 1/3] drm/i915: DP link training optimization

training parameters are set to zero and training is restarted. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 75 +++- drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 67 insertions(+), 9 deletions(-) diff --git

[Intel-gfx] [PATCH] drm/i915: DP link training optimization

VBT. The fallback on both cases is to reset the link training parameters and restart. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 93 +++- drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 84 insertions(+), 10

[Intel-gfx] [PATCH] drm/i915: DP link training optimization

Reuse existing DP link training values i.e. voltage swing and pre-emphasis levels, if DP port that we are connected to hasn't changed. If we are unable to re-initialize DP link, the fallback is to reset the link training values, and restart. modified: intel_dp.c modified:

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