[Intel-gfx] [PATCH 0/3] TV Out patches to make our mode list be according to TV timing standards
Hi all, The following patches makes the TV Out mode list be according to timing table specification from TV standards. The first one of the list fixes the https://bugs.freedesktop.org/show_bug.cgi?id=23899 When I start looking at this bug I was so focused on the pixel clock that I didn't noticed refresh rates were half of the specification for most of the modes. After the fix some modes got obsoletes and others were removed simply because they weren't on the TV Out standard timing table. From this same table I got the 1080p specification and added to our list there. Cheers, Rodrigo. Rodrigo Vivi (3): drm/i915: Fix TV Out refresh rate. drm/i915: Removing TV Out modes. drm/i915: Adding 1080p modes to our TV Out mode list. drivers/gpu/drm/i915/intel_tv.c | 176 ++- 1 files changed, 63 insertions(+), 113 deletions(-) -- 1.7.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Fix TV Out refresh rate.
TV Out refresh rate was half of the specification for almost all modes.
Due to this reason pixel clock was so low for some modes causing flickering
screen.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index f3c6a9a..2b1fcad 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -417,7 +417,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = NTSC-M,
.clock = 108000,
- .refresh= 29970,
+ .refresh= 59940,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
@@ -460,7 +460,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = NTSC-443,
.clock = 108000,
- .refresh= 29970,
+ .refresh= 59940,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
@@ -502,7 +502,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = NTSC-J,
.clock = 108000,
- .refresh= 29970,
+ .refresh= 59940,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -545,7 +545,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = PAL-M,
.clock = 108000,
- .refresh= 29970,
+ .refresh= 59940,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -589,7 +589,7 @@ static const struct tv_mode tv_modes[] = {
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = PAL-N,
.clock = 108000,
- .refresh= 25000,
+ .refresh= 5,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -634,7 +634,7 @@ static const struct tv_mode tv_modes[] = {
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = PAL,
.clock = 108000,
- .refresh= 25000,
+ .refresh= 5,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -821,7 +821,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = 1080i@50Hz,
.clock = 148800,
- .refresh= 25000,
+ .refresh= 5,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -847,7 +847,7 @@ static const struct tv_mode tv_modes[] = {
{
.name = 1080i@60Hz,
.clock = 148800,
- .refresh= 3,
+ .refresh= 6,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
--
1.7.7.4
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[Intel-gfx] [PATCH 2/3] drm/i915: Removing TV Out modes.
These modes are no longer needed or are not according to TV timing standards.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 122 ---
1 files changed, 0 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 2b1fcad..1571be3 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -674,78 +674,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 480p@59.94Hz,
- .clock = 107520,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 857,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 480p@60Hz,
- .clock = 107520,
- .refresh= 6,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 856,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 576p,
- .clock = 107520,
- .refresh= 5,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 139,
- .hblank_start = 859, .htotal = 863,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 48, .vi_end_f2 = 48,
- .nbr_end= 575,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@60Hz,
.clock = 148800,
.refresh= 6,
@@ -770,30 +698,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 720p@59.94Hz,
- .clock = 148800,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 80, .hblank_end = 300,
- .hblank_start = 1580, .htotal = 1651,
-
- .progressive= true, .trilevel_sync = true,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 29, .vi_end_f2 = 29,
- .nbr_end= 719,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@50Hz,
.clock = 148800,
.refresh= 5,
@@ -870,32 +774,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
- {
- .name = 1080i@59.94Hz,
- .clock = 148800,
- .refresh= 29970,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 88, .hblank_end = 235,
- .hblank_start = 2155, .htotal = 2201,
-
- .progressive= false,.trilevel_sync = true,
-
- .vsync_start_f1 = 4,.vsync_start_f2= 5
[Intel-gfx] [PATCH 3/3] drm/i915: Adding 1080p modes to our TV Out mode list.
According to TV Out timing standards, supported 1080p modes were missing.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 72 +++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1571be3..cfb44f4 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -774,6 +774,78 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
+ {
+ .name = 1080p@30Hz,
+ .clock = 148800,
+ .refresh= 3,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@50Hz,
+ .clock = 148800,
+ .refresh= 5,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2639,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@60Hz,
+ .clock = 148800,
+ .refresh= 6,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
};
static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
--
1.7.7.4
___
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[Intel-gfx] [PATCH 1/2] drm/i915: Removing TV Out modes.
These modes are no longer needed or are not according to TV timing standards.
Intel PRM Vol 3 - Display Registers Updated - Section 5 TV-Out Programming /
5.2.1 Television Standards / 5.2.1.1 Timing tables
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 122 ---
1 files changed, 0 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 2b1fcad..1571be3 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -674,78 +674,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 480p@59.94Hz,
- .clock = 107520,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 857,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 480p@60Hz,
- .clock = 107520,
- .refresh= 6,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 856,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 576p,
- .clock = 107520,
- .refresh= 5,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 139,
- .hblank_start = 859, .htotal = 863,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 48, .vi_end_f2 = 48,
- .nbr_end= 575,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@60Hz,
.clock = 148800,
.refresh= 6,
@@ -770,30 +698,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 720p@59.94Hz,
- .clock = 148800,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 80, .hblank_end = 300,
- .hblank_start = 1580, .htotal = 1651,
-
- .progressive= true, .trilevel_sync = true,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 29, .vi_end_f2 = 29,
- .nbr_end= 719,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@50Hz,
.clock = 148800,
.refresh= 5,
@@ -870,32 +774,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
- {
- .name = 1080i@59.94Hz,
- .clock = 148800,
- .refresh= 29970,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 88, .hblank_end = 235,
- .hblank_start = 2155, .htotal = 2201
[Intel-gfx] [PATCH 2/2] drm/i915: Adding 1080p modes to our TV Out mode list.
Adding 1080p supported modes according to new PRM version which is
internal for now.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 72 +++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1571be3..cfb44f4 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -774,6 +774,78 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
+ {
+ .name = 1080p@30Hz,
+ .clock = 148800,
+ .refresh= 3,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@50Hz,
+ .clock = 148800,
+ .refresh= 5,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2639,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@60Hz,
+ .clock = 148800,
+ .refresh= 6,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
};
static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
--
1.7.7.4
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix TV Out refresh rate.
I think we should go ahead and integrate the first and second patches and skip the 1080 (third) for now. We are internally discussing when and if that document will be released. On Fri, Jan 6, 2012 at 8:02 PM, Keith Packard kei...@keithp.com wrote: On Wed, 14 Dec 2011 21:10:06 -0200, Rodrigo Vivi rodrigo.v...@gmail.com wrote: TV Out refresh rate was half of the specification for almost all modes. Due to this reason pixel clock was so low for some modes causing flickering screen. Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com And These modes are no longer needed or are not according to TV timing standards. Intel PRM Vol 3 - Display Registers Updated - Section 5 TV-Out Programming / 5.2.1 Television Standards / 5.2.1.1 Timing tables Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com I've got these two queued on my machine. Once drm-next is merged to master, drm-intel-fixes will be fast-forwarded to that point and these fixes rebased on top of that. There's still the 1080p modes which Chris has asked for an updated changelog and a comment in the source for. -- keith.pack...@intel.com -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Problem Intel i915 driver, i3 2010T, HDMI output modes problems
Hi Paulo, sorry for not getting back you sooner... your email was here on my to do list Could you please report this issue on bugs.freedesktop.org attaching this xrandr verbose info and also dmesg xorg log and confs? Also, Is it possible to test it without the AV receiver? I think you wont see a similar behaviour? Maybe AV receiver is meessing up EDID info when booting, but it would be strange to see x reporting a freq and receiver another one anyway. The interlacing issue is also possible, so as much info you can provide us the best! I also think that the workaround Andy suggested will work in your case, but I would like to get it really fixed. Rodrigo. On Mon, Jan 16, 2012 at 8:09 PM, Andy Burns xorg.li...@burns.me.uk wrote: [apologies for munged threading, I subscribed after the original message was sent] paulo louro wrote: When starting ubuntu without the AV receiver or the TV being on, the xorg start with a resolution of 720x576. Have you tried forcing an initial mode in the Monitor section of your xorg.conf? Option PreferredMode whatever presumably whatever is something like 1920x1080x60.0 in your case ... ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes
The git repo is right, but are you sure you are using the remotes/origin/interlaced branch? It is strange that you couldn't see any interlace mode without using the handmade modeline. On Mon, Feb 13, 2012 at 4:44 PM, Atechsystem atechsys...@freenet.de wrote: -Ursprüngliche Nachricht- Von: Atechsystem [mailto:atechsys...@freenet.de] Gesendet: Montag, 13. Februar 2012 19:44 An: 'Paulo Zanoni' Betreff: AW: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes Hi, thanks for your quick reply. Paulo Zanoni [mailto:przan...@gmail.com] Which git repo and which branch exactly? You may have a repo without the patches that fix interlaced modes. I compiled it from here: git://people.freedesktop.org/~danvet/drm Which line did you add to xorg.conf? What exactly did you do in this step? Please try to remove every xorg configuration file and test again with the default configuration I added for example: Modeline 1920x1080@50i 74.25 1920 2448 2492 2640 1080 1084 1094 1124 interlace +hsync +vsync Without a modeline I can't select interlace modes. Only 60Hz, 50Hz, 30Hz, 25Hz and 24Hz. Please attach the TV, then run xrandr --verbose and send us the output. Please also send the output of intel_reg_dumper: http://intellinuxgraphics.org/intel_reg_dumper.html Please find files attached. -Ursprüngliche Nachricht- Von: Paulo Zanoni [mailto:przan...@gmail.com] Gesendet: Montag, 13. Februar 2012 18:58 An: Atechsystem Cc: dan...@ffwll.ch; intel-gfx@lists.freedesktop.org Betreff: Re: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes Hi 2012/2/13 Atechsystem atechsys...@freenet.de: I compiled the kernel from your git repro to test interlaced output with my Clarkdale (H55) Chipset. Which git repo and which branch exactly? You may have a repo without the patches that fix interlaced modes. After installing and reboot I put the interlaced line to my xorg.conf and activate them (first by xorg.conf and after that by lxdm resolution set tool). Which line did you add to xorg.conf? What exactly did you do in this step? Please try to remove every xorg configuration file and test again with the default configuration I only get a screen full of colored stripes after switching from progressive to interlaced mode. My TV shows 1080i as input mode. After that I read all mode lines from my TV by using the xorg server log and tried every interlaced modeline I found but always the same striped screen. To get sure that I use correct modelines I checked them with an plugged in card from another brand and it works immediately. Please attach the TV, then run xrandr --verbose and send us the output. Please also send the output of intel_reg_dumper: http://intellinuxgraphics.org/intel_reg_dumper.html -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] WG: Interlaced mode on intel Clarkdale only colored stripes
I'm glad that it is working for you now! Yes, the drm-intel-next-queued has all the interlaced patches that were in remotes/origin/interlaced. I don't think your tv doesn't report the interlaced modes, but the modes it reports are the CEA modes we aren't supporting yet. It is on my todo list take a carefully look at this modes. Cheers, Rodrigo. On Mon, Feb 13, 2012 at 6:44 PM, Atechsystem atechsys...@freenet.de wrote: Hello, Von: Paulo Zanoni [mailto:przan...@gmail.com] Maybe the best tree to test is this: http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next-queued Thanks, compiling from this repro solved my problem. With my TV I have to use the xorg modeline, without it I can't select the interlaced modes. If I use my NEC monitor I can select the I modeline by using the lxde monitor setting tool. I think my TV don't report the I modelines. Thanks for this patch Regards Atech -Ursprüngliche Nachricht- Von: intel-gfx-bounces+atechsystem=freenet...@lists.freedesktop.org [mailto:intel-gfx-bounces+atechsystem=freenet...@lists.freedesktop.org] Im Auftrag von Atechsystem Gesendet: Montag, 13. Februar 2012 20:05 An: 'Paulo Zanoni' Cc: intel-gfx@lists.freedesktop.org Betreff: Re: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes Von: Paulo Zanoni [mailto:przan...@gmail.com] Maybe the best tree to test is this: http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next-que ued I will compile it now. Before I used the drm-intel-next branch. I downloaded the latest tar.gz file and didn't use git to checkout the branch. Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] The git repo is right, but are you sure you are using the remotes/origin/interlaced branch? It is strange that you couldn't see any interlace mode without using the handmade modeline. No chance to select it directly. I 've no clue to select it by standard lxde dialog. -Ursprüngliche Nachricht- Von: Paulo Zanoni [mailto:przan...@gmail.com] Gesendet: Montag, 13. Februar 2012 19:56 An: Atechsystem Cc: Intel Graphics Development Betreff: Re: [Intel-gfx] Interlaced mode on intel Clarkdale only colored stripes 2012/2/13 Atechsystem atechsys...@freenet.de: I compiled it from here: git://people.freedesktop.org/~danvet/drm Did you change to the interlaced branch? Maybe the best tree to test is this: http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next-queued (repository is drm-intel and branch is drm-intel-next-queued). I added for example: Modeline 1920x1080@50i 74.25 1920 2448 2492 2640 1080 1084 1094 1124 interlace +hsync +vsync Without a modeline I can't select interlace modes. Only 60Hz, 50Hz, 30Hz, 25Hz and 24Hz. This should not be needed. If you have the correct branch, you don't need any configuration tweak: just boot the machine, plug a monitor that supports interlaced modes, and xrandr --verbose will show you some interlaced modes. Please confirm that you are using the correct branch first. Use git log or git branch commands to check. -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't pretend ips is always enabled on BDW.
As pointed out before we don't have a reliable way to read back ips
status on BDW without the risk to disable it when reading.
However now we are pretending that IPS on BDW is always on and getting
people confused about it.
So this patch allows people to know if ips was ever attempted to be enabled.
Even if the current status is impossible to be ascertain.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a93b3bf..5e36b3c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1523,10 +1523,16 @@ static int i915_ips_status(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
- if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) IPS_ENABLE)
- seq_puts(m, enabled\n);
- else
- seq_puts(m, disabled\n);
+ seq_puts(m, Enabled on boot: %s\n, yesno(i915.ips_enabled));
+
+ if (IS_BROADWELL(dev)) {
+ seq_puts(m, Currently: impossible to ascertain\n);
+ } else {
+ if (I915_READ(IPS_CTL) IPS_ENABLE)
+ seq_puts(m, Currently: enabled\n);
+ else
+ seq_puts(m, Currently: disabled\n);
+ }
intel_runtime_pm_put(dev_priv);
--
1.9.3
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Re: [Intel-gfx] [PATCH] drm/i915: Fix some NUM_RING iterators
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
On Fri, Jun 27, 2014 at 3:09 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
There are some cases in the code where we need to know how many rings to
iterate over, but cannot use for_each_ring(). These are always error cases
which happen either before ring setup, or after ring teardown (or
reset).
Note, a NUM_RINGS issue exists in semaphores, but this is fixed by the
remaining semaphore patches which Rodrigo will resubmit shortly. I'd
rather see those patches for fixing the problem than fix it here.
I found this initially for the BSD2 case where on the same platform we
can have differing rings. AFAICT however this effects many platforms.
I'd CC stable on this, except I think all the issues have been around
for multiple releases without bug reports.
Compile tested only for now.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b9bac25..0c044a9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -403,7 +403,7 @@ void i915_gem_context_reset(struct drm_device *dev)
/* Prevent the hardware from restoring the last context (which
hung) on
* the next switch */
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
struct intel_context *dctx = ring-default_context;
@@ -456,7 +456,7 @@ int i915_gem_context_init(struct drm_device *dev)
}
/* NB: RCS will hold a ref for all rings */
- for (i = 0; i I915_NUM_RINGS; i++)
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++)
dev_priv-ring[i].default_context = ctx;
DRM_DEBUG_DRIVER(%s context support initialized\n,
dev_priv-hw_context_size ? HW : fake);
@@ -493,7 +493,7 @@ void i915_gem_context_fini(struct drm_device *dev)
i915_gem_object_ggtt_unpin(dctx-obj);
}
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev); i++) {
struct intel_engine_cs *ring = dev_priv-ring[i];
if (ring-last_context)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 86362de..6e5250d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -848,7 +848,7 @@ static uint32_t i915_error_generate_code(struct
drm_i915_private *dev_priv,
* synchronization commands which almost always appear in the case
* strictly a client bug. Use instdone to differentiate those some.
*/
- for (i = 0; i I915_NUM_RINGS; i++) {
+ for (i = 0; i I915_ACTIVE_RINGS(dev_priv-dev); i++) {
if (error-ring[i].hangcheck_action == HANGCHECK_HUNG) {
if (ring_id)
*ring_id = i;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e72017b..67e2919 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,6 +90,8 @@ struct intel_engine_cs {
} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
+#define I915_ACTIVE_RINGS(dev) hweight8(INTEL_INFO(dev)-ring_mask)
+
u32 mmio_base;
struct drm_device *dev;
struct intel_ringbuffer *buffer;
--
2.0.0
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH] drm/i915: flush delayed_resume_work when suspending
I have the feeling the safest side would be disable rc6 on resume instead of force its enabling... or am I missing something? why don't you just cancel the work? and put another after resume? but if the patch really solves the problem and this is what you meant feel free to use: Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jun 27, 2014 at 2:51 PM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com It is possible that, by the time we run i915_drm_freeze(), delayed_resume_work was already queued but did not run yet. If it still didn't run after intel_runtime_pm_disable_interrupts(), by the time it runs it will try to change the interrupt registers with the interrupts already disabled, which will trigger a WARN. We can reliably reproduce this with the pm_rpm system-suspend test case. In order to avoid the problem, we have to flush the work before disabling the interrupts. We could also cancel the work instead of flushing it, but that would require us to put a runtime PM reference - and any other resource we may need in the future - in case the work was already queued, so I believe flushing the work is more future-proof, although less efficient. But I can also change this part if someone requests. Another thing I tried was to move the intel_suspend_gt_powersave() call to before intel_runtime_pm_disable_interrupts(), but since that function needs to be called after the interrupts are already disabled, due to dev_priv-rps.work, this strategy didn't work. Testcase: igt/pm_rpm/system-suspend Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80517 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e64547e..672694b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -524,6 +524,8 @@ static int i915_drm_freeze(struct drm_device *dev) return error; } + flush_delayed_work(dev_priv-rps.delayed_resume_work); + intel_runtime_pm_disable_interrupts(dev); dev_priv-enable_hotplug_processing = false; -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't pretend ips is always enabled on BDW.
As pointed out before we don't have a reliable way to read back ips
status on BDW without the risk to disable it when reading.
However now we are pretending that IPS on BDW is always on and getting
people confused about it.
So this patch allows people to know if ips was ever attempted to be enabled.
Even if the current status is impossible to be ascertain.
v2: (spotted by Paulo):
* A version that at least compiles
* with more clear messages
* let Cheryview on the safe side until we aren't sure that checking ips
state on ips won't disable it.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a93b3bf..380be89 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1523,10 +1523,17 @@ static int i915_ips_status(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
- if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) IPS_ENABLE)
- seq_puts(m, enabled\n);
- else
- seq_puts(m, disabled\n);
+ seq_printf(m, Enabled by kernel parameter: %s\n,
+ yesno(i915.enable_ips));
+
+ if (INTEL_INFO(dev)-gen = 8) {
+ seq_puts(m, Currently: unknown\n);
+ } else {
+ if (I915_READ(IPS_CTL) IPS_ENABLE)
+ seq_puts(m, Currently: enabled\n);
+ else
+ seq_puts(m, Currently: disabled\n);
+ }
intel_runtime_pm_put(dev_priv);
--
1.9.3
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Re: [Intel-gfx] [PATCH] drm/i915: flush delayed_resume_work when suspending
On Mon, Jun 30, 2014 at 12:22 PM, Paulo Zanoni przan...@gmail.com wrote: 2014-06-27 19:30 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com: I have the feeling the safest side would be disable rc6 on resume instead of force its enabling... or am I missing something? It will be enabled, then disabled. oh that's true! why don't you just cancel the work? and put another after resume? but if the patch really solves the problem and this is what you meant feel free to use: What you're suggesting is the We could also case mentioned in the second paragraph of the commit message. I even wrote and tested that patch, Yeah, reading again this is exactly what I had in mind. but Jesse seemed to prefer the flush version instead of the cancel one. I'll send the other version to the list, then reviewers and maintainers can decide which one they prefer :) I don't have stronger preferences. So, feel free to use: Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Thanks for the explanations, Rodrigo. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jun 27, 2014 at 2:51 PM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com It is possible that, by the time we run i915_drm_freeze(), delayed_resume_work was already queued but did not run yet. If it still didn't run after intel_runtime_pm_disable_interrupts(), by the time it runs it will try to change the interrupt registers with the interrupts already disabled, which will trigger a WARN. We can reliably reproduce this with the pm_rpm system-suspend test case. In order to avoid the problem, we have to flush the work before disabling the interrupts. We could also cancel the work instead of flushing it, but that would require us to put a runtime PM reference - and any other resource we may need in the future - in case the work was already queued, so I believe flushing the work is more future-proof, although less efficient. But I can also change this part if someone requests. Another thing I tried was to move the intel_suspend_gt_powersave() call to before intel_runtime_pm_disable_interrupts(), but since that function needs to be called after the interrupts are already disabled, due to dev_priv-rps.work, this strategy didn't work. Testcase: igt/pm_rpm/system-suspend Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80517 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e64547e..672694b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -524,6 +524,8 @@ static int i915_drm_freeze(struct drm_device *dev) return error; } + flush_delayed_work(dev_priv-rps.delayed_resume_work); + intel_runtime_pm_disable_interrupts(dev); dev_priv-enable_hotplug_processing = false; -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br -- Paulo Zanoni -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Fix VCS2's ring name.
It just fix a typo. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2faef26..c3f96a1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2224,7 +2224,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) return -EINVAL; } - ring-name = bds2_ring; + ring-name = bsd2_ring; ring-id = VCS2; ring-write_tail = ring_write_tail; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Introduce dual_bsd_ring parameter.
On Broadwell GT3 we have 2 Video Command Streamers (VCS),
but userspace has no control when using VCS1 or VCS2. So we cannot test,
validate or debug specific changes or workaround that might affect only
one or another ring. So this patch introduces a mechanism to avoid the
ping-pong selection and use one specific ring given at boot time.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 34 ++
drivers/gpu/drm/i915/i915_params.c | 6 ++
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..7b6614f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2069,6 +2069,7 @@ struct i915_params {
int panel_ignore_lid;
unsigned int powersave;
int semaphores;
+ int dual_bsd_ring;
unsigned int lvds_downclock;
int lvds_channel_mode;
int panel_use_ssc;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d815ef5..09f350e 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1035,26 +1035,32 @@ static int gen8_dispatch_bsd_ring(struct drm_device
*dev,
{
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_file_private *file_priv = file-driver_priv;
+ int ring_id;
+ int dual = i915.dual_bsd_ring;
/* Check whether the file_priv is using one ring */
if (file_priv-bsd_ring)
return file_priv-bsd_ring-id;
- else {
- /* If no, use the ping-pong mechanism to select one ring */
- int ring_id;
- mutex_lock(dev-struct_mutex);
- if (dev_priv-mm.bsd_ring_dispatch_index == 0) {
- ring_id = VCS;
- dev_priv-mm.bsd_ring_dispatch_index = 1;
- } else {
- ring_id = VCS2;
- dev_priv-mm.bsd_ring_dispatch_index = 0;
- }
- file_priv-bsd_ring = dev_priv-ring[ring_id];
- mutex_unlock(dev-struct_mutex);
- return ring_id;
+ /* If no, use the parameter defined or ping-pong mechanism
+* to select one ring */
+ mutex_lock(dev-struct_mutex);
+
+ if (dual == 1 || (dual != 2
+ dev_priv-mm.bsd_ring_dispatch_index == 0)) {
+ ring_id = VCS;
+ dev_priv-mm.bsd_ring_dispatch_index = 1;
+ } else {
+ ring_id = VCS2;
+ dev_priv-mm.bsd_ring_dispatch_index = 0;
}
+
+ file_priv-bsd_ring = dev_priv-ring[ring_id];
+ mutex_unlock(dev-struct_mutex);
+
+ WARN(dual, Forcibly trying to use only one bsd ring. Using: %s\n,
+file_priv-bsd_ring-name);
+ return ring_id;
}
static struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8145729..d4871c8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -29,6 +29,7 @@ struct i915_params i915 __read_mostly = {
.panel_ignore_lid = 1,
.powersave = 1,
.semaphores = -1,
+ .dual_bsd_ring = 0,
.lvds_downclock = 0,
.lvds_channel_mode = 0,
.panel_use_ssc = -1,
@@ -70,6 +71,11 @@ MODULE_PARM_DESC(semaphores,
Use semaphores for inter-ring sync
(default: -1 (use per-chip defaults)));
+module_param_named(dual_bsd_ring, i915.dual_bsd_ring, int, 0600);
+MODULE_PARM_DESC(dual_bsd_ring,
+Specify bds rings for VCS when there are multiple VCSs available.
+(0=All available bsd rings [default], 1=only VCS1, 2=only VCS2));
+
module_param_named(enable_rc6, i915.enable_rc6, int, 0400);
MODULE_PARM_DESC(enable_rc6,
Enable power-saving render C-state 6.
--
1.9.3
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[Intel-gfx] [PATCH 3/3] drm/i915: Updating comments.
ring index calculation table was out of date after other rings were added, although the formula is flexible and scale when adding new rings. So this patch just update the comments and add a brief explanation why to use sync_seqno[ring index]. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f6d1238..e85c85c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2842,6 +2842,8 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, idx = intel_ring_sync_index(from, to); seqno = obj-last_read_seqno; + /* Optimization: Avoid semaphore sync when we are sure we already +* waited for an object with higher seqno */ if (seqno = from-semaphore.sync_seqno[idx]) return 0; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index e72017b..2e8b516 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -238,9 +238,11 @@ intel_ring_sync_index(struct intel_engine_cs *ring, int idx; /* -* cs - 0 = vcs, 1 = bcs -* vcs - 0 = bcs, 1 = cs, -* bcs - 0 = cs, 1 = vcs. +* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; +* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; +* bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; +* vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; +* vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; */ idx = (other - ring) - 1; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/10] drm/i915: Make semaphore updates more precise
From: Ben Widawsky b...@bwidawsk.net
With the ring mask we now have an easy way to know the number of rings
in the system, and therefore can accurately predict the number of dwords
to emit for semaphore signalling. This was not possible (easily)
previously.
There should be no functional impact, simply fewer instructions emitted.
While we're here, simply do the round up to 2 instead of the fancier
rounding we did before, which rounding up per mbox, ie 4. This also
allows us to drop the unnecessary MI_NOOP, so not really 4, 3.
v2: Use 3 dwords instead of 4 (Ville)
Do the proper calculation to get the number of dwords to emit (Ville)
Conditionally set .sync_to when semaphores are enabled (Ville)
v3: Rebased on VCS2
Replace hweight_long with hweight32 (Ville)
v4: Pull out the accidentally squashed hunk from the next patch after
rebase (Daniel).
v5: Fix conflict after rebase (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com (v1)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2faef26..5c20536 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -679,23 +679,16 @@ static int gen6_signal(struct intel_engine_cs *signaller,
struct drm_device *dev = signaller-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *useless;
- int i, ret;
+ int i, ret, num_rings;
- /* NB: In order to be able to do semaphore MBOX updates for varying
-* number of rings, it's easiest if we round up each individual update
-* to a multiple of 2 (since ring updates must always be a multiple of
-* 2) even though the actual update only requires 3 dwords.
-*/
-#define MBOX_UPDATE_DWORDS 4
- if (i915_semaphore_is_enabled(dev))
- num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
- else
- return intel_ring_begin(signaller, num_dwords);
+#define MBOX_UPDATE_DWORDS 3
+ num_rings = hweight32(INTEL_INFO(dev)-ring_mask);
+ num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
+#undef MBOX_UPDATE_DWORDS
ret = intel_ring_begin(signaller, num_dwords);
if (ret)
return ret;
-#undef MBOX_UPDATE_DWORDS
for_each_ring(useless, dev_priv, i) {
u32 mbox_reg = signaller-semaphore.mbox.signal[i];
@@ -703,15 +696,13 @@ static int gen6_signal(struct intel_engine_cs *signaller,
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(signaller, mbox_reg);
intel_ring_emit(signaller,
signaller-outstanding_lazy_seqno);
- intel_ring_emit(signaller, MI_NOOP);
- } else {
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
}
}
+ /* If num_dwords was rounded, make sure the tail pointer is correct */
+ if (num_rings % 2 == 0)
+ intel_ring_emit(signaller, MI_NOOP);
+
return 0;
}
--
1.9.3
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[Intel-gfx] [PATCH 02/10] drm/i915: gen specific ring init
From: Ben Widawsky benjamin.widaw...@intel.com
Gen8 has already had some differentiation with how it handles rings.
Semaphores bring yet more differences, and now is as good a time as any
to do the split.
Also, since gen8 doesn't actually use semaphores up until this point,
put the proper NULL values in for the mbox info.
v2: v1 had a stale commit message
v3: Move everything in the is_semaphore_enabled() check
v4: VCS2 rebase
Remove double assignment of signal in render ring (Ville)
v5: Adding missed VCS2 signal init on gen8+ (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 227 +---
1 file changed, 151 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5c20536..e8be49b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -720,7 +720,11 @@ gen6_add_request(struct intel_engine_cs *ring)
{
int ret;
- ret = ring-semaphore.signal(ring, 4);
+ if (ring-semaphore.signal)
+ ret = ring-semaphore.signal(ring, 4);
+ else
+ ret = intel_ring_begin(ring, 4);
+
if (ret)
return ret;
@@ -1943,40 +1947,59 @@ int intel_init_render_ring_buffer(struct drm_device
*dev)
ring-id = RCS;
ring-mmio_base = RENDER_RING_BASE;
- if (INTEL_INFO(dev)-gen = 6) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ ring-add_request = gen6_add_request;
+ ring-flush = gen8_render_ring_flush;
+ ring-irq_get = gen8_ring_get_irq;
+ ring-irq_put = gen8_ring_put_irq;
+ ring-irq_enable_mask = GT_RENDER_USER_INTERRUPT;
+ ring-get_seqno = gen6_ring_get_seqno;
+ ring-set_seqno = ring_set_seqno;
+ if (i915_semaphore_is_enabled(dev)) {
+ ring-semaphore.sync_to = gen6_ring_sync;
+ ring-semaphore.signal = gen6_signal;
+ ring-semaphore.mbox.wait[RCS] =
MI_SEMAPHORE_SYNC_INVALID;
+ ring-semaphore.mbox.wait[VCS] =
MI_SEMAPHORE_SYNC_INVALID;
+ ring-semaphore.mbox.wait[BCS] =
MI_SEMAPHORE_SYNC_INVALID;
+ ring-semaphore.mbox.wait[VECS] =
MI_SEMAPHORE_SYNC_INVALID;
+ ring-semaphore.mbox.wait[VCS2] =
MI_SEMAPHORE_SYNC_INVALID;
+ ring-semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
+ ring-semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
+ ring-semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
+ ring-semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
+ ring-semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
+ }
+ } else if (INTEL_INFO(dev)-gen = 6) {
ring-add_request = gen6_add_request;
ring-flush = gen7_render_ring_flush;
if (INTEL_INFO(dev)-gen == 6)
ring-flush = gen6_render_ring_flush;
- if (INTEL_INFO(dev)-gen = 8) {
- ring-flush = gen8_render_ring_flush;
- ring-irq_get = gen8_ring_get_irq;
- ring-irq_put = gen8_ring_put_irq;
- } else {
- ring-irq_get = gen6_ring_get_irq;
- ring-irq_put = gen6_ring_put_irq;
- }
+ ring-irq_get = gen6_ring_get_irq;
+ ring-irq_put = gen6_ring_put_irq;
ring-irq_enable_mask = GT_RENDER_USER_INTERRUPT;
ring-get_seqno = gen6_ring_get_seqno;
ring-set_seqno = ring_set_seqno;
- ring-semaphore.sync_to = gen6_ring_sync;
- ring-semaphore.signal = gen6_signal;
- /*
-* The current semaphore is only applied on pre-gen8 platform.
-* And there is no VCS2 ring on the pre-gen8 platform. So the
-* semaphore between RCS and VCS2 is initialized as INVALID.
-* Gen8 will initialize the sema between VCS2 and RCS later.
-*/
- ring-semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
- ring-semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
- ring-semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
- ring-semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
- ring-semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
- ring-semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
- ring-semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
- ring-semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
- ring-semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
- ring-semaphore.mbox.signal
[Intel-gfx] [PATCH 04/10] drm/i915/bdw: implement semaphore wait
From: Ben Widawsky b...@bwidawsk.net
Semaphore waits use a new instruction, MI_SEMAPHORE_WAIT. The seqno to
wait on is all well defined by the table in the previous patch. There is
nothing else different from previous GEN's semaphore synchronization
code.
v2: Update macros to not require the other ring's ring-id (Chris)
v3: Add missing VCS2 gen8_ring_wait init besides
s/ring_buffer/engine_cs (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 -
2 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2130d07..9de11de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -268,6 +268,9 @@
#define MI_RESTORE_INHIBIT (10)
#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
#define MI_SEMAPHORE_TARGET(engine) ((engine)15)
+#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
+#define MI_SEMAPHORE_POLL(115)
+#define MI_SEMAPHORE_SAD_GTE_SDD (112)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_MEM_VIRTUAL (1 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a215ab4..2e0413c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -832,6 +832,31 @@ static inline bool i915_gem_has_seqno_wrapped(struct
drm_device *dev,
* @signaller - ring which has, or will signal
* @seqno - seqno which the waiter will block on
*/
+
+static int
+gen8_ring_sync(struct intel_engine_cs *waiter,
+ struct intel_engine_cs *signaller,
+ u32 seqno)
+{
+ struct drm_i915_private *dev_priv = waiter-dev-dev_private;
+ int ret;
+
+ ret = intel_ring_begin(waiter, 4);
+ if (ret)
+ return ret;
+
+ intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_SAD_GTE_SDD);
+ intel_ring_emit(waiter, seqno);
+ intel_ring_emit(waiter,
+ lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller-id)));
+ intel_ring_emit(waiter,
+ upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller-id)));
+ intel_ring_advance(waiter);
+ return 0;
+}
+
static int
gen6_ring_sync(struct intel_engine_cs *waiter,
struct intel_engine_cs *signaller,
@@ -2056,7 +2081,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring-set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev)) {
BUG_ON(!dev_priv-semaphore_obj);
- ring-semaphore.sync_to = gen6_ring_sync;
+ ring-semaphore.sync_to = gen8_ring_sync;
ring-semaphore.signal = gen8_rcs_signal;
GEN8_RING_SEMAPHORE_INIT;
}
@@ -2267,7 +2292,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring-dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev)) {
- ring-semaphore.sync_to = gen6_ring_sync;
+ ring-semaphore.sync_to = gen8_ring_sync;
ring-semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
}
@@ -2343,8 +2368,8 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
ring-irq_put = gen8_ring_put_irq;
ring-dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- ring-semaphore.sync_to = gen6_ring_sync;
if (i915_semaphore_is_enabled(dev)) {
+ ring-semaphore.sync_to = gen8_ring_sync;
ring-semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
}
@@ -2374,7 +2399,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring-irq_put = gen8_ring_put_irq;
ring-dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev)) {
- ring-semaphore.sync_to = gen6_ring_sync;
+ ring-semaphore.sync_to = gen8_ring_sync;
ring-semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
}
@@ -2432,7 +2457,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring-irq_put = gen8_ring_put_irq;
ring-dispatch_execbuffer
[Intel-gfx] [PATCH 10/10] drm/i915: Enable semaphores on BDW
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6eb45ac..1f84f88 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -477,10 +477,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) if (i915.semaphores = 0) return i915.semaphores; - /* Until we get further testing... */ - if (IS_GEN8(dev)) - return false; - #ifdef CONFIG_INTEL_IOMMU /* Enable semaphores on SNB when IO remapping is off */ if (INTEL_INFO(dev)-gen == 6 intel_iommu_gfx_mapped) -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm/i915/bdw: collect semaphore error state
From: Ben Widawsky b...@bwidawsk.net
Since the semaphore information is in an object, just dump it, and let
the user parse it later.
NOTE: The page being used for the semaphores are incoherent with the
CPU. No matter what I do, I cannot figure out a way to read anything but
0s. Note that the semaphore waits are indeed working.
v2: Don't print signal, and wait (they should be the same). Instead,
print sync_seqno (Chris)
v3: Free the semaphore error object (Chris)
v4: Fix semaphore offset calculation during error state collection
(Ville)
v5: VCS2 rebase
Make semaphore object error capture coding style consistent (Ville)
Do the proper math for the signal offset (Ville)
v6: Fix small conflicts on rebase and s/ring_buffer/engine_cs (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 51 ---
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61e43fc..f50ae5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -324,6 +324,7 @@ struct drm_i915_error_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
+ struct drm_i915_error_object *semaphore_obj;
struct drm_i915_error_ring {
bool valid;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9d42b6a..45b6191 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -327,6 +327,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
struct drm_device *dev = error_priv-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_error_state *error = error_priv-error;
+ struct drm_i915_error_object *obj;
int i, j, offset, elt;
int max_hangcheck_score;
@@ -395,8 +396,6 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
error-pinned_bo_count[0]);
for (i = 0; i ARRAY_SIZE(error-ring); i++) {
- struct drm_i915_error_object *obj;
-
obj = error-ring[i].batchbuffer;
if (obj) {
err_puts(m, dev_priv-ring[i].name);
@@ -459,6 +458,18 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
}
}
+ if ((obj = error-semaphore_obj)) {
+ err_printf(m, Semaphore page = 0x%08x\n, obj-gtt_offset);
+ for (elt = 0; elt PAGE_SIZE/16; elt += 4) {
+ err_printf(m, [%04x] %08x %08x %08x %08x\n,
+ elt * 4,
+ obj-pages[0][elt],
+ obj-pages[0][elt+1],
+ obj-pages[0][elt+2],
+ obj-pages[0][elt+3]);
+ }
+ }
+
if (error-overlay)
intel_overlay_print_error_state(m, error-overlay);
@@ -529,6 +540,7 @@ static void i915_error_state_free(struct kref *error_ref)
kfree(error-ring[i].requests);
}
+ i915_error_object_free(error-semaphore_obj);
kfree(error-active_bo);
kfree(error-overlay);
kfree(error-display);
@@ -747,6 +759,33 @@ static void i915_gem_record_fences(struct drm_device *dev,
}
+static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
+ struct drm_i915_error_state *error,
+ struct intel_engine_cs *ring,
+ struct drm_i915_error_ring *ering)
+{
+ struct intel_engine_cs *useless;
+ int i;
+
+ if (!i915_semaphore_is_enabled(dev_priv-dev))
+ return;
+
+ if (!error-semaphore_obj)
+ error-semaphore_obj =
+ i915_error_object_create(dev_priv,
+dev_priv-semaphore_obj,
+dev_priv-gtt.base);
+
+ for_each_ring(useless, dev_priv, i) {
+ u16 signal_offset =
+ (GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
+ u32 *tmp = error-semaphore_obj-pages[0];
+
+ ering-semaphore_mboxes[i] = tmp[signal_offset];
+ ering-semaphore_seqno[i] = ring-semaphore.sync_seqno[i];
+ }
+}
+
static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
@@ -764,6 +803,7 @@ static
[Intel-gfx] [PATCH 03/10] drm/i915/bdw: implement semaphore signal
From: Ben Widawsky b...@bwidawsk.net
Semaphore signalling works similarly to previous GENs with the exception
that the per ring mailboxes no longer exist. Instead you must define
your own space, somewhere in the GTT.
The comments in the code define the layout I've opted for, which should
be fairly future proof. Ie. I tried to define offsets in abstract terms
(NUM_RINGS, seqno size, etc).
NOTE: If one wanted to move this to the HWSP they could. I've decided
one 4k object would be easier to deal with, and provide potential wins
with cache locality, but that's all speculative.
v2: Update the macro to not need the other ring's ring-id (Chris)
Update the comment to use the correct formula (Chris)
v3: Move the macros the ringbuffer.h to prevent churn in next patch
(Ville)
v4: Fixed compilation rebase conflict
commit 1ec9e26ddab06459e89a890431b2de064c5d1056
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Feb 14 14:01:11 2014 +0100
drm/i915: Consolidate binding parameters into flags
v5: VCS2 rebase
Replace hweight_long with hweight32
v6 (Rodrigo): * Add missed VC2 gen8 ring signal init
* fixing conflicst on rebase
* minor fixes on address table
* remove WARN_ON
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 78 --
4 files changed, 189 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..61e43fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1374,6 +1374,7 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct intel_engine_cs ring[I915_NUM_RINGS];
+ struct drm_i915_gem_object *semaphore_obj;
uint32_t last_seqno, next_seqno;
drm_dma_handle_t *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3488567..2130d07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -240,7 +240,7 @@
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 19)
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 19)
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 19)
-#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
+#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
#define MI_SEMAPHORE_GLOBAL_GTT(122)
#define MI_SEMAPHORE_UPDATE (121)
#define MI_SEMAPHORE_COMPARE (120)
@@ -266,6 +266,8 @@
#define MI_RESTORE_EXT_STATE_EN (12)
#define MI_FORCE_RESTORE (11)
#define MI_RESTORE_INHIBIT (10)
+#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
+#define MI_SEMAPHORE_TARGET(engine) ((engine)15)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_MEM_VIRTUAL (1 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
@@ -360,6 +362,7 @@
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(110) /*
GM45+ only */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (19)
#define PIPE_CONTROL_NOTIFY (18)
+#define PIPE_CONTROL_FLUSH_ENABLE(17) /* gen7+ */
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (14)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (13)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (12)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e8be49b..a215ab4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -660,6 +660,13 @@ static int init_render_ring(struct intel_engine_cs *ring)
static void render_ring_cleanup(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-semaphore_obj) {
+ i915_gem_object_ggtt_unpin(dev_priv-semaphore_obj);
+ drm_gem_object_unreference(dev_priv-semaphore_obj-base);
+ dev_priv-semaphore_obj = NULL;
+ }
if (ring-scratch.obj == NULL)
return;
@@ -673,6 +680,80 @@ static void render_ring_cleanup(struct intel_engine_cs
*ring)
ring-scratch.obj = NULL;
}
+static int gen8_rcs_signal(struct intel_engine_cs *signaller,
+ unsigned int num_dwords)
+{
+#define MBOX_UPDATE_DWORDS 8
+ struct drm_device *dev = signaller-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *waiter;
+ int i, ret, num_rings;
+
+ num_rings = hweight32(INTEL_INFO(dev)-ring_mask);
+ num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS
[Intel-gfx] [PATCH 08/10] drm/i915: semaphore debugfs
From: Ben Widawsky b...@bwidawsk.net
Simple debugfs file to display the current state of semaphores. This is
useful if you want to see the state without hanging the GPU.
NOTE: This patch is optional to the series.
NOTE2: Like the GPU error state collection, the reads are currently
incoherent.
v2 (Rodrigo): * Iterate only on active rings.
* s/ring_buffer/engine_cs.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 71 +
1 file changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6b7b32b..ec24e14 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2386,6 +2386,76 @@ static int i915_display_info(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_semaphore_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m-private;
+ struct drm_device *dev = node-minor-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring;
+ int num_rings = hweight32(INTEL_INFO(dev)-ring_mask);
+ int i, j, ret;
+
+ if (!i915_semaphore_is_enabled(dev)) {
+ seq_puts(m, Semaphores are disabled\n);
+ return 0;
+ }
+
+ ret = mutex_lock_interruptible(dev-struct_mutex);
+ if (ret)
+ return ret;
+
+ if (IS_BROADWELL(dev)) {
+ struct page *page;
+ uint64_t *seqno;
+
+ page = i915_gem_object_get_page(dev_priv-semaphore_obj, 0);
+
+ seqno = (uint64_t *)kmap_atomic(page);
+ for_each_ring(ring, dev_priv, i) {
+ uint64_t offset;
+
+ seq_printf(m, %s\n, ring-name);
+
+ seq_puts(m, Last signal:);
+ for (j = 0; j num_rings; j++) {
+ offset = i * I915_NUM_RINGS + j;
+ seq_printf(m, 0x%08llx (0x%02llx) ,
+ seqno[offset], offset * 8);
+ }
+ seq_putc(m, '\n');
+
+ seq_puts(m, Last wait: );
+ for (j = 0; j num_rings; j++) {
+ offset = i + (j * I915_NUM_RINGS);
+ seq_printf(m, 0x%08llx (0x%02llx) ,
+ seqno[offset], offset * 8);
+ }
+ seq_putc(m, '\n');
+
+ }
+ kunmap_atomic(seqno);
+ } else {
+ seq_puts(m, Last signal:);
+ for_each_ring(ring, dev_priv, i)
+ for (j = 0; j num_rings; j++)
+ seq_printf(m, 0x%08x\n,
+
I915_READ(ring-semaphore.mbox.signal[j]));
+ seq_putc(m, '\n');
+ }
+
+ seq_puts(m, \nSync seqno:\n);
+ for_each_ring(ring, dev_priv, i) {
+ for (j = 0; j num_rings; j++) {
+ seq_printf(m, 0x%08x ,
ring-semaphore.sync_seqno[j]);
+ }
+ seq_putc(m, '\n');
+ }
+ seq_putc(m, '\n');
+
+ mutex_unlock(dev-struct_mutex);
+ return 0;
+}
+
struct pipe_crc_info {
const char *name;
struct drm_device *dev;
@@ -3837,6 +3907,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_pc8_status, i915_pc8_status, 0},
{i915_power_domain_info, i915_power_domain_info, 0},
{i915_display_info, i915_display_info, 0},
+ {i915_semaphore_status, i915_semaphore_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
1.9.3
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[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 42 ++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0217a41..66e2481 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2784,12 +2784,7 @@ static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
if (INTEL_INFO(dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return false;
+ return (ipehr 23) == 0x1c;
} else {
ipehr = ~MI_SEMAPHORE_SYNC_MASK;
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
@@ -2798,19 +2793,20 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32
ipehr)
}
static struct intel_engine_cs *
-semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
+semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64
offset)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct intel_engine_cs *signaller;
int i;
if (INTEL_INFO(dev_priv-dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return NULL;
+ for_each_ring(signaller, dev_priv, i) {
+ if (ring == signaller)
+ continue;
+
+ if (offset ==
signaller-semaphore.signal_ggtt[ring-id])
+ return signaller;
+ }
} else {
u32 sync_bits = ipehr MI_SEMAPHORE_SYNC_MASK;
@@ -2823,8 +2819,8 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring, u32 ipehr)
}
}
- DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x\n,
- ring-id, ipehr);
+ DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x, offset
0x%0%016llx\n,
+ ring-id, ipehr, offset);
return NULL;
}
@@ -2834,7 +2830,8 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
u32 cmd, ipehr, head;
- int i;
+ u64 offset = 0;
+ int i, backwards;
ipehr = I915_READ(RING_IPEHR(ring-mmio_base));
if (!ipehr_is_semaphore_wait(ring-dev, ipehr))
@@ -2843,13 +2840,15 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
/*
* HEAD is likely pointing to the dword after the actual command,
* so scan backwards until we find the MBOX. But limit it to just 3
-* dwords. Note that we don't care about ACTHD here since that might
+* or 4 dwords depending on the semaphore wait command size.
+* Note that we don't care about ACTHD here since that might
* point at at batch, and semaphores are always emitted into the
* ringbuffer itself.
*/
head = I915_READ_HEAD(ring) HEAD_ADDR;
+ backwards = (INTEL_INFO(ring-dev)-gen = 8) ? 5 : 4;
- for (i = 4; i; --i) {
+ for (i = backwards; i; --i) {
/*
* Be paranoid and presume the hw has gone off into the wild -
* our ring is smaller than what the hardware (and hence
@@ -2869,7 +2868,12 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
return NULL;
*seqno = ioread32(ring-buffer-virtual_start + head + 4) + 1;
- return semaphore_wait_to_signaller_ring(ring, ipehr);
+ if (INTEL_INFO(ring-dev)-gen = 8) {
+ offset = ioread32(ring-buffer-virtual_start + head + 12);
+ offset = 32;
+ offset = ioread32(ring-buffer-virtual_start + head + 8);
+ }
+ return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
}
static int semaphore_passed(struct intel_engine_cs *ring)
--
1.9.3
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[Intel-gfx] [PATCH 09/10] drm/i915/bdw: poll semaphores
From: Ben Widawsky benjamin.widaw...@intel.com As Ville points out, it's possible/probable we don't actually need this. Potentially, this validates the letter of the spec, and not the spirit. Ville: I discussed this on irc w/ Ben, and I was suggesting we don't need to poll. Polling apparently can be used as a workaround for certain hardware issues, but it looks like those issues shouldn't affect us, for the momemnt at least. So my suggestion was to try w/o polling first (since there could be some power cost to polling) and add the poll bit if problems arise. Rodrigo: Spec suggests this as an W/A for GT3. However semaphores didn't worked in my BDW GT2 on Signal Mode. So pool mode is definitely needed. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Tested-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2e0413c..7a6112e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -847,6 +847,7 @@ gen8_ring_sync(struct intel_engine_cs *waiter, intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | + MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_GTE_SDD); intel_ring_emit(waiter, seqno); intel_ring_emit(waiter, -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/i915: Extract semaphore error collection
From: Ben Widawsky benjamin.widaw...@intel.com
v2: s/ring_buffer/engine_cs (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 66cf417..9d42b6a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -746,6 +746,23 @@ static void i915_gem_record_fences(struct drm_device *dev,
}
}
+
+static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
+ struct intel_engine_cs *ring,
+ struct drm_i915_error_ring *ering)
+{
+ ering-semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring-mmio_base));
+ ering-semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring-mmio_base));
+ ering-semaphore_seqno[0] = ring-semaphore.sync_seqno[0];
+ ering-semaphore_seqno[1] = ring-semaphore.sync_seqno[1];
+
+ if (HAS_VEBOX(dev_priv-dev)) {
+ ering-semaphore_mboxes[2] =
+ I915_READ(RING_SYNC_2(ring-mmio_base));
+ ering-semaphore_seqno[2] = ring-semaphore.sync_seqno[2];
+ }
+}
+
static void i915_record_ring_state(struct drm_device *dev,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
@@ -755,18 +772,7 @@ static void i915_record_ring_state(struct drm_device *dev,
if (INTEL_INFO(dev)-gen = 6) {
ering-rc_psmi = I915_READ(ring-mmio_base + 0x50);
ering-fault_reg = I915_READ(RING_FAULT_REG(ring));
- ering-semaphore_mboxes[0]
- = I915_READ(RING_SYNC_0(ring-mmio_base));
- ering-semaphore_mboxes[1]
- = I915_READ(RING_SYNC_1(ring-mmio_base));
- ering-semaphore_seqno[0] = ring-semaphore.sync_seqno[0];
- ering-semaphore_seqno[1] = ring-semaphore.sync_seqno[1];
- }
-
- if (HAS_VEBOX(dev)) {
- ering-semaphore_mboxes[2] =
- I915_READ(RING_SYNC_2(ring-mmio_base));
- ering-semaphore_seqno[2] = ring-semaphore.sync_seqno[2];
+ gen6_record_semaphore_state(dev_priv, ring, ering);
}
if (INTEL_INFO(dev)-gen = 4) {
--
1.9.3
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Move compressed_fb to static allocation
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
On Thu, Jun 19, 2014 at 12:06 PM, Ben Widawsky benjamin.widaw...@intel.com
wrote:
We are already using the size to determine whether or not to free the
object, so there is no functional change there. Almost everything else
has changed to static allocations of the drm_mm_node too.
Aside from bringing this inline with much of our other code, this makes
error paths slightly simpler, which benefits the look of an upcoming
patch.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 27 ++-
2 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 0640071..0003206 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -605,7 +605,7 @@ struct i915_fbc {
enum plane plane;
int y;
- struct drm_mm_node *compressed_fb;
+ struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
struct intel_fbc_work {
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 6441178..642fd36 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -106,27 +106,25 @@ static unsigned long i915_stolen_to_physical(struct
drm_device *dev)
static int i915_setup_compression(struct drm_device *dev, int size)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- struct drm_mm_node *compressed_fb,
*uninitialized_var(compressed_llb);
+ struct drm_mm_node *uninitialized_var(compressed_llb);
int ret;
- compressed_fb = kzalloc(sizeof(*compressed_fb), GFP_KERNEL);
- if (!compressed_fb)
- goto err_llb;
-
/* Try to over-allocate to reduce reallocations and fragmentation
*/
- ret = drm_mm_insert_node(dev_priv-mm.stolen, compressed_fb,
+ ret = drm_mm_insert_node(dev_priv-mm.stolen,
+dev_priv-fbc.compressed_fb,
size = 1, 4096, DRM_MM_SEARCH_DEFAULT);
if (ret)
- ret = drm_mm_insert_node(dev_priv-mm.stolen,
compressed_fb,
+ ret = drm_mm_insert_node(dev_priv-mm.stolen,
+dev_priv-fbc.compressed_fb,
size = 1, 4096,
DRM_MM_SEARCH_DEFAULT);
if (ret)
goto err_llb;
if (HAS_PCH_SPLIT(dev))
- I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb-start);
+ I915_WRITE(ILK_DPFC_CB_BASE,
dev_priv-fbc.compressed_fb.start);
else if (IS_GM45(dev)) {
- I915_WRITE(DPFC_CB_BASE, compressed_fb-start);
+ I915_WRITE(DPFC_CB_BASE,
dev_priv-fbc.compressed_fb.start);
} else {
compressed_llb = kzalloc(sizeof(*compressed_llb),
GFP_KERNEL);
if (!compressed_llb)
@@ -140,12 +138,11 @@ static int i915_setup_compression(struct drm_device
*dev, int size)
dev_priv-fbc.compressed_llb = compressed_llb;
I915_WRITE(FBC_CFB_BASE,
- dev_priv-mm.stolen_base +
compressed_fb-start);
+ dev_priv-mm.stolen_base +
dev_priv-fbc.compressed_fb.start);
I915_WRITE(FBC_LL_BASE,
dev_priv-mm.stolen_base +
compressed_llb-start);
}
- dev_priv-fbc.compressed_fb = compressed_fb;
dev_priv-fbc.size = size;
DRM_DEBUG_KMS(reserved %d bytes of contiguous stolen space for
FBC\n,
@@ -155,9 +152,8 @@ static int i915_setup_compression(struct drm_device
*dev, int size)
err_fb:
kfree(compressed_llb);
- drm_mm_remove_node(compressed_fb);
+ drm_mm_remove_node(dev_priv-fbc.compressed_fb);
err_llb:
- kfree(compressed_fb);
pr_info_once(drm: not enough stolen space for compressed buffer
(need %d more bytes), disabling. Hint: you may be able to increase stolen
memory size in the BIOS to avoid this.\n, size);
return -ENOSPC;
}
@@ -185,10 +181,7 @@ void i915_gem_stolen_cleanup_compression(struct
drm_device *dev)
if (dev_priv-fbc.size == 0)
return;
- if (dev_priv-fbc.compressed_fb) {
- drm_mm_remove_node(dev_priv-fbc.compressed_fb);
- kfree(dev_priv-fbc.compressed_fb);
- }
+ drm_mm_remove_node(dev_priv-fbc.compressed_fb);
if (dev_priv-fbc.compressed_llb) {
drm_mm_remove_node(dev_priv-fbc.compressed_llb);
--
2.0.0
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--
Rodrigo Vivi
Blog
Re: [Intel-gfx] [PATCH] drm/i915: Try harder to get FBC
Jani, please ignore the 4th patch on this series and merge the 3 I've
reviewed and tested already.
They are essential to allow FBC work on BDW without changing bios
configuration and allow PC7 residency.
Thanks,
Rodrigo.
On Mon, Jun 30, 2014 at 10:41 AM, Rodrigo Vivi rodrigo.v...@intel.com
wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The GEN FBC unit provides the ability to set a low pass on frames it
attempts to compress. If a frame is less than a certain amount
compressibility (2:1, 4:1) it will not bother. This allows the driver to
reduce the size it requests out of stolen memory.
Unluckily, a few months ago, Ville actually began using this feature for
framebuffers that are 16bpp (not sure why not 8bpp). In those cases, we
are already using this mechanism for a different purpose, and so we can
only achieve one further level of compression (2:1 - 4:1)
FBC GEN1, ie. pre-G45 is ignored.
The cleverness of the patch is Art's. The bugs are mine.
v2: Update message and including missing threshold case 3 (Spotted by
Arthur).
Reviewedby: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Art Runyan arthur.j.run...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 3 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 54
+-
drivers/gpu/drm/i915/intel_pm.c| 30 +--
3 files changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 5b7aed2..9953ea8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -600,6 +600,7 @@ struct intel_context {
struct i915_fbc {
unsigned long size;
+ unsigned threshold;
unsigned int fb_id;
enum plane plane;
int y;
@@ -2489,7 +2490,7 @@ static inline void i915_gem_chipset_flush(struct
drm_device *dev)
/* i915_gem_stolen.c */
int i915_gem_init_stolen(struct drm_device *dev);
-int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
+int i915_gem_stolen_setup_compression(struct drm_device *dev, int size,
int fb_cpp);
void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index a86b331..b695d18 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -105,35 +105,61 @@ static unsigned long i915_stolen_to_physical(struct
drm_device *dev)
static int find_compression_threshold(struct drm_device *dev,
struct drm_mm_node *node,
- int size)
+ int size,
+ int fb_cpp)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- const int compression_threshold = 1;
+ int compression_threshold = 1;
int ret;
- /* Try to over-allocate to reduce reallocations and fragmentation
*/
+ /* HACK: This code depends on what we will do in *_enable_fbc. If
that
+* code changes, this code needs to change as well.
+*
+* The enable_fbc code will attempt to use one of our 2 compression
+* thresholds, therefore, in that case, we only have 1 resort.
+*/
+
+ /* Try to over-allocate to reduce reallocations and fragmentation.
*/
ret = drm_mm_insert_node(dev_priv-mm.stolen, node,
size = 1, 4096, DRM_MM_SEARCH_DEFAULT);
- if (ret)
- ret = drm_mm_insert_node(dev_priv-mm.stolen, node,
-size = 1, 4096,
-DRM_MM_SEARCH_DEFAULT);
- if (ret)
+ if (ret == 0)
+ return compression_threshold;
+
+again:
+ /* HW's ability to limit the CFB is 1:4 */
+ if (compression_threshold 4 ||
+ (fb_cpp == 2 compression_threshold == 2))
return 0;
- else
+
+ ret = drm_mm_insert_node(dev_priv-mm.stolen, node,
+size = 1, 4096,
+DRM_MM_SEARCH_DEFAULT);
+ if (ret INTEL_INFO(dev)-gen = 4) {
+ return 0;
+ } else if (ret) {
+ compression_threshold = 1;
+ goto again;
+ } else {
return compression_threshold;
+ }
}
-static int i915_setup_compression(struct drm_device *dev, int size)
+static int i915_setup_compression(struct drm_device *dev, int size, int
fb_cpp)
{
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_mm_node *uninitialized_var(compressed_llb);
int ret;
ret
[Intel-gfx] [PATCH] drm/i915: Fix VCS2's ring name.
It just fix a typo. v2: removing underscore to let this like all other ring names (Oscar) Cc: Oscar Mateo oscar.ma...@intel.com Reviewed-by (v1): Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2faef26..22c2b9a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2224,7 +2224,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) return -EINVAL; } - ring-name = bds2_ring; + ring-name = bsd2 ring; ring-id = VCS2; ring-write_tail = ring_write_tail; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/10] drm-intel-collector - update
This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector It was 4 rounds out of date what made it hard to get old patches. However Daniel and Jani didn't leave many patches behind. 0 on Apr 4 - Apr 16 1 on Apr 16 - May 6 2 on May 6 - May 23 3 on May 23 - Jun 6 Next round Jun 6 to Jun 20 is only after next drm-intel-testing update. Here goes the update list in order for better reviewers assignment: Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer: Paulo Zanoni paulo.r.zan...@intel.com - Reviewer: Patch drm/i915: Don't save/restore RS when not used - Reviewer: Patch drm/i915: Upgrade execbuffer fail after resume failure to EIO - Reviewer: Patch drm/i915: Add property to set HDMI aspect ratio - Reviewer: Ville Syrjälä ville.syrj...@linux.intel.com - Reviewer: Patch drm/i915/vlv: WA for Turbo and RC6 to work together. - Reviewer: Patch drm/i915: honour forced connector modes - Reviewer: Patch drm/i915: HWS must be in the mappable region for g33 - Reviewer: Patch drm/i915: Don't promote UC to WT automagically - Reviewer: Patch drm/i915/bdw: Always issue a force restore - Reviewer: Patch drm/i915/vlv: T12 eDP panel timing enforcement during reboot. - Reviewer: There are some reasons that some patches can be left behind: 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts. 2. Kernel didn't compiled with your patch. 3. I simply missed it. If you believe this is the case please warn me. 4. Remind that any reply to your email automatically take your patch to next round. Please help me to get these patches reviewed and queued by Daniel. Thanks, Rodrigo. Ben Widawsky (2): drm/i915: Don't save/restore RS when not used drm/i915/bdw: Always issue a force restore Chris Wilson (3): drm/i915: Upgrade execbuffer fail after resume failure to EIO drm/i915: honour forced connector modes drm/i915: HWS must be in the mappable region for g33 Clint Taylor (1): drm/i915/vlv: T12 eDP panel timing enforcement during reboot. Deepak S (2): drm/i915: Bring UP Power Wells before disabling RC6. drm/i915/vlv: WA for Turbo and RC6 to work together. Vandana Kannan (1): drm/i915: Add property to set HDMI aspect ratio Ville Syrjälä (1): drm/i915: Don't promote UC to WT automagically drivers/gpu/drm/i915/i915_drv.h| 16 drivers/gpu/drm/i915/i915_gem.c| 9 +- drivers/gpu/drm/i915/i915_gem_context.c| 15 ++-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++- drivers/gpu/drm/i915/i915_irq.c| 133 - drivers/gpu/drm/i915/i915_reg.h| 11 +++ drivers/gpu/drm/i915/intel_dp.c| 42 + drivers/gpu/drm/i915/intel_drv.h | 4 + drivers/gpu/drm/i915/intel_fbdev.c | 33 +++ drivers/gpu/drm/i915/intel_hdmi.c | 12 +++ drivers/gpu/drm/i915/intel_modes.c | 28 ++ drivers/gpu/drm/i915/intel_pm.c| 18 +++- drivers/gpu/drm/i915/intel_ringbuffer.c| 16 +++- 13 files changed, 318 insertions(+), 34 deletions(-) -- 1.9.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/10] drm/i915: Bring UP Power Wells before disabling RC6.
From: Deepak S deepa...@intel.com
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Reviewer: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Deepak S deepa...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d771e82..1e4611a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3354,8 +3354,14 @@ static void valleyview_disable_rps(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ /* we're doing forcewake before Disabling RC6,
+* This what the BIOS expects when going into suspend */
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
I915_WRITE(GEN6_RC_CONTROL, 0);
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
gen6_disable_rps_interrupts(dev);
}
--
1.9.0
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[Intel-gfx] [PATCH 02/10] drm/i915: Don't save/restore RS when not used
From: Ben Widawsky benjamin.widaw...@intel.com
Cc: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 21eda88..633e318 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -545,6 +545,7 @@ mi_set_context(struct intel_engine_cs *ring,
struct intel_context *new_context,
u32 hw_flags)
{
+ u32 flags = hw_flags | MI_MM_SPACE_GTT;
int ret;
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
@@ -558,6 +559,10 @@ mi_set_context(struct intel_engine_cs *ring,
return ret;
}
+ /* These flags are for resource streamer on HSW+ */
+ if (!IS_HASWELL(ring-dev) INTEL_INFO(ring-dev)-gen 8)
+ flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
+
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
@@ -570,11 +575,8 @@ mi_set_context(struct intel_engine_cs *ring,
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
- intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context-obj) |
- MI_MM_SPACE_GTT |
- MI_SAVE_EXT_STATE_EN |
- MI_RESTORE_EXT_STATE_EN |
- hw_flags);
+ intel_ring_emit(ring,
+ i915_gem_obj_ggtt_offset(new_context-obj) | flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
--
1.9.0
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[Intel-gfx] [PATCH 00/10] drm-intel-collector - update
This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector It was 4 rounds out of date what made it hard to get old patches. However Daniel and Jani didn't leave many patches behind. 0 on Apr 4 - Apr 16 1 on Apr 16 - May 6 2 on May 6 - May 23 3 on May 23 - Jun 6 Next round Jun 6 to Jun 20 is only after next drm-intel-testing update. Here goes the update list in order for better reviewers assignment: Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer: Paulo Zanoni paulo.r.zan...@intel.com - Reviewer: Patch drm/i915: Don't save/restore RS when not used - Reviewer: Patch drm/i915: Upgrade execbuffer fail after resume failure to EIO - Reviewer: Patch drm/i915: Add property to set HDMI aspect ratio - Reviewer: Ville Syrjälä ville.syrj...@linux.intel.com - Reviewer: Patch drm/i915/vlv: WA for Turbo and RC6 to work together. - Reviewer: Patch drm/i915: honour forced connector modes - Reviewer: Patch drm/i915: HWS must be in the mappable region for g33 - Reviewer: Patch drm/i915: Don't promote UC to WT automagically - Reviewer: Patch drm/i915/bdw: Always issue a force restore - Reviewer: Patch drm/i915/vlv: T12 eDP panel timing enforcement during reboot. - Reviewer: There are some reasons that some patches can be left behind: 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts. 2. Kernel didn't compiled with your patch. 3. I simply missed it. If you believe this is the case please warn me. 4. Remind that any reply to your email automatically take your patch to next round. Please help me to get these patches reviewed and queued by Daniel. Thanks, Rodrigo. Ben Widawsky (2): drm/i915: Don't save/restore RS when not used drm/i915/bdw: Always issue a force restore Chris Wilson (3): drm/i915: Upgrade execbuffer fail after resume failure to EIO drm/i915: honour forced connector modes drm/i915: HWS must be in the mappable region for g33 Clint Taylor (1): drm/i915/vlv: T12 eDP panel timing enforcement during reboot. Deepak S (2): drm/i915: Bring UP Power Wells before disabling RC6. drm/i915/vlv: WA for Turbo and RC6 to work together. Vandana Kannan (1): drm/i915: Add property to set HDMI aspect ratio Ville Syrjälä (1): drm/i915: Don't promote UC to WT automagically drivers/gpu/drm/i915/i915_drv.h| 16 drivers/gpu/drm/i915/i915_gem.c| 9 +- drivers/gpu/drm/i915/i915_gem_context.c| 15 ++-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++- drivers/gpu/drm/i915/i915_irq.c| 133 - drivers/gpu/drm/i915/i915_reg.h| 11 +++ drivers/gpu/drm/i915/intel_dp.c| 42 + drivers/gpu/drm/i915/intel_drv.h | 4 + drivers/gpu/drm/i915/intel_fbdev.c | 33 +++ drivers/gpu/drm/i915/intel_hdmi.c | 12 +++ drivers/gpu/drm/i915/intel_modes.c | 28 ++ drivers/gpu/drm/i915/intel_pm.c| 18 +++- drivers/gpu/drm/i915/intel_ringbuffer.c| 16 +++- 13 files changed, 318 insertions(+), 34 deletions(-) -- 1.9.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] drm/i915: Upgrade execbuffer fail after resume failure to EIO
From: Chris Wilson ch...@chris-wilson.co.uk
If we try to execute on a known ring, but it has failed to be
initialised correctly, report that the GPU is hung rather than the
command invalid. This leaves us reporting EINVAL only if the user
requests execution on a ring that is not supported by the device.
This should prevent UXA from getting stuck in a null render loop after a
failed resume.
v2 (Rodrigo): Fix conflict and add VCS2 ring and
s/intel_ring_buffer/intel_engine_cs.
Reported-by: Jiri Kosina ji...@jikos.cz
References: https://bugs.freedesktop.org/show_bug.cgi?id=76554
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d815ef5..23786ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1076,6 +1076,19 @@ eb_get_batch(struct eb_vmas *eb)
return vma-obj;
}
+static bool
+intel_ring_valid(struct intel_engine_cs *ring)
+{
+ switch (ring-id) {
+ case RCS: return true;
+ case VCS: return HAS_BSD(ring-dev);
+ case BCS: return HAS_BLT(ring-dev);
+ case VECS: return HAS_VEBOX(ring-dev);
+ case VCS2: return HAS_BSD2(ring-dev);
+ default: return false;
+ }
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file,
@@ -1133,7 +1146,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (!intel_ring_initialized(ring)) {
DRM_DEBUG(execbuf with invalid ring: %d\n,
(int)(args-flags I915_EXEC_RING_MASK));
- return -EINVAL;
+ return intel_ring_valid(ring) ? -EIO : -EINVAL;
}
mode = args-flags I915_EXEC_CONSTANTS_MASK;
--
1.9.0
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[Intel-gfx] [PATCH 04/10] drm/i915: Add property to set HDMI aspect ratio
From: Vandana Kannan vandana.kan...@intel.com
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode set.
v2: Daniel's review comments incorporated.
Call for a mode set to update property.
Reviewer: Ville Syrjälä ville.syrj...@linux.intel.com
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Jesse Barnes jesse.bar...@intel.com
Cc: Vijay Purushothaman vijay.a.purushotha...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 12
drivers/gpu/drm/i915/intel_modes.c | 28
4 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..1bf277e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1529,6 +1529,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *aspect_ratio_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5f7c7bd..7b4d743 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -495,6 +495,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
@@ -923,6 +924,7 @@ int intel_connector_update_modes(struct drm_connector
*connector,
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+void intel_attach_aspect_ratio_property(struct drm_connector *connector);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2422413..1851284 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode-picture_aspect_ratio = intel_hdmi-aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(frame.avi,
adjusted_mode);
if (ret 0) {
@@ -1124,6 +1127,11 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == dev_priv-aspect_ratio_property) {
+ intel_hdmi-aspect_ratio = val;
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1484,6 +1492,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_aspect_ratio_property(connector);
intel_hdmi-color_range_auto = true;
}
@@ -1551,6 +1560,9 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector-get_hw_state = intel_connector_get_hw_state;
intel_connector-unregister = intel_connector_unregister;
+ /* Initialize aspect ratio member of intel_hdmi */
+ intel_hdmi-aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
intel_hdmi_add_properties(intel_hdmi, connector);
intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index 0e860f3..6f814da 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,31 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
drm_object_attach_property(connector-base, prop, 0);
}
+
+static const struct drm_prop_enum_list aspect_ratio_names[] = {
+ { HDMI_PICTURE_ASPECT_NONE, Automatic },
+ { HDMI_PICTURE_ASPECT_4_3, 4:3 },
+ { HDMI_PICTURE_ASPECT_16_9, 16:9 },
+};
+
+void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector-dev;
+ struct drm_i915_private *dev_priv
[Intel-gfx] [PATCH 10/10] drm/i915/vlv: T12 eDP panel timing enforcement during reboot.
From: Clint Taylor clinton.a.tay...@intel.com
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2: removed redundant pr_crit(), commented magic value for pp_div_reg
Ver3: moved SYS_RESTART check earlier, new name for pp_div.
Signed-off-by: Clint Taylor clinton.a.tay...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 42
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..ece8f28 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,6 +28,8 @@
#include linux/i2c.h
#include linux/slab.h
#include linux/export.h
+#include linux/notifier.h
+#include linux/reboot.h
#include drm/drmP.h
#include drm/drm_crtc.h
#include drm/drm_crtc_helper.h
@@ -336,6 +338,38 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}
+/* Reboot notifier handler to shutdown panel power to guarantee T12 timing */
+static int edp_notify_handler(struct notifier_block *this, unsigned long code,
+ void *unused)
+{
+ struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
+edp_notifier);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 pp_div;
+ u32 pp_ctrl_reg, pp_div_reg;
+ enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+ if ((!is_edp(intel_dp))
+ (code != SYS_RESTART ))
+ return 0;
+
+ if (IS_VALLEYVIEW(dev)) {
+ pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+ pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
+ pp_div = I915_READ(VLV_PIPE_PP_DIVISOR(pipe));
+ pp_div = PP_REFERENCE_DIVIDER_MASK;
+
+ /* 0x1F write to PP_DIV_REG sets max cycle delay */
+ I915_WRITE(pp_div_reg , pp_div | 0x1F);
+ I915_WRITE(pp_ctrl_reg,
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ msleep(intel_dp-panel_power_cycle_delay);
+ }
+ return 0;
+}
+
static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -3785,6 +3819,10 @@ void intel_dp_encoder_destroy(struct drm_encoder
*encoder)
drm_modeset_lock(dev-mode_config.connection_mutex, NULL);
edp_panel_vdd_off_sync(intel_dp);
drm_modeset_unlock(dev-mode_config.connection_mutex);
+ if (intel_dp-edp_notifier.notifier_call) {
+ unregister_reboot_notifier(intel_dp-edp_notifier);
+ intel_dp-edp_notifier.notifier_call = NULL;
+ }
}
kfree(intel_dig_port);
}
@@ -4353,6 +4391,10 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
if (is_edp(intel_dp)) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_init_panel_power_sequencer(dev, intel_dp, power_seq);
+ if (IS_VALLEYVIEW(dev)) {
+ intel_dp-edp_notifier.notifier_call =
edp_notify_handler;
+ register_reboot_notifier(intel_dp-edp_notifier);
+ }
}
intel_dp_aux_init(intel_dp, intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b4d743..c52e879 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -542,6 +542,8 @@ struct intel_dp {
unsigned long last_power_cycle;
unsigned long last_power_on;
unsigned long last_backlight_off;
+ struct notifier_block edp_notifier;
+
bool use_tps3;
struct intel_connector *attached_connector;
--
1.9.0
___
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[Intel-gfx] [PATCH 09/10] drm/i915/bdw: Always issue a force restore
From: Ben Widawsky benjamin.widaw...@intel.com The PDPs seem to get screwed up otherwise, specifically PDP0. I am not really clear why this is required, it just works with full PPGTT. v2: Only do it for gen8, to limit regression potential v3: Fix the bugzilla links Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 633e318..61b60b6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -573,6 +573,9 @@ mi_set_context(struct intel_engine_cs *ring, else intel_ring_emit(ring, MI_NOOP); + if (INTEL_INFO(ring-dev)-gen == 8) + hw_flags |= MI_FORCE_RESTORE; + intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_SET_CONTEXT); intel_ring_emit(ring, -- 1.9.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/i915: honour forced connector modes
From: Chris Wilson ch...@chris-wilson.co.uk
In the move over to use BIOS connector configs, we lost the ability to
force a specific set of connectors on or off. Try to remedy that by
dropping back to the old behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).
Based on earlier patches by Jesse Barnes.
v2: Remove Jesse's patch
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 33 -
1 file changed, 12 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 226fbc7..34c1a3d 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -331,24 +331,6 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
int num_connectors_enabled = 0;
int num_connectors_detected = 0;
- /*
-* If the user specified any force options, just bail here
-* and use that config.
-*/
- for (i = 0; i fb_helper-connector_count; i++) {
- struct drm_fb_helper_connector *fb_conn;
- struct drm_connector *connector;
-
- fb_conn = fb_helper-connector_info[i];
- connector = fb_conn-connector;
-
- if (!enabled[i])
- continue;
-
- if (connector-force != DRM_FORCE_UNSPECIFIED)
- return false;
- }
-
save_enabled = kcalloc(dev-mode_config.num_connector, sizeof(bool),
GFP_KERNEL);
if (!save_enabled)
@@ -374,8 +356,18 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
continue;
}
+ if (connector-force == DRM_FORCE_OFF) {
+ DRM_DEBUG_KMS(connector %s is disabled by user,
skipping\n,
+ connector-name);
+ enabled[i] = false;
+ continue;
+ }
+
encoder = connector-encoder;
if (!encoder || WARN_ON(!encoder-crtc)) {
+ if (connector-force DRM_FORCE_OFF)
+ goto bail;
+
DRM_DEBUG_KMS(connector %s has no encoder or crtc,
skipping\n,
connector-name);
enabled[i] = false;
@@ -394,8 +386,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
for (j = 0; j fb_helper-connector_count; j++) {
if (crtcs[j] == new_crtc) {
DRM_DEBUG_KMS(fallback: cloned
configuration\n);
- fallback = true;
- goto out;
+ goto bail;
}
}
@@ -466,8 +457,8 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
fallback = true;
}
-out:
if (fallback) {
+bail:
DRM_DEBUG_KMS(Not using firmware configuration\n);
memcpy(enabled, save_enabled, dev-mode_config.num_connector);
kfree(save_enabled);
--
1.9.0
___
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Re: [Intel-gfx] [PATCH 09/10] drm/i915/bdw: Always issue a force restore
Thanks Please just ignore this one for now. It will be removed on next round. On Thu, Jul 3, 2014 at 5:38 PM, Ben Widawsky benjamin.widaw...@intel.com wrote: On Thu, Jul 03, 2014 at 05:33:05PM -0400, Rodrigo Vivi wrote: From: Ben Widawsky benjamin.widaw...@intel.com The PDPs seem to get screwed up otherwise, specifically PDP0. I am not really clear why this is required, it just works with full PPGTT. v2: Only do it for gen8, to limit regression potential v3: Fix the bugzilla links Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 633e318..61b60b6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -573,6 +573,9 @@ mi_set_context(struct intel_engine_cs *ring, else intel_ring_emit(ring, MI_NOOP); + if (INTEL_INFO(ring-dev)-gen == 8) + hw_flags |= MI_FORCE_RESTORE; + intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_SET_CONTEXT); intel_ring_emit(ring, Ville had a good point on this patch wrt to note setting both MI_FORCE_RESTORE, and MI_RESTORE_INHIBIT (though it seems to cause no problems). I think also with some of the do_switch() cleanups recently submitted, this one may no longer be necessary - not sure. -- Ben Widawsky, Intel Open Source Technology Center -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Implement MI decode for gen8
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
v2: fix typo. Removing spurious 0% from debug msg 0x%0%0. (Daniel)
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 42 ++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0217a41..05264ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2784,12 +2784,7 @@ static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
if (INTEL_INFO(dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return false;
+ return (ipehr 23) == 0x1c;
} else {
ipehr = ~MI_SEMAPHORE_SYNC_MASK;
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
@@ -2798,19 +2793,20 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32
ipehr)
}
static struct intel_engine_cs *
-semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
+semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64
offset)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct intel_engine_cs *signaller;
int i;
if (INTEL_INFO(dev_priv-dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return NULL;
+ for_each_ring(signaller, dev_priv, i) {
+ if (ring == signaller)
+ continue;
+
+ if (offset ==
signaller-semaphore.signal_ggtt[ring-id])
+ return signaller;
+ }
} else {
u32 sync_bits = ipehr MI_SEMAPHORE_SYNC_MASK;
@@ -2823,8 +2819,8 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring, u32 ipehr)
}
}
- DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x\n,
- ring-id, ipehr);
+ DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x, offset
0x%016llx\n,
+ ring-id, ipehr, offset);
return NULL;
}
@@ -2834,7 +2830,8 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
u32 cmd, ipehr, head;
- int i;
+ u64 offset = 0;
+ int i, backwards;
ipehr = I915_READ(RING_IPEHR(ring-mmio_base));
if (!ipehr_is_semaphore_wait(ring-dev, ipehr))
@@ -2843,13 +2840,15 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
/*
* HEAD is likely pointing to the dword after the actual command,
* so scan backwards until we find the MBOX. But limit it to just 3
-* dwords. Note that we don't care about ACTHD here since that might
+* or 4 dwords depending on the semaphore wait command size.
+* Note that we don't care about ACTHD here since that might
* point at at batch, and semaphores are always emitted into the
* ringbuffer itself.
*/
head = I915_READ_HEAD(ring) HEAD_ADDR;
+ backwards = (INTEL_INFO(ring-dev)-gen = 8) ? 5 : 4;
- for (i = 4; i; --i) {
+ for (i = backwards; i; --i) {
/*
* Be paranoid and presume the hw has gone off into the wild -
* our ring is smaller than what the hardware (and hence
@@ -2869,7 +2868,12 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
return NULL;
*seqno = ioread32(ring-buffer-virtual_start + head + 4) + 1;
- return semaphore_wait_to_signaller_ring(ring, ipehr);
+ if (INTEL_INFO(ring-dev)-gen = 8) {
+ offset = ioread32(ring-buffer-virtual_start + head + 12);
+ offset = 32;
+ offset = ioread32(ring-buffer-virtual_start + head + 8);
+ }
+ return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
}
static int semaphore_passed(struct intel_engine_cs *ring)
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.
v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 6 ++
4 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c1b88a8..b049fc5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1510,6 +1510,47 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_fbc_fc_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (INTEL_INFO(dev)-gen 5)
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+ *val = dev_priv-fbc.false_color;
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+static int i915_fbc_fc_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg;
+
+ if (INTEL_INFO(dev)-gen 5)
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+
+ reg = I915_READ(ILK_DPFC_CONTROL);
+ dev_priv-fbc.false_color = val;
+
+ I915_WRITE(ILK_DPFC_CONTROL, val ?
+ (reg | FBC_CTL_FALSE_COLOR) :
+ (reg ~FBC_CTL_FALSE_COLOR));
+
+ drm_modeset_unlock_all(dev);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
+ i915_fbc_fc_get, i915_fbc_fc_set,
+ %llu\n);
+
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m-private;
@@ -3996,6 +4037,7 @@ static const struct i915_debugfs_files {
{i915_pri_wm_latency, i915_pri_wm_latency_fops},
{i915_spr_wm_latency, i915_spr_wm_latency_fops},
{i915_cur_wm_latency, i915_cur_wm_latency_fops},
+ {i915_fbc_false_color, i915_fbc_fc_fops},
};
void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04fc3f2..397b838 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -609,6 +609,8 @@ struct i915_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
+ bool false_color;
+
struct intel_fbc_work {
struct delayed_work work;
struct drm_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8353075..3c7b24e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1509,6 +1509,7 @@ enum punit_power_well {
/* Framebuffer compression for Ironlake */
#define ILK_DPFC_CB_BASE 0x43200
#define ILK_DPFC_CONTROL 0x43208
+#define FBC_CTL_FALSE_COLOR (110)
/* The bit 28-8 is reserved */
#define DPFC_RESERVED(0x1F00)
#define ILK_DPFC_RECOMP_CTL0x4320c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f2a4056..b52097f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -247,6 +247,9 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc)
if (IS_GEN5(dev))
dpfc_ctl |= obj-fence_reg;
+ if (dev_priv-fbc.false_color)
+ dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc-y);
I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) |
ILK_FBC_RT_VALID);
/* enable it... */
@@ -313,6 +316,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
+ if (dev_priv-fbc.false_color)
+ dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
if (IS_IVYBRIDGE(dev)) {
--
1.9.1
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[Intel-gfx] [PATCH 11/11] drm/i915: Enable PSR by default.
Panel Self Refresh is an eDP power saving feature specified by VESA's eDP v1.3,
that allows some panel componets to shutdown while you still see static images
on
the screen. Besides being supported on the platform it must be supported by the
eDP panel itself.
Now that we have the propper frontbuffer tracking support and correct locks on
place
we can enabled this feature by default.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 8145729..bbdee21 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -37,7 +37,7 @@ struct i915_params i915 __read_mostly = {
.enable_fbc = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
- .enable_psr = 0,
+ .enable_psr = 1,
.preliminary_hw_support =
IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
.disable_power_well = 1,
.enable_ips = 1,
@@ -118,7 +118,7 @@ MODULE_PARM_DESC(enable_ppgtt,
(-1=auto [default], 0=disabled, 1=aliasing, 2=full));
module_param_named(enable_psr, i915.enable_psr, int, 0600);
-MODULE_PARM_DESC(enable_psr, Enable PSR (default: false));
+MODULE_PARM_DESC(enable_psr, Enable PSR (default: true));
module_param_named(preliminary_hw_support, i915.preliminary_hw_support, int,
0600);
MODULE_PARM_DESC(preliminary_hw_support,
--
1.9.3
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[Intel-gfx] [PATCH 03/11] drm/i915: Track the psr dp connector in dev_priv-psr.enabled
From: Daniel Vetter daniel.vet...@ffwll.ch
Trying to fish that one out through looping is a bit a locking
nightmare. So just set it and use it in the work struct.
v2:
- Don't Oops in psr_work, spotted by Rodrigo.
- Fix compile warning.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_dp.c | 22 +-
3 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 981ca42..62ea619 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1894,7 +1894,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support));
seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok));
- seq_printf(m, Enabled: %s\n, yesno(dev_priv-psr.enabled));
+ seq_printf(m, Enabled: %s\n, yesno((bool)dev_priv-psr.enabled));
seq_printf(m, Active: %s\n, yesno(dev_priv-psr.active));
enabled = HAS_PSR(dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91f137f..1ec4d4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -654,10 +654,11 @@ struct i915_drrs {
struct intel_connector *connector;
};
+struct intel_dp;
struct i915_psr {
bool sink_support;
bool source_ok;
- bool enabled;
+ struct intel_dp *enabled;
bool active;
struct delayed_work work;
};
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cb57494..a07d192 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1876,7 +1876,7 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
/* Enable PSR on the host */
intel_edp_psr_enable_source(intel_dp);
- dev_priv-psr.enabled = true;
+ dev_priv-psr.enabled = intel_dp;
dev_priv-psr.active = true;
}
@@ -1917,26 +1917,22 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
DRM_ERROR(Timed out waiting for PSR Idle State\n);
- dev_priv-psr.enabled = false;
+ dev_priv-psr.enabled = NULL;
}
static void intel_edp_psr_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), psr.work.work);
- struct drm_device *dev = dev_priv-dev;
- struct intel_encoder *encoder;
- struct intel_dp *intel_dp = NULL;
+ struct intel_dp *intel_dp = dev_priv-psr.enabled;
- list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
- if (encoder-type == INTEL_OUTPUT_EDP) {
- intel_dp = enc_to_intel_dp(encoder-base);
+ if (!intel_dp)
+ return;
- if (!intel_edp_psr_match_conditions(intel_dp))
- intel_edp_psr_disable(intel_dp);
- else
- intel_edp_psr_do_enable(intel_dp);
- }
+ if (!intel_edp_psr_match_conditions(intel_dp))
+ intel_edp_psr_disable(intel_dp);
+ else
+ intel_edp_psr_do_enable(intel_dp);
}
static void intel_edp_psr_inactivate(struct drm_device *dev)
--
1.9.3
___
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[Intel-gfx] [PATCH 02/11] drm/i915: Add a FIXME about drrs/psr interactions
From: Daniel Vetter daniel.vet...@ffwll.ch
Can't review this right now due to lack of DRRS code.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 302cdaa..cb57494 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4141,6 +4141,11 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
return;
}
+ /*
+* FIXME: This needs proper synchronization with psr state. But really
+* hard to tell without seeing the user of this function of this code.
+* Check locking and ordering once that lands.
+*/
if (INTEL_INFO(dev)-gen 8 intel_edp_is_psr_enabled(dev)) {
DRM_DEBUG_KMS(DRRS is disabled as PSR is enabled\n);
return;
--
1.9.3
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[Intel-gfx] [PATCH 09/11] drm/i915: Improve PSR debugfs output
From: Daniel Vetter daniel.vet...@ffwll.ch Add busy_frontbuffer_bits and locking. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 62ea619..fc39610 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1892,10 +1892,15 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); + mutex_lock(dev_priv-psr.lock); seq_printf(m, Sink_Support: %s\n, yesno(dev_priv-psr.sink_support)); seq_printf(m, Source_OK: %s\n, yesno(dev_priv-psr.source_ok)); seq_printf(m, Enabled: %s\n, yesno((bool)dev_priv-psr.enabled)); seq_printf(m, Active: %s\n, yesno(dev_priv-psr.active)); + seq_printf(m, Busy frontbuffer bits: 0x%03x\n, + dev_priv-psr.busy_frontbuffer_bits); + seq_printf(m, Re-enable work scheduled: %s\n, + yesno(work_busy(dev_priv-psr.work.work))); enabled = HAS_PSR(dev) I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE; @@ -1905,6 +1910,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) EDP_PSR_PERF_CNT_MASK; seq_printf(m, Performance_Counter: %u\n, psrperf); + mutex_unlock(dev_priv-psr.lock); intel_runtime_pm_put(dev_priv); return 0; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/11] drm/i915: Lock down psr sw/hw state tracking
From: Daniel Vetter daniel.vet...@ffwll.ch
Make sure we track the sw side (psr.active) correctly and WARN
everywhere it might get out of sync with the hw.
v2: Fixup WARN_ON logic inversion, reported by Rodrigo.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bc3a2a4..b4e4bdc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1867,8 +1867,8 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- if (intel_edp_is_psr_enabled(dev))
- return;
+ WARN_ON(I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE);
+ WARN_ON(dev_priv-psr.active);
/* Enable PSR on the panel */
intel_edp_psr_enable_sink(intel_dp);
@@ -1909,13 +1909,19 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
if (!dev_priv-psr.enabled)
return;
- I915_WRITE(EDP_PSR_CTL(dev),
- I915_READ(EDP_PSR_CTL(dev)) ~EDP_PSR_ENABLE);
+ if (dev_priv-psr.active) {
+ I915_WRITE(EDP_PSR_CTL(dev),
+ I915_READ(EDP_PSR_CTL(dev)) ~EDP_PSR_ENABLE);
+
+ /* Wait till PSR is idle */
+ if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev))
+ EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
+ DRM_ERROR(Timed out waiting for PSR Idle State\n);
- /* Wait till PSR is idle */
- if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev))
- EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
- DRM_ERROR(Timed out waiting for PSR Idle State\n);
+ dev_priv-psr.active = false;
+ } else {
+ WARN_ON(I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE);
+ }
dev_priv-psr.enabled = NULL;
}
@@ -1933,16 +1939,6 @@ static void intel_edp_psr_work(struct work_struct *work)
intel_edp_psr_do_enable(intel_dp);
}
-static void intel_edp_psr_inactivate(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev-dev_private;
-
- dev_priv-psr.active = false;
-
- I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
- ~EDP_PSR_ENABLE);
-}
-
void intel_edp_psr_exit(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1955,8 +1951,15 @@ void intel_edp_psr_exit(struct drm_device *dev)
cancel_delayed_work_sync(dev_priv-psr.work);
- if (dev_priv-psr.active)
- intel_edp_psr_inactivate(dev);
+ if (dev_priv-psr.active) {
+ u32 val = I915_READ(EDP_PSR_CTL(dev));
+
+ WARN_ON(!(val EDP_PSR_ENABLE));
+
+ I915_WRITE(EDP_PSR_CTL(dev), val ~EDP_PSR_ENABLE);
+
+ dev_priv-psr.active = false;
+ }
schedule_delayed_work(dev_priv-psr.work,
msecs_to_jiffies(100));
--
1.9.3
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[Intel-gfx] [PATCH 08/11] drm/i915: Fix up PSR frontbuffer tracking
From: Daniel Vetter daniel.vet...@ffwll.ch
I've tried to split this up, but all the changes are so tightly
related that I didn't find a good way to do this without breaking
bisecting. Essentially this completely changes how psr is glued into
the overall driver, and there's not much you can do to soften such a
paradigm change.
- Use frontbuffer tracking bits stuff to separate disable and
re-enable.
- Don't re-check everything in the psr work. We have now accurate
tracking for everything, so no need to check for sprites or tiling
really. Allows us to ditch tons of locks.
- That in turn allows us to properly cancel the work in the disable
function - no more deadlocks.
- Add a check for HSW sprites and force a flush. Apparently the
hardware doesn't forward the flushing when updating the sprite base
address. We can do the same trick everywhere else we have such
issues, e.g. on baytrail with ... everything.
- Don't re-enable psr with a delay in psr_exit. It really must be
turned off forever if we detect a gtt write. At least with the
current frontbuffer render tracking. Userspace can do a busy ioctl
call or no-op pageflip to re-enable psr.
- Drop redundant checks for crtc and crtc-active - now that they're
only called from enable this is guaranteed.
- Fix up the hsw port check. eDP can also happen on port D, but the
issue is exactly that it doesn't work there. So an || check is
wrong.
- We still schedule the psr work with a delay. The frontbuffer
flushing interface mandates that we upload the next full frame, so
need to wait a bit. Once we have single-shot frame uploads we can do
better here.
v2: Don't enable psr initially, rely upon the fb flush of the initial
plane setup for that. Gives us more unified code flow and makes the
crtc enable sequence less a special case.
v3: s/psr_exit/psr_invalidate/ for consistency
v4: Fixup whitespace.
v5: Correctly bail out of psr_invalidate/flush when
dev_priv-psr.enabled is NULL. Spotted by Rodrigo.
v6:
- Only schedule work when there's work to do. Fixes WARNINGs reported
by Rodrigo.
- Comments Chris requested to clarify the code.
v7: Fix conflict on rebase (Rodrigo)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_dp.c | 124 ++-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
4 files changed, 85 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ae069b6..f48e452 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,6 +662,7 @@ struct i915_psr {
struct intel_dp *enabled;
bool active;
struct delayed_work work;
+ unsigned busy_frontbuffer_bits;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe6f1db..538fe31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8938,7 +8938,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj,
intel_mark_fb_busy(dev, obj-frontbuffer_bits, ring);
- intel_edp_psr_exit(dev);
+ intel_edp_psr_invalidate(dev, obj-frontbuffer_bits);
}
/**
@@ -8964,7 +8964,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
- intel_edp_psr_exit(dev);
+ intel_edp_psr_flush(dev, frontbuffer_bits);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a59d5a6..a8f8d00 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1797,8 +1797,6 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_crtc *crtc = dig_port-base.base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_i915_gem_object *obj = intel_fb_obj(crtc-primary-fb);
- struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
lockdep_assert_held(dev_priv-psr.lock);
lockdep_assert_held(dev-struct_mutex);
@@ -1812,8 +1810,7 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return false;
}
- if (IS_HASWELL(dev) (intel_encoder-type != INTEL_OUTPUT_EDP ||
- dig_port-port != PORT_A)) {
+ if (IS_HASWELL(dev) dig_port-port != PORT_A) {
DRM_DEBUG_KMS(HSW ties PSR to DDI A (eDP)\n);
return false;
}
@@ -1823,33 +1820,10 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
return false
[Intel-gfx] [PATCH 07/11] drm/i915: Add locking to psr code
From: Daniel Vetter daniel.vet...@ffwll.ch
It's not really optional to have locking ...
The ugly part is how much locking the psr work needs since it has to
recheck everything. Which is way too much. But we need to ditch the
psr work in it's current form anyway and implement proper frontbuffer
tracking.
The other nasty bit that had to go was the delayed work cancle in
psr_exit. Which means a bunch of races just became a bit more likely,
but mea culpa.
v2: Fixup HAS_PSR checks, resulting in uninitialized mutex issues.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 38 +++---
2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ec4d4a..ae069b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,6 +656,7 @@ struct i915_drrs {
struct intel_dp;
struct i915_psr {
+ struct mutex lock;
bool sink_support;
bool source_ok;
struct intel_dp *enabled;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5854ae6..a59d5a6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1800,6 +1800,11 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
struct drm_i915_gem_object *obj = intel_fb_obj(crtc-primary-fb);
struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
+ lockdep_assert_held(dev_priv-psr.lock);
+ lockdep_assert_held(dev-struct_mutex);
+ WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
+ WARN_ON(!drm_modeset_is_locked(crtc-mutex));
+
dev_priv-psr.source_ok = false;
if (!HAS_PSR(dev)) {
@@ -1869,6 +1874,7 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
WARN_ON(I915_READ(EDP_PSR_CTL(dev)) EDP_PSR_ENABLE);
WARN_ON(dev_priv-psr.active);
+ lockdep_assert_held(dev_priv-psr.lock);
/* Enable PSR on the panel */
intel_edp_psr_enable_sink(intel_dp);
@@ -1895,8 +1901,10 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
return;
}
+ mutex_lock(dev_priv-psr.lock);
if (dev_priv-psr.enabled) {
DRM_DEBUG_KMS(PSR already in use\n);
+ mutex_unlock(dev_priv-psr.lock);
return;
}
@@ -1905,6 +1913,7 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
if (intel_edp_psr_match_conditions(intel_dp))
intel_edp_psr_do_enable(intel_dp);
+ mutex_unlock(dev_priv-psr.lock);
}
void intel_edp_psr_disable(struct intel_dp *intel_dp)
@@ -1912,9 +1921,15 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev-dev_private;
- if (!dev_priv-psr.enabled)
+ if (!HAS_PSR(dev))
return;
+ mutex_lock(dev_priv-psr.lock);
+ if (!dev_priv-psr.enabled) {
+ mutex_unlock(dev_priv-psr.lock);
+ return;
+ }
+
if (dev_priv-psr.active) {
I915_WRITE(EDP_PSR_CTL(dev),
I915_READ(EDP_PSR_CTL(dev)) ~EDP_PSR_ENABLE);
@@ -1930,19 +1945,30 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
}
dev_priv-psr.enabled = NULL;
+ mutex_unlock(dev_priv-psr.lock);
}
static void intel_edp_psr_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), psr.work.work);
+ struct drm_device *dev = dev_priv-dev;
struct intel_dp *intel_dp = dev_priv-psr.enabled;
+ drm_modeset_lock_all(dev);
+ mutex_lock(dev-struct_mutex);
+ mutex_lock(dev_priv-psr.lock);
+ intel_dp = dev_priv-psr.enabled;
+
if (!intel_dp)
- return;
+ goto unlock;
if (intel_edp_psr_match_conditions(intel_dp))
intel_edp_psr_do_enable(intel_dp);
+unlock:
+ mutex_unlock(dev_priv-psr.lock);
+ mutex_unlock(dev-struct_mutex);
+ drm_modeset_unlock_all(dev);
}
void intel_edp_psr_exit(struct drm_device *dev)
@@ -1955,8 +1981,7 @@ void intel_edp_psr_exit(struct drm_device *dev)
if (!dev_priv-psr.enabled)
return;
- cancel_delayed_work_sync(dev_priv-psr.work);
-
+ mutex_lock(dev_priv-psr.lock);
if (dev_priv-psr.active) {
u32 val = I915_READ(EDP_PSR_CTL(dev));
@@ -1969,16 +1994,15 @@ void intel_edp_psr_exit(struct drm_device *dev)
schedule_delayed_work(dev_priv-psr.work,
msecs_to_jiffies(100));
+ mutex_unlock(dev_priv-psr.lock
[Intel-gfx] [PATCH 01/11] drm/i915: Run psr_setup unconditionally
From: Daniel Vetter daniel.vet...@ffwll.ch
Due to runtime pm and system s/r we need to restore hw state every
time we enable a pipe again. Hence trying to avoid that is just
pointless book-keeping which Rodrigo then tried to work around by
manually adding psr_setup calls to our resume code.
Much simpler to just remove code instead.
v2: Properly bail out of psr exit if psr isn't enabled. Spotted by
Rodrigo.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_dp.c | 7 +--
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a89c912..91f137f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -657,7 +657,6 @@ struct i915_drrs {
struct i915_psr {
bool sink_support;
bool source_ok;
- bool setup_done;
bool enabled;
bool active;
struct delayed_work work;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ae3737c..302cdaa 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1714,9 +1714,6 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev-dev_private;
struct edp_vsc_psr psr_vsc;
- if (dev_priv-psr.setup_done)
- return;
-
/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
memset(psr_vsc, 0, sizeof(psr_vsc));
psr_vsc.sdp_header.HB0 = 0;
@@ -1728,8 +1725,6 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp)
/* Avoid continuous PSR exit by masking memup and hpd */
I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
-
- dev_priv-psr.setup_done = true;
}
static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
@@ -1961,7 +1956,7 @@ void intel_edp_psr_exit(struct drm_device *dev)
if (!HAS_PSR(dev))
return;
- if (!dev_priv-psr.setup_done)
+ if (!dev_priv-psr.enabled)
return;
cancel_delayed_work_sync(dev_priv-psr.work);
--
1.9.3
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[Intel-gfx] [PATCH 06/11] drm/i915: More checks for psr.enabled
From: Daniel Vetter daniel.vet...@ffwll.ch
We need to make sure that no one else is using this in the
enable function and also that the work item hasn't raced
with the disabled function.
v2: Improve bisectability by moving one hunk to an earlier patch.
v3: added missing dev_priv declaration (Rodrigo)
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b4e4bdc..5854ae6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1883,6 +1883,7 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
if (!HAS_PSR(dev)) {
DRM_DEBUG_KMS(PSR not supported on this platform\n);
@@ -1894,6 +1895,11 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
return;
}
+ if (dev_priv-psr.enabled) {
+ DRM_DEBUG_KMS(PSR already in use\n);
+ return;
+ }
+
/* Setup PSR once */
intel_edp_psr_setup(intel_dp);
--
1.9.3
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[Intel-gfx] [PATCH 10/11] drm/i915: Remove redundant HAS_PSR checks
From: Daniel Vetter daniel.vet...@ffwll.ch
We only need to check for this in psr_enable, everything else is
already protect by the dev_priv-psr.enabled checks. Those need the
psr locking, but these functions are called infrequent enough that the
locking overhead is negligible.
Suggested by Chris Wilson.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a8f8d00..5498e12 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1805,11 +1805,6 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
dev_priv-psr.source_ok = false;
- if (!HAS_PSR(dev)) {
- DRM_DEBUG_KMS(PSR not supported on this platform\n);
- return false;
- }
-
if (IS_HASWELL(dev) dig_port-port != PORT_A) {
DRM_DEBUG_KMS(HSW ties PSR to DDI A (eDP)\n);
return false;
@@ -1896,9 +1891,6 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev-dev_private;
- if (!HAS_PSR(dev))
- return;
-
mutex_lock(dev_priv-psr.lock);
if (!dev_priv-psr.enabled) {
mutex_unlock(dev_priv-psr.lock);
@@ -1973,9 +1965,6 @@ void intel_edp_psr_invalidate(struct drm_device *dev,
struct drm_crtc *crtc;
enum pipe pipe;
- if (!HAS_PSR(dev))
- return;
-
mutex_lock(dev_priv-psr.lock);
if (!dev_priv-psr.enabled) {
mutex_unlock(dev_priv-psr.lock);
@@ -2000,9 +1989,6 @@ void intel_edp_psr_flush(struct drm_device *dev,
struct drm_crtc *crtc;
enum pipe pipe;
- if (!HAS_PSR(dev))
- return;
-
mutex_lock(dev_priv-psr.lock);
if (!dev_priv-psr.enabled) {
mutex_unlock(dev_priv-psr.lock);
--
1.9.3
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[Intel-gfx] [PATCH 04/11] drm/i915: Don't try to disable psr harder from the work item
From: Daniel Vetter daniel.vet...@ffwll.ch It's disabled already except when we've raced. Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a07d192..bc3a2a4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1929,9 +1929,7 @@ static void intel_edp_psr_work(struct work_struct *work) if (!intel_dp) return; - if (!intel_edp_psr_match_conditions(intel_dp)) - intel_edp_psr_disable(intel_dp); - else + if (intel_edp_psr_match_conditions(intel_dp)) intel_edp_psr_do_enable(intel_dp); } -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm,drm/i915: Export cmdline mode parsing
This patch got a conflict on latest -collector. Is it still needed? If yes, could you please rebase? I was also going to tell about the Make the pysical object coherent... but I noticed you already rebased. Thanks, Rodrigo. On Wed, May 14, 2014 at 1:46 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Wed, May 14, 2014 at 11:31:47AM +0300, Jani Nikula wrote: On Tue, 13 May 2014, Chris Wilson ch...@chris-wilson.co.uk wrote: i915.ko has a custom fbdev initialisation routine that aims to preserve the current mode set by the BIOS, unless overruled by the user. The user's wishes are determined by what, if any, mode is specified on the command line (via the video= parameter). However, that command line mode is first parsed by drm_fb_helper_initial_config() which is called after i915.ko's custom initial_config() as a fallback method. So in order for us to honour it, we need to export the routine out of the helper and call it first. Is this an answer to https://bugs.freedesktop.org/show_bug.cgi?id=73154? Yes. Not in this patch, but we can also use in that case as well. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Perform cmdline mode parsing during connector initialisation
,
+connector-cmdline_mode);
+ if (mode == NULL)
+ return 0;
+
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
static int drm_helper_probe_single_connector_modes_merge_bits(struct
drm_connector *connector,
uint32_t
maxX, uint32_t maxY, bool merge_type_bits)
{
@@ -134,6 +150,7 @@ static int
drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
if (count == 0 connector-status == connector_status_connected)
count = drm_add_modes_noedid(connector, 1024, 768);
+ count += drm_helper_probe_add_cmdline_mode(connector);
if (count == 0)
goto prune;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 251b75e6bf7a..abaed07a4b3b 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -532,6 +532,7 @@ struct drm_connector {
void *helper_private;
/* forced on connector */
+ struct drm_cmdline_mode cmdline_mode;
enum drm_connector_force force;
uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
struct drm_encoder *encoder; /* currently active encoder */
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index 7997246d4039..28ead2b6f59b 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -77,7 +77,6 @@ struct drm_fb_helper_funcs {
struct drm_fb_helper_connector {
struct drm_connector *connector;
- struct drm_cmdline_mode cmdline_mode;
};
struct drm_fb_helper {
--
2.0.0
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[Intel-gfx] [PATCH 01/11] drm/i915: Bring UP Power Wells before disabling RC6.
From: Deepak S deepa...@intel.com
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Reviewer: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Deepak S deepa...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 780c3ab..4fb8917 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3398,8 +3398,14 @@ static void valleyview_disable_rps(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ /* we're doing forcewake before Disabling RC6,
+* This what the BIOS expects when going into suspend */
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
I915_WRITE(GEN6_RC_CONTROL, 0);
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
gen6_disable_rps_interrupts(dev);
}
--
1.9.3
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[Intel-gfx] [PATCH 00/11] drm-intel-collector - update
This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector Here goes the update list in order for better reviewers assignment: Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer: Paulo Zanoni paulo.r.zan...@intel.com Patch drm/i915: Don't save/restore RS when not used - Reviewer: Patch drm/i915: Upgrade execbuffer fail after resume failure to EIO - Reviewer: Patch drm/i915: Add property to set HDMI aspect ratio - Reviewer: Ville Syrjälä ville.syrj...@linux.intel.com Patch drm/i915: honour forced connector modes - Reviewer: Patch drm/i915: Don't promote UC to WT automagically - Reviewer: Patch drm/i915: Refactor the physical and virtual page hws setup - Reviewer: Patch drm/i915: clean up PPGTT checking logic - Reviewer: Patch drm/i915: re-order ppgtt sanitize logic v2 - Reviewer: Patch drm/i915: Bring GPU Freq to min while suspending. - Reviewer: Patch drm/i915/bdw: Map unused PDPs to a scratch page - Reviewer: Thanks, Rodrigo. Ben Widawsky (1): drm/i915: Don't save/restore RS when not used Bob Beckett (1): drm/i915/bdw: Map unused PDPs to a scratch page Chris Wilson (3): drm/i915: Upgrade execbuffer fail after resume failure to EIO drm/i915: honour forced connector modes drm/i915: Refactor the physical and virtual page hws setup Deepak S (2): drm/i915: Bring UP Power Wells before disabling RC6. drm/i915: Bring GPU Freq to min while suspending. Jesse Barnes (2): drm/i915: clean up PPGTT checking logic drm/i915: re-order ppgtt sanitize logic v2 Vandana Kannan (1): drm/i915: Add property to set HDMI aspect ratio Ville Syrjälä (1): drm/i915: Don't promote UC to WT automagically drivers/gpu/drm/i915/i915_dma.c| 16 +--- drivers/gpu/drm/i915/i915_drv.h| 5 +- drivers/gpu/drm/i915/i915_gem.c| 11 ++- drivers/gpu/drm/i915/i915_gem_context.c| 10 ++- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++- drivers/gpu/drm/i915/i915_gem_gtt.c| 114 +++-- drivers/gpu/drm/i915/i915_gem_gtt.h| 3 +- drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_fbdev.c | 33 +++-- drivers/gpu/drm/i915/intel_hdmi.c | 12 +++ drivers/gpu/drm/i915/intel_modes.c | 28 +++ drivers/gpu/drm/i915/intel_pm.c| 6 ++ drivers/gpu/drm/i915/intel_ringbuffer.c| 81 ++-- 13 files changed, 209 insertions(+), 127 deletions(-) -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/11] drm/i915: Bring GPU Freq to min while suspending.
From: Deepak S deepa...@linux.intel.com We might be leaving the PGU Frequency (and thus vnn) high during the suspend. Flusing the delayed work queue should take care of this. Signed-off-by: Deepak S deepa...@linux.intel.com Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c3e7e8f..aafb382 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4559,7 +4559,7 @@ i915_gem_suspend(struct drm_device *dev) del_timer_sync(dev_priv-gpu_error.hangcheck_timer); cancel_delayed_work_sync(dev_priv-mm.retire_work); - cancel_delayed_work_sync(dev_priv-mm.idle_work); + flush_delayed_work(dev_priv-mm.idle_work); return 0; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/11] drm/i915: Add property to set HDMI aspect ratio
From: Vandana Kannan vandana.kan...@intel.com
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode set.
v2: Daniel's review comments incorporated.
Call for a mode set to update property.
Reviewer: Ville Syrjälä ville.syrj...@linux.intel.com
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Jesse Barnes jesse.bar...@intel.com
Cc: Vijay Purushothaman vijay.a.purushotha...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 12
drivers/gpu/drm/i915/intel_modes.c | 28
4 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 47c8ec1..804ea1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1562,6 +1562,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *aspect_ratio_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 016d894..bee9e53 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -498,6 +498,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
@@ -931,6 +932,7 @@ int intel_connector_update_modes(struct drm_connector
*connector,
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+void intel_attach_aspect_ratio_property(struct drm_connector *connector);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2422413..1851284 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode-picture_aspect_ratio = intel_hdmi-aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(frame.avi,
adjusted_mode);
if (ret 0) {
@@ -1124,6 +1127,11 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == dev_priv-aspect_ratio_property) {
+ intel_hdmi-aspect_ratio = val;
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1484,6 +1492,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_aspect_ratio_property(connector);
intel_hdmi-color_range_auto = true;
}
@@ -1551,6 +1560,9 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector-get_hw_state = intel_connector_get_hw_state;
intel_connector-unregister = intel_connector_unregister;
+ /* Initialize aspect ratio member of intel_hdmi */
+ intel_hdmi-aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
intel_hdmi_add_properties(intel_hdmi, connector);
intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index 0e860f3..6f814da 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,31 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
drm_object_attach_property(connector-base, prop, 0);
}
+
+static const struct drm_prop_enum_list aspect_ratio_names[] = {
+ { HDMI_PICTURE_ASPECT_NONE, Automatic },
+ { HDMI_PICTURE_ASPECT_4_3, 4:3 },
+ { HDMI_PICTURE_ASPECT_16_9, 16:9 },
+};
+
+void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector-dev;
+ struct drm_i915_private *dev_priv
[Intel-gfx] [PATCH 06/11] drm/i915: Don't promote UC to WT automagically
From: Ville Syrjälä ville.syrj...@linux.intel.com
If the object is already UC leave it as UC instead of automagically
promoting it to WT in i915_gem_object_pin_to_display_plane() when
the hardware is WT capable.
Supposedly the user wanted UC for a reason, so let's respect that.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5d4d73..c3e7e8f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3840,6 +3840,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
struct intel_engine_cs *pipelined)
{
u32 old_read_domains, old_write_domain;
+ unsigned int cache_level;
bool was_pin_display;
int ret;
@@ -3864,8 +3865,12 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
* of uncaching, which would allow us to flush all the LLC-cached data
* with that bit in the PTE to main memory with just one PIPE_CONTROL.
*/
- ret = i915_gem_object_set_cache_level(obj,
- HAS_WT(obj-base.dev) ?
I915_CACHE_WT : I915_CACHE_NONE);
+ if (HAS_WT(obj-base.dev) obj-cache_level != I915_CACHE_NONE)
+ cache_level = I915_CACHE_WT;
+ else
+ cache_level = I915_CACHE_NONE;
+
+ ret = i915_gem_object_set_cache_level(obj, cache_level);
if (ret)
goto err_unpin_display;
--
1.9.3
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[Intel-gfx] [PATCH 02/11] drm/i915: Don't save/restore RS when not used
From: Ben Widawsky benjamin.widaw...@intel.com
v2: fix conflict on rebase.
Cc: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index de72a28..49ae7ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -565,6 +565,7 @@ mi_set_context(struct intel_engine_cs *ring,
struct intel_context *new_context,
u32 hw_flags)
{
+ u32 flags = hw_flags | MI_MM_SPACE_GTT;
int ret;
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
@@ -578,6 +579,10 @@ mi_set_context(struct intel_engine_cs *ring,
return ret;
}
+ /* These flags are for resource streamer on HSW+ */
+ if (!IS_HASWELL(ring-dev) INTEL_INFO(ring-dev)-gen 8)
+ flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
+
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
@@ -591,10 +596,7 @@ mi_set_context(struct intel_engine_cs *ring,
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
intel_ring_emit(ring,
i915_gem_obj_ggtt_offset(new_context-legacy_hw_ctx.rcs_state) |
- MI_MM_SPACE_GTT |
- MI_SAVE_EXT_STATE_EN |
- MI_RESTORE_EXT_STATE_EN |
- hw_flags);
+ flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
--
1.9.3
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[Intel-gfx] [PATCH 03/11] drm/i915: Upgrade execbuffer fail after resume failure to EIO
From: Chris Wilson ch...@chris-wilson.co.uk
If we try to execute on a known ring, but it has failed to be
initialised correctly, report that the GPU is hung rather than the
command invalid. This leaves us reporting EINVAL only if the user
requests execution on a ring that is not supported by the device.
This should prevent UXA from getting stuck in a null render loop after a
failed resume.
v2 (Rodrigo): Fix conflict and add VCS2 ring and
s/intel_ring_buffer/intel_engine_cs.
Reported-by: Jiri Kosina ji...@jikos.cz
References: https://bugs.freedesktop.org/show_bug.cgi?id=76554
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 60998fc..288ff61 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1233,6 +1233,19 @@ eb_get_batch(struct eb_vmas *eb)
return vma-obj;
}
+static bool
+intel_ring_valid(struct intel_engine_cs *ring)
+{
+ switch (ring-id) {
+ case RCS: return true;
+ case VCS: return HAS_BSD(ring-dev);
+ case BCS: return HAS_BLT(ring-dev);
+ case VECS: return HAS_VEBOX(ring-dev);
+ case VCS2: return HAS_BSD2(ring-dev);
+ default: return false;
+ }
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file,
@@ -1289,7 +1302,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (!intel_ring_initialized(ring)) {
DRM_DEBUG(execbuf with invalid ring: %d\n,
(int)(args-flags I915_EXEC_RING_MASK));
- return -EINVAL;
+ return intel_ring_valid(ring) ? -EIO : -EINVAL;
}
if (args-buffer_count 1) {
--
1.9.3
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[Intel-gfx] [PATCH 05/11] drm/i915: honour forced connector modes
From: Chris Wilson ch...@chris-wilson.co.uk
In the move over to use BIOS connector configs, we lost the ability to
force a specific set of connectors on or off. Try to remedy that by
dropping back to the old behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).
Based on earlier patches by Jesse Barnes.
v2: Remove Jesse's patch
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 33 -
1 file changed, 12 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index f475414..5d879d18 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -331,24 +331,6 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
int num_connectors_enabled = 0;
int num_connectors_detected = 0;
- /*
-* If the user specified any force options, just bail here
-* and use that config.
-*/
- for (i = 0; i fb_helper-connector_count; i++) {
- struct drm_fb_helper_connector *fb_conn;
- struct drm_connector *connector;
-
- fb_conn = fb_helper-connector_info[i];
- connector = fb_conn-connector;
-
- if (!enabled[i])
- continue;
-
- if (connector-force != DRM_FORCE_UNSPECIFIED)
- return false;
- }
-
save_enabled = kcalloc(dev-mode_config.num_connector, sizeof(bool),
GFP_KERNEL);
if (!save_enabled)
@@ -374,8 +356,18 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
continue;
}
+ if (connector-force == DRM_FORCE_OFF) {
+ DRM_DEBUG_KMS(connector %s is disabled by user,
skipping\n,
+ connector-name);
+ enabled[i] = false;
+ continue;
+ }
+
encoder = connector-encoder;
if (!encoder || WARN_ON(!encoder-crtc)) {
+ if (connector-force DRM_FORCE_OFF)
+ goto bail;
+
DRM_DEBUG_KMS(connector %s has no encoder or crtc,
skipping\n,
connector-name);
enabled[i] = false;
@@ -394,8 +386,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
for (j = 0; j fb_helper-connector_count; j++) {
if (crtcs[j] == new_crtc) {
DRM_DEBUG_KMS(fallback: cloned
configuration\n);
- fallback = true;
- goto out;
+ goto bail;
}
}
@@ -466,8 +457,8 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
fallback = true;
}
-out:
if (fallback) {
+bail:
DRM_DEBUG_KMS(Not using firmware configuration\n);
memcpy(enabled, save_enabled, dev-mode_config.num_connector);
kfree(save_enabled);
--
1.9.3
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[Intel-gfx] [PATCH 07/11] drm/i915: Refactor the physical and virtual page hws setup
From: Chris Wilson ch...@chris-wilson.co.uk
We duplicated the legacy physical HWS setup routine for no good reason.
Combine it with the more recent virtual HWS setup for simplicity.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 16 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 81 -
2 files changed, 39 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5ae6081..44919f8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -104,17 +104,6 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev)
}
}
-static void i915_write_hws_pga(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev-dev_private;
- u32 addr;
-
- addr = dev_priv-status_page_dmah-busaddr;
- if (INTEL_INFO(dev)-gen = 4)
- addr |= (dev_priv-status_page_dmah-busaddr 28) 0xf0;
- I915_WRITE(HWS_PGA, addr);
-}
-
/**
* Frees the hardware status page, whether it's a physical address or a virtual
* address set up by the X Server.
@@ -255,10 +244,7 @@ static int i915_dma_resume(struct drm_device *dev)
}
DRM_DEBUG_DRIVER(hw status page @ %p\n,
ring-status_page.page_addr);
- if (ring-status_page.gfx_addr != 0)
- intel_ring_setup_status_page(ring);
- else
- i915_write_hws_pga(dev);
+ intel_ring_setup_status_page(ring);
DRM_DEBUG_DRIVER(Enabled hardware status page\n);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 599709e..316babf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -443,17 +443,6 @@ u64 intel_ring_get_active_head(struct intel_engine_cs
*ring)
return acthd;
}
-static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
-{
- struct drm_i915_private *dev_priv = ring-dev-dev_private;
- u32 addr;
-
- addr = dev_priv-status_page_dmah-busaddr;
- if (INTEL_INFO(ring-dev)-gen = 4)
- addr |= (dev_priv-status_page_dmah-busaddr 28) 0xf0;
- I915_WRITE(HWS_PGA, addr);
-}
-
static bool stop_ring(struct intel_engine_cs *ring)
{
struct drm_i915_private *dev_priv = to_i915(ring-dev);
@@ -511,10 +500,7 @@ static int init_ring_common(struct intel_engine_cs *ring)
}
}
- if (I915_NEED_GFX_HWS(dev))
- intel_ring_setup_status_page(ring);
- else
- ring_setup_phys_status_page(ring);
+ intel_ring_setup_status_page(ring);
/* Initialize the ring. This must happen _after_ we've cleared the ring
* registers with the above sequence (the readback of the HEAD registers
@@ -1101,39 +1087,48 @@ void intel_ring_setup_status_page(struct
intel_engine_cs *ring)
{
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = ring-dev-dev_private;
- u32 mmio = 0;
+ u32 mmio, addr;
- /* The ring status page addresses are no longer next to the rest of
-* the ring registers as of gen7.
-*/
- if (IS_GEN7(dev)) {
- switch (ring-id) {
- case RCS:
- mmio = RENDER_HWS_PGA_GEN7;
- break;
- case BCS:
- mmio = BLT_HWS_PGA_GEN7;
- break;
- /*
-* VCS2 actually doesn't exist on Gen7. Only shut up
-* gcc switch check warning
+ if (!I915_NEED_GFX_HWS(dev)) {
+ addr = dev_priv-status_page_dmah-busaddr;
+ if (INTEL_INFO(ring-dev)-gen = 4)
+ addr |= (dev_priv-status_page_dmah-busaddr 28)
0xf0;
+ mmio = HWS_PGA;
+ } else {
+ addr = ring-status_page.gfx_addr;
+ /* The ring status page addresses are no longer next to the
rest of
+* the ring registers as of gen7.
*/
- case VCS2:
- case VCS:
- mmio = BSD_HWS_PGA_GEN7;
- break;
- case VECS:
- mmio = VEBOX_HWS_PGA_GEN7;
- break;
+ if (IS_GEN7(dev)) {
+ switch (ring-id) {
+ default:
+ case RCS:
+ mmio = RENDER_HWS_PGA_GEN7;
+ break;
+ case BCS:
+ mmio = BLT_HWS_PGA_GEN7;
+ break;
+ /*
+* VCS2 actually doesn't exist on Gen7. Only
shut up
+* gcc switch
[Intel-gfx] [PATCH 08/11] drm/i915: clean up PPGTT checking logic
From: Jesse Barnes jbar...@virtuousgeek.org
sanitize_enable_ppgtt is the function that checks all the conditions,
honoring a forced ppgtt status or doing auto-detect as necessary. Just
make sure it returns the right value in all cases and use that in the
macros instead of the confusing intel_enable_ppgtt() function.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
3 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 804ea1b..428c374 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2032,8 +2032,8 @@ struct drm_i915_cmd_table {
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)-gen = 6)
#define HAS_ALIASING_PPGTT(dev)(INTEL_INFO(dev)-gen = 6)
#define HAS_PPGTT(dev) (INTEL_INFO(dev)-gen = 7 !IS_GEN8(dev))
-#define USES_PPGTT(dev)intel_enable_ppgtt(dev, false)
-#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
+#define USES_PPGTT(dev)(i915.enable_ppgtt)
+#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)-has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev)
(INTEL_INFO(dev)-overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4153ee..ea08de7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -33,17 +33,6 @@
static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
-bool intel_enable_ppgtt(struct drm_device *dev, bool full)
-{
- if (i915.enable_ppgtt == 0)
- return false;
-
- if (i915.enable_ppgtt == 1 full)
- return false;
-
- return true;
-}
-
static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
{
if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
@@ -69,6 +58,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int
enable_ppgtt)
return 0;
}
+ if (HAS_PPGTT(dev))
+ return 2;
+
return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8d6f7c1..666c938 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -272,7 +272,6 @@ void i915_gem_init_global_gtt(struct drm_device *dev);
void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
unsigned long mappable_end, unsigned long end);
-bool intel_enable_ppgtt(struct drm_device *dev, bool full);
int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
void i915_check_and_clear_faults(struct drm_device *dev);
--
1.9.3
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[Intel-gfx] [PATCH 09/11] drm/i915: re-order ppgtt sanitize logic v2
From: Jesse Barnes jbar...@virtuousgeek.org
Put hw limitations first, disabling ppgtt if necessary right away.
After that, check user passed args or auto-detect and do the right
thing, falling back to aliasing PPGTT if the user tries to enable full
PPGTT but it isn't available.
v2: simplify auto-detect case since we already caught the no PPGTT case early
on (Jesse)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ea08de7..743512e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -35,15 +35,6 @@ static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv);
static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
{
- if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
- return 0;
-
- if (enable_ppgtt == 1)
- return 1;
-
- if (enable_ppgtt == 2 HAS_PPGTT(dev))
- return 2;
-
#ifdef CONFIG_INTEL_IOMMU
/* Disable ppgtt on SNB if VT-d is on. */
if (INTEL_INFO(dev)-gen == 6 intel_iommu_gfx_mapped) {
@@ -58,10 +49,20 @@ static int sanitize_enable_ppgtt(struct drm_device *dev,
int enable_ppgtt)
return 0;
}
- if (HAS_PPGTT(dev))
- return 2;
+ if (!HAS_ALIASING_PPGTT(dev))
+ return 0;
- return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
+ /* Check user passed enable_ppgtt param and try to honor it */
+ switch (enable_ppgtt) {
+ case 0:
+ return 0;
+ case 1:
+ return 1; /* caught any hw limits above */
+ case 2:
+ /* fall through to auto-detect */
+ default: /* auto-detect */
+ return HAS_PPGTT(dev) ? 2 : 1;
+ }
}
--
1.9.3
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com So don't write it, otherwise we will trigger unclaimed register errors. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c12a5da..14505a1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7345,8 +7345,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) WARN(I915_READ(PCH_PP_STATUS) PP_ON, Panel power on\n); WARN(I915_READ(BLC_PWM_CPU_CTL2) BLM_PWM_ENABLE, CPU PWM1 enabled\n); - WARN(I915_READ(HSW_BLC_PWM2_CTL) BLM_PWM_ENABLE, -CPU PWM2 enabled\n); + if (IS_HASWELL(dev)) + WARN(I915_READ(HSW_BLC_PWM2_CTL) BLM_PWM_ENABLE, +CPU PWM2 enabled\n); WARN(I915_READ(BLC_PWM_PCH_CTL1) BLM_PCH_PWM_ENABLE, PCH PWM1 enabled\n); WARN(I915_READ(UTIL_PIN_CTL) UTIL_PIN_ENABLE, -- 2.0.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com On Thu, Jul 10, 2014 at 12:31 PM, Paulo Zanoni przan...@gmail.com wrote: 2014-07-08 11:58 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Tue, Jul 08, 2014 at 11:15:03AM -0300, Paulo Zanoni wrote: 2014-07-07 18:23 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com If we enable unclaimed register reporting on Gen 8, we will discover that the IRQ registers for pipes B and C are also on the power well, so writes to them when the power well is disabled result in unclaimed register errors. Also, hsw_power_well_post_enable() already takes care of re-enabling them once the power well is enabled. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com Hm, shouldn't we split this into only setting up pipe A here and the pipe B stuff once we fire up the power well? No because these functions might be called when the power wells are already enabled. Hm, where does this still happen? bdw has power well support and chv has a different display block ... At driver init time... If you load i915.ko and the power wells are already enabled, we have to do it here. This code changed too often and I have no idea any more what's up and what's down here ;-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 12
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++
3 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 2e116e9d..a8b8b6b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3204,6 +3204,18 @@ static void gen8_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev);
}
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(dev_priv-irq_lock, irqflags);
+ GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv-de_irq_mask[PIPE_B],
+ ~dev_priv-de_irq_mask[PIPE_B]);
+ GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv-de_irq_mask[PIPE_C],
+ ~dev_priv-de_irq_mask[PIPE_C]);
+ spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
+}
+
static void cherryview_irq_preinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 5f7c7bd..46a3a09 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -687,6 +687,7 @@ void intel_runtime_pm_disable_interrupts(struct
drm_device *dev);
void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void i9xx_check_fifo_underruns(struct drm_device *dev);
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
/* intel_crt.c */
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..4cc9e5c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5913,7 +5913,6 @@ bool intel_display_power_enabled(struct
drm_i915_private *dev_priv,
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
- unsigned long irqflags;
/*
* After we re-enable the power well, if we touch VGA register
0x3d5
@@ -5929,21 +5928,8 @@ static void hsw_power_well_post_enable(struct
drm_i915_private *dev_priv)
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(dev-pdev, VGA_RSRC_LEGACY_IO);
- if (IS_BROADWELL(dev)) {
- spin_lock_irqsave(dev_priv-irq_lock, irqflags);
- I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
- dev_priv-de_irq_mask[PIPE_B]);
- I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
- ~dev_priv-de_irq_mask[PIPE_B] |
- GEN8_PIPE_VBLANK);
- I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
- dev_priv-de_irq_mask[PIPE_C]);
- I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
- ~dev_priv-de_irq_mask[PIPE_C] |
- GEN8_PIPE_VBLANK);
- POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
- spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
- }
+ if (IS_BROADWELL(dev))
+ gen8_irq_power_well_post_enable(dev_priv);
}
static void hsw_set_power_well(struct drm_i915_private *dev_priv,
--
2.0.0
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: reorganize the unclaimed register detection code
, reg, true, false); \
REG_READ_FOOTER; \
}
@@ -700,12 +753,13 @@ hsw_write##x(struct drm_i915_private *dev_priv,
off_t reg, u##x val, bool trace)
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
- hsw_unclaimed_reg_clear(dev_priv, reg); \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
__raw_i915_write##x(dev_priv, reg, val); \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
- hsw_unclaimed_reg_check(dev_priv, reg); \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
+ hsw_unclaimed_reg_detect(dev_priv); \
REG_WRITE_FOOTER; \
}
--
2.0.0
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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The rest looks good. With that fixed and probably with comment removed as
Daniel mentioned, feel free to use:
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
--
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: BDW can also detect unclaimed registers
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
By the time I wrote this patch, it allowed me to catch some problems.
But due to patch reordering - in order to prevent fake regression
reports - this patch may be merged after the fixes of the problems
identified by this patch.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/intel_uncore.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 8a0cb0c..bdb223c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -303,6 +303,7 @@ static const struct intel_device_info
intel_broadwell_d_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -314,6 +315,7 @@ static const struct intel_device_info
intel_broadwell_m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -325,6 +327,7 @@ static const struct intel_device_info
intel_broadwell_gt3d_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
@@ -336,6 +339,7 @@ static const struct intel_device_info
intel_broadwell_gt3m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
BSD2_RING,
.has_llc = 1,
.has_ddi = 1,
+ .has_fpga_dbg = 1,
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index de5402f..1fcf78b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -788,6 +788,7 @@ static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv, u32 reg)
static void \
gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val,
bool trace) { \
REG_WRITE_HEADER; \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
if (reg 0x4 !is_gen8_shadowed(dev_priv, reg)) { \
if (dev_priv-uncore.forcewake_count == 0) \
dev_priv-uncore.funcs.force_wake_get(dev_priv, \
@@ -799,6 +800,8 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
} else { \
__raw_i915_write##x(dev_priv, reg, val); \
} \
+ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
+ hsw_unclaimed_reg_detect(dev_priv); \
REG_WRITE_FOOTER; \
}
--
2.0.0
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[Intel-gfx] [PATCH] drm/i915: Fix semaphore_seqno and semaphore_mboxes sizes
Otherwise some iteractions depending on the current number of active rings
could overflow.
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b8308d..190f0e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -342,7 +342,7 @@ struct drm_i915_error_state {
u32 cpu_ring_head;
u32 cpu_ring_tail;
- u32 semaphore_seqno[I915_NUM_RINGS - 1];
+ u32 semaphore_seqno[I915_NUM_RINGS];
/* Register state */
u32 tail;
@@ -361,7 +361,7 @@ struct drm_i915_error_state {
u32 fault_reg;
u64 faddr;
u32 rc_psmi; /* sleep state */
- u32 semaphore_mboxes[I915_NUM_RINGS - 1];
+ u32 semaphore_mboxes[I915_NUM_RINGS];
struct drm_i915_error_object {
int page_count;
--
1.9.3
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Re: [Intel-gfx] [PATCH] drm/i915: Fix semaphore_seqno and semaphore_mboxes sizes
just ignore this one..
On Thu, Jul 17, 2014 at 5:00 AM, Rodrigo Vivi rodrigo.v...@intel.com
wrote:
Otherwise some iteractions depending on the current number of active rings
could overflow.
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 2b8308d..190f0e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -342,7 +342,7 @@ struct drm_i915_error_state {
u32 cpu_ring_head;
u32 cpu_ring_tail;
- u32 semaphore_seqno[I915_NUM_RINGS - 1];
+ u32 semaphore_seqno[I915_NUM_RINGS];
/* Register state */
u32 tail;
@@ -361,7 +361,7 @@ struct drm_i915_error_state {
u32 fault_reg;
u64 faddr;
u32 rc_psmi; /* sleep state */
- u32 semaphore_mboxes[I915_NUM_RINGS - 1];
+ u32 semaphore_mboxes[I915_NUM_RINGS];
struct drm_i915_error_object {
int page_count;
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9faebbc..36a7960 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -764,7 +764,7 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
{
- struct intel_engine_cs *useless;
+ struct intel_engine_cs *to;
int i;
if (!i915_semaphore_is_enabled(dev_priv-dev))
@@ -776,13 +776,14 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
dev_priv-semaphore_obj,
dev_priv-gtt.base);
- for_each_ring(useless, dev_priv, i) {
+ for_each_ring(to, dev_priv, i) {
u16 signal_offset =
(GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
u32 *tmp = error-semaphore_obj-pages[0];
+ int idx = intel_ring_sync_index(ring, to);
- ering-semaphore_mboxes[i] = tmp[signal_offset];
- ering-semaphore_seqno[i] = ring-semaphore.sync_seqno[i];
+ ering-semaphore_mboxes[idx] = tmp[signal_offset];
+ ering-semaphore_seqno[idx] = ring-semaphore.sync_seqno[idx];
}
}
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: print full error ring semaphore mboxes and sync.
With the increasing number of rings,
we probably have more information to print than we were printing.
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 36a7960..0beeebf 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -242,6 +242,8 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
struct drm_device *dev,
struct drm_i915_error_ring *ring)
{
+ int i;
+
if (!ring-valid)
return;
@@ -264,23 +266,15 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
if (INTEL_INFO(dev)-gen = 6) {
err_printf(m, RC PSMI: 0x%08x\n, ring-rc_psmi);
err_printf(m, FAULT_REG: 0x%08x\n, ring-fault_reg);
- err_printf(m, SYNC_0: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[0],
- ring-semaphore_seqno[0]);
- err_printf(m, SYNC_1: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[1],
- ring-semaphore_seqno[1]);
- if (HAS_VEBOX(dev)) {
- err_printf(m, SYNC_2: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[2],
- ring-semaphore_seqno[2]);
+ for (i = 0; i I915_NUM_RINGS - 1; i++) {
+ err_printf(m, SYNC_%d: 0x%08x [last synced
0x%08x]\n,
+ i, ring-semaphore_mboxes[i],
+ ring-semaphore_seqno[i]);
}
}
if (USES_PPGTT(dev)) {
err_printf(m, GFX_MODE: 0x%08x\n, ring-vm_info.gfx_mode);
-
if (INTEL_INFO(dev)-gen = 8) {
- int i;
for (i = 0; i 4; i++)
err_printf(m, PDP%d: 0x%016llx\n,
i, ring-vm_info.pdp[i]);
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: print full error ring semaphore mboxes and sync.
With the increasing number of rings,
we probably have more information to print than we were printing.
v2: Loop only over active rings and print info with ring names.
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 36a7960..b1848e0 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -242,6 +242,10 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
struct drm_device *dev,
struct drm_i915_error_ring *ring)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *from, *to;
+ int i, j;
+
if (!ring-valid)
return;
@@ -264,23 +268,19 @@ static void i915_ring_error_state(struct
drm_i915_error_state_buf *m,
if (INTEL_INFO(dev)-gen = 6) {
err_printf(m, RC PSMI: 0x%08x\n, ring-rc_psmi);
err_printf(m, FAULT_REG: 0x%08x\n, ring-fault_reg);
- err_printf(m, SYNC_0: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[0],
- ring-semaphore_seqno[0]);
- err_printf(m, SYNC_1: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[1],
- ring-semaphore_seqno[1]);
- if (HAS_VEBOX(dev)) {
- err_printf(m, SYNC_2: 0x%08x [last synced 0x%08x]\n,
- ring-semaphore_mboxes[2],
- ring-semaphore_seqno[2]);
+ for_each_ring(from, dev_priv, i) {
+ for_each_ring(to, dev_priv, j) {
+ int idx = intel_ring_sync_index(from, to);
+ err_printf(m, SYNC[%s - %s]: 0x%08x [last
synced 0x%08x]\n,
+ from-name, to-name,
+ ring-semaphore_mboxes[idx],
+ ring-semaphore_seqno[idx]);
+ }
}
}
if (USES_PPGTT(dev)) {
err_printf(m, GFX_MODE: 0x%08x\n, ring-vm_info.gfx_mode);
-
if (INTEL_INFO(dev)-gen = 8) {
- int i;
for (i = 0; i 4; i++)
err_printf(m, PDP%d: 0x%016llx\n,
i, ring-vm_info.pdp[i]);
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9faebbc..6608bee 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -764,7 +764,7 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
{
- struct intel_engine_cs *useless;
+ struct intel_engine_cs *to;
int i;
if (!i915_semaphore_is_enabled(dev_priv-dev))
@@ -776,13 +776,17 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
dev_priv-semaphore_obj,
dev_priv-gtt.base);
- for_each_ring(useless, dev_priv, i) {
+ for_each_ring(to, dev_priv, i) {
u16 signal_offset =
(GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
u32 *tmp = error-semaphore_obj-pages[0];
+ int idx = intel_ring_sync_index(ring, to);
- ering-semaphore_mboxes[i] = tmp[signal_offset];
- ering-semaphore_seqno[i] = ring-semaphore.sync_seqno[i];
+ if (ring-id == to-id)
+ return;
+
+ ering-semaphore_mboxes[idx] = tmp[signal_offset];
+ ering-semaphore_seqno[idx] = ring-semaphore.sync_seqno[idx];
}
}
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring-id == to-id (Damien).
use continue instead of return (Rodrigo).
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9faebbc..1efcf1f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -764,8 +764,8 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
{
- struct intel_engine_cs *useless;
- int i;
+ struct intel_engine_cs *to;
+ int i, idx;
if (!i915_semaphore_is_enabled(dev_priv-dev))
return;
@@ -776,13 +776,18 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
dev_priv-semaphore_obj,
dev_priv-gtt.base);
- for_each_ring(useless, dev_priv, i) {
+ for_each_ring(to, dev_priv, i) {
u16 signal_offset =
(GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
u32 *tmp = error-semaphore_obj-pages[0];
- ering-semaphore_mboxes[i] = tmp[signal_offset];
- ering-semaphore_seqno[i] = ring-semaphore.sync_seqno[i];
+ if (ring == to)
+ continue;
+
+ idx = intel_ring_sync_index(ring, to);
+
+ ering-semaphore_mboxes[idx] = tmp[signal_offset];
+ ering-semaphore_seqno[idx] = ring-semaphore.sync_seqno[idx];
}
}
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs - 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs - 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 - 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring-id == to-id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9faebbc..0b3f694 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -764,7 +764,7 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *ring,
struct drm_i915_error_ring *ering)
{
- struct intel_engine_cs *useless;
+ struct intel_engine_cs *to;
int i;
if (!i915_semaphore_is_enabled(dev_priv-dev))
@@ -776,13 +776,20 @@ static void gen8_record_semaphore_state(struct
drm_i915_private *dev_priv,
dev_priv-semaphore_obj,
dev_priv-gtt.base);
- for_each_ring(useless, dev_priv, i) {
- u16 signal_offset =
- (GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
- u32 *tmp = error-semaphore_obj-pages[0];
+ for_each_ring(to, dev_priv, i) {
+ int idx;
+ u16 signal_offset;
+ u32 *tmp;
- ering-semaphore_mboxes[i] = tmp[signal_offset];
- ering-semaphore_seqno[i] = ring-semaphore.sync_seqno[i];
+ if (ring == to)
+ continue;
+
+ signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
+ tmp = error-semaphore_obj-pages[0];
+ idx = intel_ring_sync_index(ring, to);
+
+ ering-semaphore_mboxes[idx] = tmp[signal_offset];
+ ering-semaphore_seqno[idx] = ring-semaphore.sync_seqno[idx];
}
}
--
1.9.3
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[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 16 ++--
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef38c3b..ccb97f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -314,6 +314,7 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
+ u32 gtier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0b3f694..372fea3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -359,6 +359,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (IS_HASWELL(dev))
+ err_printf(m, GTIER: 0x%08x\n, error-gtier);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1135,13 +1137,15 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev))
+ if (IS_HASWELL(dev)) {
+ error-ier = I915_READ(DEIER);
+ error-gtier = I915_READ(GTIER);
+ } else if (HAS_PCH_SPLIT(dev)) {
error-ier = I915_READ(DEIER) | I915_READ(GTIER);
- else {
- if (IS_GEN2(dev))
- error-ier = I915_READ16(IER);
- else
- error-ier = I915_READ(IER);
+ } else if (IS_GEN2(dev)) {
+ error-ier = I915_READ16(IER);
+ } else {
+ error-ier = I915_READ(IER);
}
/* 4: Everything else */
--
1.9.3
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.
On Wed, Jul 30, 2014 at 10:53 AM, Paulo Zanoni przan...@gmail.com wrote:
2014-07-28 12:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 16 ++--
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index ef38c3b..ccb97f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -314,6 +314,7 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
+ u32 gtier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0b3f694..372fea3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -359,6 +359,8 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (IS_HASWELL(dev))
+ err_printf(m, GTIER: 0x%08x\n, error-gtier);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1135,13 +1137,15 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev))
+ if (IS_HASWELL(dev)) {
+ error-ier = I915_READ(DEIER);
+ error-gtier = I915_READ(GTIER);
+ } else if (HAS_PCH_SPLIT(dev)) {
error-ier = I915_READ(DEIER) | I915_READ(GTIER);
You did a change for HSW only, but we have these bits since Gen5. Why
don't you do this change for the whole HAS_PCH_SPLIT chunk instead of
adding a HSW-specific piece?
I am not a huge user of these error state files, I can't really think
why we would want to or the IER bits, so your patch looks correct to
me.
I believe before HSW they had the same interface both DEIR and GTIER, but
since I'm splitting it for HSW you are right we can split everywhere else
with or without common interface.
- else {
- if (IS_GEN2(dev))
- error-ier = I915_READ16(IER);
- else
- error-ier = I915_READ(IER);
+ } else if (IS_GEN2(dev)) {
+ error-ier = I915_READ16(IER);
+ } else {
+ error-ier = I915_READ(IER);
While reviewing your patch I also noticed that at the top of this
function we set error-ier for VLV, but then at this point we just
overwrite what was previously set. You could write another patch to
fix VLV too :)
Yeah, it is messy... I'll also split for VLV and organize a bit to avoid
overwriting...
}
/* 4: Everything else */
--
1.9.3
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--
Paulo Zanoni
___
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.
On Wed, Jul 30, 2014 at 11:09 AM, Paulo Zanoni przan...@gmail.com wrote:
2014-07-28 12:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also
listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
https://bugs.freedesktop.org/show_bug.cgi?id=81701
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gpu_error.c | 23 ---
3 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..679cda6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -783,7 +783,7 @@ static int i915_interrupt_info(struct seq_file *m,
void *data)
seq_printf(m, Pipe %c stat: %08x\n,
pipe_name(pipe),
I915_READ(PIPESTAT(pipe)));
- } else {
+ } else if (!IS_BROADWELL(dev)) {
seq_printf(m, North Display Interrupt enable:
%08x\n,
I915_READ(DEIER));
seq_printf(m, North Display Interrupt identity:
%08x\n,
This chunk is not needed since we already have a check for gen = 8
at the top.
oh, for a moment I thought it was messy as the other code and it was
writing twice...
mainly when you mentioned that you could reproduce the unclaimed when
reading debugfs...
but probably was related to the powerwell you mentioned below...
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index ccb97f1..ee28cd7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -314,7 +314,9 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
- u32 gtier;
+ u32 gtier[4];
+ u32 deier[3];
+ u32 de_misc_ier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 372fea3..f865d1d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -358,9 +358,19 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, Suspend count: %u\n, error-suspend_count);
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
- err_printf(m, IER: 0x%08x\n, error-ier);
+ if (IS_BROADWELL(dev)) {
+ for_each_pipe(i)
+ err_printf(m, DEIER pipe %c: 0x%08x\n,
pipe_name(i),
+ error-deier[i]);
+ for (i = 0; i 4; i++)
+ err_printf(m, GTIER gt %d: 0x%08x\n, i,
+ error-gtier[i]);
+ err_printf(m, DE_MISC_IER: 0x%08x\n,
error-de_misc_ier);
+ } else {
+ err_printf(m, IER: 0x%08x\n, error-ier);
+ }
if (IS_HASWELL(dev))
- err_printf(m, GTIER: 0x%08x\n, error-gtier);
+ err_printf(m, GTIER: 0x%08x\n, error-gtier[0]);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1093,6 +1103,7 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
struct drm_device *dev = dev_priv-dev;
+ int i;
/* General organization
* 1. Registers specific to a single generation
@@ -1139,7 +1150,13 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (IS_HASWELL(dev)) {
error-ier = I915_READ(DEIER);
- error-gtier = I915_READ(GTIER);
+ error-gtier[0] = I915_READ(GTIER);
+ } else if (IS_BROADWELL(dev)) {
+ for_each_pipe(i)
+ error-deier[i] = I915_READ(GEN8_DE_PIPE_IER(i));
for_each_pipe(i)
if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_PIPE(i)))
error-deier[i] = I915_READ(GEN8_DE_PIPE_IER(i));
If the pipe's power well is disabled, the IER register is powered off
and we can get an unclaimed register errors too.
thanks! I'll add it...
Also also need to be added to debugfs interface.
I also just noticed that this function contains the /* 4: Everything
else */ comment twice
[Intel-gfx] [PATCH 1/2] drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.
v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
MBZ before IVB.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
4 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..bcfdc00 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_fbc_fc_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (INTEL_INFO(dev)-gen 7)
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+ *val = dev_priv-fbc.false_color;
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+static int i915_fbc_fc_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg;
+
+ if (INTEL_INFO(dev)-gen 7)
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+
+ reg = I915_READ(ILK_DPFC_CONTROL);
+ dev_priv-fbc.false_color = val;
+
+ I915_WRITE(ILK_DPFC_CONTROL, val ?
+ (reg | FBC_CTL_FALSE_COLOR) :
+ (reg ~FBC_CTL_FALSE_COLOR));
+
+ drm_modeset_unlock_all(dev);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
+ i915_fbc_fc_get, i915_fbc_fc_set,
+ %llu\n);
+
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m-private;
@@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files {
{i915_pri_wm_latency, i915_pri_wm_latency_fops},
{i915_spr_wm_latency, i915_spr_wm_latency_fops},
{i915_cur_wm_latency, i915_cur_wm_latency_fops},
+ {i915_fbc_false_color, i915_fbc_fc_fops},
};
void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18c9ad8..3018bf5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,6 +636,8 @@ struct i915_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
+ bool false_color;
+
struct intel_fbc_work {
struct delayed_work work;
struct drm_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28e21ed..b5d295a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1540,6 +1540,7 @@ enum punit_power_well {
/* Framebuffer compression for Ironlake */
#define ILK_DPFC_CB_BASE 0x43200
#define ILK_DPFC_CONTROL 0x43208
+#define FBC_CTL_FALSE_COLOR (110)
/* The bit 28-8 is reserved */
#define DPFC_RESERVED(0x1F00)
#define ILK_DPFC_RECOMP_CTL0x4320c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ddd4df..338a80b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
+ if (dev_priv-fbc.false_color)
+ dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
if (IS_IVYBRIDGE(dev)) {
--
1.9.3
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: FBC flush nuke for BDW
According to spec FBC on BDW and HSW are identical without any gaps. So let's copy the nuke and let FBC really start compressing stuff. Without this patch we can verify with false color that nothing is being compressed. With the nuke in place and false color it is possible to see false color debugs. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b3d8f76..3e06a1b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -416,6 +416,9 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, intel_ring_emit(ring, 0); intel_ring_advance(ring); + if (!invalidate_domains flush_domains) + return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); + return 0; } @@ -2058,7 +2061,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring, } intel_ring_advance(ring); - if (IS_GEN7(dev) !invalidate flush) + if (INTEL_INFO(dev)-gen = 7 !invalidate flush) return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); return 0; -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Skip Stolen Memory first page.
WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 21c025a..3acefb3 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -290,6 +290,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int bios_reserved = 0;
+ int initial_reserved = 0;
#ifdef CONFIG_INTEL_IOMMU
if (intel_iommu_gfx_mapped INTEL_INFO(dev)-gen 8) {
@@ -314,9 +315,13 @@ int i915_gem_init_stolen(struct drm_device *dev)
if (WARN_ON(bios_reserved dev_priv-gtt.stolen_size))
return 0;
+ /* WaSkipStolenMemoryFirstPage */
+ if (INTEL_INFO(dev)-gen = 8)
+ initial_reserved = 4096;
+
/* Basic memrange allocator for stolen space */
- drm_mm_init(dev_priv-mm.stolen, 0, dev_priv-gtt.stolen_size -
- bios_reserved);
+ drm_mm_init(dev_priv-mm.stolen, initial_reserved,
+ dev_priv-gtt.stolen_size - bios_reserved);
return 0;
}
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.
v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
4 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..2147b41 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_fbc_fc_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (INTEL_INFO(dev)-gen 7 || !HAS_PCH_SPLIT(dev))
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+ *val = dev_priv-fbc.false_color;
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+static int i915_fbc_fc_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg;
+
+ if (INTEL_INFO(dev)-gen 7 || !HAS_PCH_SPLIT(dev))
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+
+ reg = I915_READ(ILK_DPFC_CONTROL);
+ dev_priv-fbc.false_color = val;
+
+ I915_WRITE(ILK_DPFC_CONTROL, val ?
+ (reg | FBC_CTL_FALSE_COLOR) :
+ (reg ~FBC_CTL_FALSE_COLOR));
+
+ drm_modeset_unlock_all(dev);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
+ i915_fbc_fc_get, i915_fbc_fc_set,
+ %llu\n);
+
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m-private;
@@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files {
{i915_pri_wm_latency, i915_pri_wm_latency_fops},
{i915_spr_wm_latency, i915_spr_wm_latency_fops},
{i915_cur_wm_latency, i915_cur_wm_latency_fops},
+ {i915_fbc_false_color, i915_fbc_fc_fops},
};
void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d604f4f..3a29f9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,6 +636,8 @@ struct i915_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
+ bool false_color;
+
struct intel_fbc_work {
struct delayed_work work;
struct drm_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28e21ed..b5d295a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1540,6 +1540,7 @@ enum punit_power_well {
/* Framebuffer compression for Ironlake */
#define ILK_DPFC_CB_BASE 0x43200
#define ILK_DPFC_CONTROL 0x43208
+#define FBC_CTL_FALSE_COLOR (110)
/* The bit 28-8 is reserved */
#define DPFC_RESERVED(0x1F00)
#define ILK_DPFC_RECOMP_CTL0x4320c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ddd4df..338a80b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
+ if (dev_priv-fbc.false_color)
+ dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
if (IS_IVYBRIDGE(dev)) {
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Skip Stolen Memory first page.
WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle
v2: Improve variable names and fix allocated size.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 21c025a..82035b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -289,7 +289,8 @@ void i915_gem_cleanup_stolen(struct drm_device *dev)
int i915_gem_init_stolen(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- int bios_reserved = 0;
+ int start_rsvd = 0;
+ int end_rsvd = 0;
#ifdef CONFIG_INTEL_IOMMU
if (intel_iommu_gfx_mapped INTEL_INFO(dev)-gen 8) {
@@ -308,15 +309,19 @@ int i915_gem_init_stolen(struct drm_device *dev)
DRM_DEBUG_KMS(found %zd bytes of stolen memory at %08lx\n,
dev_priv-gtt.stolen_size, dev_priv-mm.stolen_base);
+ /* WaSkipStolenMemoryFirstPage */
+ if (INTEL_INFO(dev)-gen = 8)
+ start_rsvd = 4096;
+
if (IS_VALLEYVIEW(dev))
- bios_reserved = 1024*1024; /* top 1M on VLV/BYT */
+ end_rsvd = 1024*1024; /* top 1M on VLV/BYT */
- if (WARN_ON(bios_reserved dev_priv-gtt.stolen_size))
+ if (WARN_ON((start_rsvd + end_rsvd) dev_priv-gtt.stolen_size))
return 0;
/* Basic memrange allocator for stolen space */
- drm_mm_init(dev_priv-mm.stolen, 0, dev_priv-gtt.stolen_size -
- bios_reserved);
+ drm_mm_init(dev_priv-mm.stolen, start_rsvd,
+ dev_priv-gtt.stolen_size - start_rsvd - end_rsvd);
return 0;
}
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: FBC flush nuke for BDW
According to spec FBC on BDW and HSW are identical without any gaps.
So let's copy the nuke and let FBC really start compressing stuff.
Without this patch we can verify with false color that nothing is being
compressed. With the nuke in place and false color it is possible
to see false color debugs.
v2: Fix rebase conflict.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2908896..4ba3db1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -406,6 +406,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
{
u32 flags = 0;
u32 scratch_addr = ring-scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ int ret;
flags |= PIPE_CONTROL_CS_STALL;
@@ -424,7 +425,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
}
- return gen8_emit_pipe_control(ring, flags, scratch_addr);
+ ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
+ if (ret)
+ return ret;
+
+ if (!invalidate_domains flush_domains)
+ return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
+
+ return 0;
}
static void ring_write_tail(struct intel_engine_cs *ring,
@@ -2065,7 +2073,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
}
intel_ring_advance(ring);
- if (IS_GEN7(dev) !invalidate flush)
+ if (INTEL_INFO(dev)-gen = 7 !invalidate flush)
return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
return 0;
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.
v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
4 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..aea1a81 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_fbc_fc_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (INTEL_INFO(dev)-gen 7 || !HAS_FBC(dev))
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+ *val = dev_priv-fbc.false_color;
+ drm_modeset_unlock_all(dev);
+
+ return 0;
+}
+
+static int i915_fbc_fc_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg;
+
+ if (INTEL_INFO(dev)-gen 7 || !HAS_FBC(dev))
+ return -ENODEV;
+
+ drm_modeset_lock_all(dev);
+
+ reg = I915_READ(ILK_DPFC_CONTROL);
+ dev_priv-fbc.false_color = val;
+
+ I915_WRITE(ILK_DPFC_CONTROL, val ?
+ (reg | FBC_CTL_FALSE_COLOR) :
+ (reg ~FBC_CTL_FALSE_COLOR));
+
+ drm_modeset_unlock_all(dev);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
+ i915_fbc_fc_get, i915_fbc_fc_set,
+ %llu\n);
+
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m-private;
@@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files {
{i915_pri_wm_latency, i915_pri_wm_latency_fops},
{i915_spr_wm_latency, i915_spr_wm_latency_fops},
{i915_cur_wm_latency, i915_cur_wm_latency_fops},
+ {i915_fbc_false_color, i915_fbc_fc_fops},
};
void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d604f4f..3a29f9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,6 +636,8 @@ struct i915_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
+ bool false_color;
+
struct intel_fbc_work {
struct delayed_work work;
struct drm_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28e21ed..b5d295a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1540,6 +1540,7 @@ enum punit_power_well {
/* Framebuffer compression for Ironlake */
#define ILK_DPFC_CB_BASE 0x43200
#define ILK_DPFC_CONTROL 0x43208
+#define FBC_CTL_FALSE_COLOR (110)
/* The bit 28-8 is reserved */
#define DPFC_RESERVED(0x1F00)
#define ILK_DPFC_RECOMP_CTL0x4320c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ddd4df..338a80b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
+ if (dev_priv-fbc.false_color)
+ dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
if (IS_IVYBRIDGE(dev)) {
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
v2: since we have gtier variable already let's split for everybody
and avoid the strange | op.
Also avoid overriding the value that was set for vlv. In this case I
believe that we should reorganize the whole function, but I'll respect
the comment that ask to not touch the order and let this organization
work to be done later.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 24 ++--
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d604f4f..60227b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,6 +317,7 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
+ u32 gtier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0b3f694..76c67dd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -359,6 +359,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+ err_printf(m, GTIER: 0x%08x\n, error-gtier);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1102,7 +1104,8 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
/* 1: Registers specific to a single generation */
if (IS_VALLEYVIEW(dev)) {
- error-ier = I915_READ(GTIER) | I915_READ(VLV_IER);
+ error-gtier = I915_READ(GTIER);
+ error-ier = I915_READ(VLV_IER);
error-forcewake = I915_READ(FORCEWAKE_VLV);
}
@@ -1135,17 +1138,18 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev))
- error-ier = I915_READ(DEIER) | I915_READ(GTIER);
- else {
- if (IS_GEN2(dev))
- error-ier = I915_READ16(IER);
- else
- error-ier = I915_READ(IER);
+ if (HAS_PCH_SPLIT(dev)) {
+ error-ier = I915_READ(DEIER);
+ error-gtier = I915_READ(GTIER);
+ } else if (IS_GEN2(dev)) {
+ error-ier = I915_READ16(IER);
+ } else {
+ error-ier = I915_READ(IER);
}
- /* 4: Everything else */
- error-eir = I915_READ(EIR);
+ /* do not override what was set above for VLV */
+ if (!IS_VALLEYVIEW(dev))
+ error-eir = I915_READ(EIR);
error-pgtbl_er = I915_READ(PGTBL_ER);
i915_get_extra_instdone(dev, error-extra_instdone);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
https://bugs.freedesktop.org/show_bug.cgi?id=81701
v2: Fix small issues of first version and don't read DEIER regs when pipe's
power well is disabled
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gpu_error.c | 29 +
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..b3493d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -703,6 +703,10 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
}
for_each_pipe(pipe) {
+ if (!intel_display_power_enabled(dev_priv,
+
POWER_DOMAIN_PIPE(pipe)))
+ continue;
+
seq_printf(m, Pipe %c IMR:\t%08x\n,
pipe_name(pipe),
I915_READ(GEN8_DE_PIPE_IMR(pipe)));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60227b2..d1ae952 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,7 +317,9 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
- u32 gtier;
+ u32 gtier[4];
+ u32 deier[3];
+ u32 de_misc_ier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 76c67dd..088b535 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -359,8 +359,19 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (IS_BROADWELL(dev)) {
+ for_each_pipe(i)
+ err_printf(m, DEIER pipe %c: 0x%08x\n, pipe_name(i),
+ error-deier[i]);
+ for (i = 0; i 4; i++)
+ err_printf(m, GTIER gt %d: 0x%08x\n, i,
+ error-gtier[i]);
+ err_printf(m, DE_MISC_IER: 0x%08x\n, error-de_misc_ier);
+ } else {
+ err_printf(m, IER: 0x%08x\n, error-ier);
+ }
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
- err_printf(m, GTIER: 0x%08x\n, error-gtier);
+ err_printf(m, GTIER: 0x%08x\n, error-gtier[0]);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1093,6 +1104,7 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
struct drm_device *dev = dev_priv-dev;
+ int i;
/* General organization
* 1. Registers specific to a single generation
@@ -1104,7 +1116,7 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
/* 1: Registers specific to a single generation */
if (IS_VALLEYVIEW(dev)) {
- error-gtier = I915_READ(GTIER);
+ error-gtier[0] = I915_READ(GTIER);
error-ier = I915_READ(VLV_IER);
error-forcewake = I915_READ(FORCEWAKE_VLV);
}
@@ -1138,9 +1150,18 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_BROADWELL(dev)) {
+ for_each_pipe(i)
+ if (intel_display_power_enabled(dev_priv,
+ POWER_DOMAIN_PIPE(i)))
+ error-deier[i] =
+ I915_READ(GEN8_DE_PIPE_IER(i));
+ for (i = 0; i 4; i++)
+ error-gtier[i] = I915_READ(GEN8_GT_IER(i));
+ error-de_misc_ier = I915_READ(GEN8_DE_MISC_IER);
+ } else if (HAS_PCH_SPLIT(dev)) {
error-ier = I915_READ(DEIER);
- error-gtier = I915_READ(GTIER);
+ error-gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
error-ier = I915_READ16(IER);
} else {
--
1.9.1
[Intel-gfx] [PATCH] drm/i915: Fix error state collecting
Fix signal_offset when recording semaphore state on BDW. Reviewed-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 0b3f694..0ea6a6b 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -784,7 +784,8 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, if (ring == to) continue; - signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4; + signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) (PAGE_SIZE - 1)) + / 4; tmp = error-semaphore_obj-pages[0]; idx = intel_ring_sync_index(ring, to); -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Collect gtier properly on HSW.
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
v2: since we have gtier variable already let's split for everybody
and avoid the strange | op.
Also avoid overriding the value that was set for vlv. In this case I
believe that we should reorganize the whole function, but I'll respect
the comment that ask to not touch the order and let this organization
work to be done later.
v3: moving VLV check to the right place.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++--
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d604f4f..60227b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,6 +317,7 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
+ u32 gtier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0b3f694..c8f901f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -359,6 +359,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+ err_printf(m, GTIER: 0x%08x\n, error-gtier);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1102,7 +1104,8 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
/* 1: Registers specific to a single generation */
if (IS_VALLEYVIEW(dev)) {
- error-ier = I915_READ(GTIER) | I915_READ(VLV_IER);
+ error-gtier = I915_READ(GTIER);
+ error-ier = I915_READ(VLV_IER);
error-forcewake = I915_READ(FORCEWAKE_VLV);
}
@@ -1135,16 +1138,14 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev))
- error-ier = I915_READ(DEIER) | I915_READ(GTIER);
- else {
- if (IS_GEN2(dev))
- error-ier = I915_READ16(IER);
- else
- error-ier = I915_READ(IER);
+ if (HAS_PCH_SPLIT(dev)) {
+ error-ier = I915_READ(DEIER);
+ error-gtier = I915_READ(GTIER);
+ } else if (IS_GEN2(dev)) {
+ error-ier = I915_READ16(IER);
+ } else if (!IS_VALLEYVIEW(dev)) {
+ error-ier = I915_READ(IER);
}
-
- /* 4: Everything else */
error-eir = I915_READ(EIR);
error-pgtbl_er = I915_READ(PGTBL_ER);
--
1.9.1
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Fix DEIER and GTIER collecting for BDW.
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
https://bugs.freedesktop.org/show_bug.cgi?id=81701
v2: Fix small issues of first version and don't read DEIER regs when pipe's
power well is disabled
v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gpu_error.c | 32
3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b7..b3493d3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -703,6 +703,10 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
}
for_each_pipe(pipe) {
+ if (!intel_display_power_enabled(dev_priv,
+
POWER_DOMAIN_PIPE(pipe)))
+ continue;
+
seq_printf(m, Pipe %c IMR:\t%08x\n,
pipe_name(pipe),
I915_READ(GEN8_DE_PIPE_IMR(pipe)));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60227b2..d1ae952 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,7 +317,9 @@ struct drm_i915_error_state {
u32 eir;
u32 pgtbl_er;
u32 ier;
- u32 gtier;
+ u32 gtier[4];
+ u32 deier[3];
+ u32 de_misc_ier;
u32 ccid;
u32 derrmr;
u32 forcewake;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c8f901f..402b621 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -328,6 +328,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf
*m,
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_error_state *error = error_priv-error;
struct drm_i915_error_object *obj;
+ enum pipe pipe;
int i, j, offset, elt;
int max_hangcheck_score;
@@ -359,8 +360,20 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
err_printf(m, PCI ID: 0x%04x\n, dev-pdev-device);
err_printf(m, EIR: 0x%08x\n, error-eir);
err_printf(m, IER: 0x%08x\n, error-ier);
+ if (IS_BROADWELL(dev)) {
+ for_each_pipe(pipe)
+ err_printf(m, DEIER pipe %c: 0x%08x\n,
+ pipe_name(pipe),
+ error-deier[pipe]);
+ for (i = 0; i 4; i++)
+ err_printf(m, GTIER gt %d: 0x%08x\n, i,
+ error-gtier[i]);
+ err_printf(m, DE_MISC_IER: 0x%08x\n, error-de_misc_ier);
+ } else {
+ err_printf(m, IER: 0x%08x\n, error-ier);
+ }
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
- err_printf(m, GTIER: 0x%08x\n, error-gtier);
+ err_printf(m, GTIER: 0x%08x\n, error-gtier[0]);
err_printf(m, PGTBL_ER: 0x%08x\n, error-pgtbl_er);
err_printf(m, FORCEWAKE: 0x%08x\n, error-forcewake);
err_printf(m, DERRMR: 0x%08x\n, error-derrmr);
@@ -1093,6 +1106,8 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
struct drm_i915_error_state *error)
{
struct drm_device *dev = dev_priv-dev;
+ enum pipe pipe;
+ int i;
/* General organization
* 1. Registers specific to a single generation
@@ -1104,7 +1119,7 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
/* 1: Registers specific to a single generation */
if (IS_VALLEYVIEW(dev)) {
- error-gtier = I915_READ(GTIER);
+ error-gtier[0] = I915_READ(GTIER);
error-ier = I915_READ(VLV_IER);
error-forcewake = I915_READ(FORCEWAKE_VLV);
}
@@ -1138,9 +1153,18 @@ static void i915_capture_reg_state(struct
drm_i915_private *dev_priv,
if (HAS_HW_CONTEXTS(dev))
error-ccid = I915_READ(CCID);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_BROADWELL(dev)) {
+ for_each_pipe(pipe)
+ if (intel_display_power_enabled(dev_priv,
+
POWER_DOMAIN_PIPE(pipe)))
+ error-deier[pipe] =
+ I915_READ
[Intel-gfx] [PATCH] drm/i915: FBC flush nuke for BDW
According to spec FBC on BDW and HSW are identical without any gaps.
So let's copy the nuke and let FBC really start compressing stuff.
Without this patch we can verify with false color that nothing is being
compressed. With the nuke in place and false color it is possible
to see false color debugs.
Unfortunatelly on some rings like BCS on BDW we have to avoid Bits 22:18 on
LRIs due to a high risk of hung. So, when using Blt ring for frontbuffer rend
cache would never been cleaned and FBC would stop compressing buffer.
One alternative is to cache clean on software frontbuffer tracking.
v2: Fix rebase conflict.
v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c| 3 +++
drivers/gpu/drm/i915/intel_pm.c | 10 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +-
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a372f2..25d7365 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2713,6 +2713,7 @@ extern void intel_modeset_setup_hw_state(struct
drm_device *dev,
extern void i915_redisable_vga(struct drm_device *dev);
extern void i915_redisable_vga_power_on(struct drm_device *dev);
extern bool intel_fbc_enabled(struct drm_device *dev);
+extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value);
extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 883af0b..c8421cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9044,6 +9044,9 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
intel_edp_psr_flush(dev, frontbuffer_bits);
+
+ if (IS_GEN8(dev))
+ gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 684dc5f..de07d3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -345,6 +345,16 @@ bool intel_fbc_enabled(struct drm_device *dev)
return dev_priv-display.fbc_enabled(dev);
}
+void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (!IS_GEN8(dev))
+ return;
+
+ I915_WRITE(MSG_FBC_REND_STATE, value);
+}
+
static void intel_fbc_work_fn(struct work_struct *__work)
{
struct intel_fbc_work *work =
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2908896..2fe871c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -406,6 +406,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
{
u32 flags = 0;
u32 scratch_addr = ring-scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ int ret;
flags |= PIPE_CONTROL_CS_STALL;
@@ -424,7 +425,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
}
- return gen8_emit_pipe_control(ring, flags, scratch_addr);
+ ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
+ if (ret)
+ return ret;
+
+ if (!invalidate_domains flush_domains)
+ return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
+
+ return 0;
}
static void ring_write_tail(struct intel_engine_cs *ring,
--
1.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915: Add thread stall DOP clock gating workaround on Broadwell.
From: Kenneth Graunke kenn...@whitecape.org Ben and I believe this will be necessary on production hardware. Signed-off-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 684dc5f..f919596 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5412,6 +5412,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_ROW_CHICKEN, _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + /* WaDisableThreadStallDopClockGating:bdw */ + I915_WRITE(GEN8_ROW_CHICKEN, + _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + /* * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for * pre-production hardware -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/bdw: Always issue a force restore
From: Ben Widawsky benjamin.widaw...@intel.com The PDPs seem to get screwed up otherwise, specifically PDP0. I am not really clear why this is required, it just works with full PPGTT. v2: Only do it for gen8, to limit regression potential v3: Fix the bugzilla links Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 3b99390..56f7b1e 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -586,6 +586,9 @@ mi_set_context(struct intel_engine_cs *ring, else intel_ring_emit(ring, MI_NOOP); + if (INTEL_INFO(ring-dev)-gen == 8) + hw_flags |= MI_FORCE_RESTORE; + intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_SET_CONTEXT); intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context-legacy_hw_ctx.rcs_state) | -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915: BDW Semaphore signal with Post Sync
With this bit set MI_SEMAPHORE_SIGNAL command is executed as a pipelined PIPE_CONTROL flush command with Semaphore Signal as post sync operation. However this can only be set only when Fixed Function DOP Clock Gate Disable is set. This brought a bit of stability on Semaphores minimizing the hangs. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 3 +++ drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dc13961..27a54a0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -269,6 +269,7 @@ #define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */ #define MI_SEMAPHORE_TARGET(engine) ((engine)15) #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ +#define MI_SEMAPHORE_POST_SYNC (121) #define MI_SEMAPHORE_POLL(115) #define MI_SEMAPHORE_SAD_GTE_SDD (112) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f919596..ab8cbda 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5481,6 +5481,9 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, + _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); + /* WaDisableSDEUnitClockGating:bdw */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cd30b39..edb8234 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -730,6 +730,7 @@ static int gen8_rcs_signal(struct intel_engine_cs *signaller, intel_ring_emit(signaller, signaller-outstanding_lazy_seqno); intel_ring_emit(signaller, 0); intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | + MI_SEMAPHORE_POST_SYNC | MI_SEMAPHORE_TARGET(waiter-id)); intel_ring_emit(signaller, 0); } -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915/bdw: MI_FLUSH_DW a qword instead of dword
From: Ben Widawsky benjamin.widaw...@intel.com
The actual post sync op is Write Immediate Data QWord. It is therefore
arguable that we should have always done a qword write.
The actual impetus for this patch is our decoder complains when we write
a dword and I was trying to eliminate the spurious errors. With this
patch, I've noticed a really strange reproducible error turns into a
different strange reproducible error - so it does indeed have some
effect of some sort.
This was also recommended to me by someone that is familiar with the
Windows driver.
It's based on top of the semaphore series, so it won't be easily
applied, I'd guess.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 95 +
1 file changed, 74 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2908896..9a562b5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -727,7 +727,7 @@ static int gen8_rcs_signal(struct intel_engine_cs
*signaller,
static int gen8_xcs_signal(struct intel_engine_cs *signaller,
unsigned int num_dwords)
{
-#define MBOX_UPDATE_DWORDS 6
+#define MBOX_UPDATE_DWORDS 8
struct drm_device *dev = signaller-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *waiter;
@@ -746,15 +746,18 @@ static int gen8_xcs_signal(struct intel_engine_cs
*signaller,
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
- intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
+ intel_ring_emit(signaller, (MI_FLUSH_DW + 2) |
MI_FLUSH_DW_OP_STOREDW);
intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
MI_FLUSH_DW_USE_GTT);
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
intel_ring_emit(signaller, signaller-outstanding_lazy_seqno);
+ intel_ring_emit(signaller, 0); /* upper dword */
+
intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
MI_SEMAPHORE_TARGET(waiter-id));
intel_ring_emit(signaller, 0);
+ intel_ring_emit(signaller, MI_NOOP);
}
return 0;
@@ -1939,8 +1942,6 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(ring-dev)-gen = 8)
- cmd += 1;
/*
* Bspec vol 1c.5 - video engine command streamer:
* If ENABLED, all TLBs will be invalidated once the flush
@@ -1952,13 +1953,38 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring,
MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(ring-dev)-gen = 8) {
- intel_ring_emit(ring, 0); /* upper addr */
- intel_ring_emit(ring, 0); /* value */
- } else {
- intel_ring_emit(ring, 0);
- intel_ring_emit(ring, MI_NOOP);
- }
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
+ return 0;
+}
+
+static int gen8_bsd_ring_flush(struct intel_engine_cs *ring,
+ u32 invalidate, u32 flush)
+{
+ uint32_t cmd;
+ int ret;
+
+ ret = intel_ring_begin(ring, 6);
+ if (ret)
+ return ret;
+
+ cmd = MI_FLUSH_DW + 2;
+ /*
+* Bspec vol 1c.5 - video engine command streamer:
+* If ENABLED, all TLBs will be invalidated once the flush
+* operation is complete. This bit is only valid when the
+* Post-Sync Operation field is a value of 1h or 3h.
+*/
+ if (invalidate I915_GEM_GPU_DOMAINS)
+ cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
+ MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(ring, 0); /* upper addr */
+ intel_ring_emit(ring, 0); /* value */
+ intel_ring_emit(ring, 0); /* value */
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
}
@@ -2029,8 +2055,38 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring,
return 0;
}
-/* Blitter support (SandyBridge+) */
+static int gen8_ring_flush(struct intel_engine_cs *ring,
+ u32 invalidate, u32 flush)
+{
+ uint32_t cmd;
+ int ret;
+
+ ret = intel_ring_begin(ring, 6);
+ if (ret
