t; + * frames, we'll go with 9 frames for now
> + */
> + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
> + val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> +
> + val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
>
On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza wrote:
> TPS4 support was added to PSR because HBR3/PSR spec was not closed
> when ICL was freezed so if HBR3 was supported by PSR, ICL would
> already be ready but it was not added to spec so lets always
> disable TPS4.
>
> v3: Misse
On Mon, Mar 11, 2019 at 04:38:00PM -0700, Souza, Jose wrote:
> On Mon, 2019-03-11 at 16:34 -0700, Rodrigo Vivi wrote:
> > On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza
> > wrote:
> > > TPS4 support was added to PSR because HBR3/PSR spec was not closed
&g
please file
this bug to DMC while adding a FIXME with DMC bugged version on it?
Aa: Pavana
If it doesn't happen with DMC loaded than maybe a HSD would for hw
team would be good anyway.
Cc: Art.
Thanks,
Rodrigo.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by
Hi Dave and Daniel,
Here goes drm-intel-next-fixes-2019-03-12:
- HDCP state handling in ddi_update_pipe
- Protect i915_active iterators from the shrinker
- Reacquire priolist cache after dropping the engine lock
- (Selftest) Always free spinner on __sseu_prepare error
- Acquire breadcrumb ref bef
On Wed, Mar 13, 2019 at 10:30:52AM -0700, Lucas De Marchi wrote:
> On Fri, Mar 08, 2019 at 01:43:00PM -0800, Rodrigo Vivi wrote:
> > In order to make it easier to bring up new platforms
> > without having to take care about all corner cases
> > that was previously taken care f
On Wed, Mar 13, 2019 at 02:43:30PM +, Chris Wilson wrote:
> In preparation to making the ppGTT binding for a context explicit (to
> facilitate reusing the same ppGTT between different contexts), allow the
> user to create and destroy named ppGTT.
>
> v2: Replace global barrier for swapping ove
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915
From: Bob Paauwe
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/dr
From: Bob Paauwe
Unlike ICL, all of the output ports are combo phys so just return
true in is_port_combophy for all EHL ports to indicate that.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++-
1 file changed, 15 insertions(+), 1
From: James Ausmus
Add known EHL PCI IDs.
Cc: Bob Paauwe
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_pci.c | 9 +
include/drm/i915_pciids.h | 7 +++
3 files changed, 17 insertions(+)
diff
From: Bob Paauwe
While EHL does support 4 level extended ppgtt, it only makes use
of 36 bits instead of the 48 like the other platforms that have
4 level extended ppgtt.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++---
1 file
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915
On Wed, Mar 13, 2019 at 08:47:41PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-03-13 20:11:21)
> > On Wed, Mar 13, 2019 at 02:43:30PM +, Chris Wilson wrote:
> > > + /*
> > > + * We need to flush any requests using the current ppgtt before
>
I just noticed that initial PCH comparative patch
left some >= PCH_ICP cases behind.
Let's also cover these cases and leave only the pin map
behind now.
No functional change. Hence no fixes tag.
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_irq.
>
> More support and features will be in the patches that follow.
>
> v2: Split IDs according to GT. (Rodrigo)
>
> v3: Update IDs.
>
> Cc: Rodrigo Vivi
> Cc: Lucas De Marchi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915
On Thu, Mar 14, 2019 at 11:29:18AM -0700, Anusha wrote:
> From: Anusha Srivatsa
>
> Comet Lake PCH is based off of Cannon Point(CNP).
> Add PCI ID for Comet Lake PCH.
>
> v2: Code cleanup (DK)
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: Anu
On Thu, Mar 14, 2019 at 11:45:18AM -0700, Lucas De Marchi wrote:
> On Wed, Mar 13, 2019 at 02:43:07PM -0700, Rodrigo Vivi wrote:
> > I just noticed that initial PCH comparative patch
> > left some >= PCH_ICP cases behind.
> >
> > Let's also cover these cases an
tter reflect the commonality of using 4 levels.
>
> Based on a patch by Bob Paauwe
>
> Signed-off-by: Chris Wilson
> Cc: Bob Paauwe
> Cc: Matthew Auld
> Cc: Joonas Lahtinen
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gvt/scheduler.c| 6 ++---
>
On Thu, Mar 14, 2019 at 10:38:39PM +, Chris Wilson wrote:
> The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> so refactor that into a common routine.
>
> Signed-off-by: Chris Wilson
> Cc: Bob Paauwe
> Cc: Matthew Auld
> Cc: Joonas Lahtinen
a patch by Bob Paauwe
>
> Signed-off-by: Chris Wilson
> Cc: Bob Paauwe
> Cc: Zhenyu Wang
> Cc: Zhi Wang
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.c| 2 +-
> drivers/gpu/drm/i915/i915_pvinfo.h
atic struct i915_hw_ppgtt *gen6_ppgtt_create(struct
> drm_i915_private *i915)
>
> ppgtt->base.vm.i915 = i915;
> ppgtt->base.vm.dma = &i915->drm.pdev->dev;
> -
> - ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
> + ppg
nt, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
> + value = INTEL_PPGTT(dev_priv);
I don't know the users of this param so I'm not 100% confident that this
doesn't break something.
But overall this seems the right way to go and the rest of
the patch looks
rkaround the issue by cleaning PSR_CTL before enable PSR2.
>
> v2:
> - Updated commit description and comment to state that it may be
> a DMC firmware issue (Rodrigo)
> - No need to RMW, let's write 0 to PSR_CTL(Dhinakaran)
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Viv
lson
> Cc: Mika Kuoppala
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3d8020888604.
On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> On Fri, 15 Mar 2019 09:09:11 +
> Chris Wilson wrote:
>
> > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > On Thu, Mar 14, 2019 at 10:38:39PM +, Chris Wilson wrote:
> > > > The basic se
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-7-rodrigo.v...@intel.com
---
drivers/gpu/drm/i915
From: James Ausmus
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for proper ack.
Cc: Bob Paauwe
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-2-rodrigo.v...@intel.com
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-6-rodr
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-9-rodrigo.v...@intel.com
---
drivers/gpu/drm/i915
On Fri, Mar 15, 2019 at 10:26:04AM -0700, Bob Paauwe wrote:
> On Fri, 15 Mar 2019 10:01:51 -0700
> Rodrigo Vivi wrote:
>
> > On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > > On Fri, 15 Mar 2019 09:09:11 +
> > > Chris Wilson wrote:
> >
Let's reserve EHL stolen memory for graphics.
ElkhartLake is a gen11 platform which is compatible with
ICL changes.
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Cc: José Roberto de Souza
Signed-off-by: Rodrigo Vivi
---
_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
Cc: Bob Paauwe
Cc: Chris Wilson
Cc: José Roberto de Souza
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++
include/drm/i915_pciids.h | 7 +++
2 files ch
On Fri, Mar 15, 2019 at 11:39:54AM -0700, Vanshidhar Konda wrote:
> Extend the timeout for the hardware to signal SEND_BUSY on the DP
> Aux Channel Controller register.
>
> This is needed to address FDO #109982
> https://bugzilla.freedesktop.org/show_bug.cgi?id=109982
instead of mentioning like t
On Fri, Mar 15, 2019 at 01:27:22PM -0700, Vanshidhar Konda wrote:
> On Fri, Mar 15, 2019 at 12:38:41PM -0700, Rodrigo Vivi wrote:
> > On Fri, Mar 15, 2019 at 11:39:54AM -0700, Vanshidhar Konda wrote:
> > > Extend the timeout for the hardware to signal SEND_BUSY on the DP
On Fri, Mar 15, 2019 at 02:31:40PM -0700, Rodrigo Vivi wrote:
> On Fri, Mar 15, 2019 at 01:27:22PM -0700, Vanshidhar Konda wrote:
> > On Fri, Mar 15, 2019 at 12:38:41PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Mar 15, 2019 at 11:39:54AM -0700, Vanshidhar Konda wrote:
> > &g
On Fri, Mar 15, 2019 at 02:39:25PM -0700, Rodrigo Vivi wrote:
> On Fri, Mar 15, 2019 at 02:31:40PM -0700, Rodrigo Vivi wrote:
> > On Fri, Mar 15, 2019 at 01:27:22PM -0700, Vanshidhar Konda wrote:
> > > On Fri, Mar 15, 2019 at 12:38:41PM -0700, Rodrigo Vivi wrote:
> > > &
On Fri, Mar 15, 2019 at 03:56:17PM +0200, Jani Nikula wrote:
> v4 of [1], rebased and very mildly tweaked, with the intention to merge.
before it starts conflicting again :)
> I added
> Chris' Reviewed-bys despite the rebase.
Acked-by: Rodrigo Vivi
Do you intend to follow-up wit
On Fri, Mar 15, 2019 at 04:05:12PM -0700, Vanshidhar Konda wrote:
> On Fri, Mar 15, 2019 at 02:43:46PM -0700, Rodrigo Vivi wrote:
> > On Fri, Mar 15, 2019 at 02:39:25PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Mar 15, 2019 at 02:31:40PM -0700, Rodrigo Vivi wrote:
> > > &
On Mon, Mar 18, 2019 at 10:26:52PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pass dev_priv to intel_get_lvds_encoder() and polish the
> implementation a bit.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_d
On Mon, Mar 18, 2019 at 10:26:51PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Sprinkle some curly braces in accordance with the coding style.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_display.c | 11
On Mon, Mar 18, 2019 at 10:26:53PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make things look a bit nicer by passing dev_priv to
> intel_is_dual_link_lvds().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i
Hi Shaobo,
n Mon, Mar 18, 2019 at 05:01:10PM -0600, Shaobo He wrote:
> Hello everyone,
>
> My name is Shaobo He and I am a graduate student at University of Utah. I am
> using a static analysis tool to search for null pointer dereferences and
> came across a potentially invalid memory access in t
return NULL;
>
> Thanks,
> Shaobo
> On 3/18/19 5:26 PM, Rodrigo Vivi wrote:
> > Hi Shaobo,
> >
> > n Mon, Mar 18, 2019 at 05:01:10PM -0600, Shaobo He wrote:
> > > Hello everyone,
> > >
> > > My name is Shaobo He and I am a graduate student a
t; > So all of this discussion is hypothetical in the sense that it really
> > should never happen. You can track down the args passed to
> > intel_gmbus_get_adapter(), while the static analyzer is unable to do
> > that.
> >
> > BR,
> > Jani.
> >
> >
&g
On Tue, Mar 19, 2019 at 05:50:22PM +0200, Jani Nikula wrote:
> On Mon, 18 Mar 2019, Ville Syrjälä wrote:
> > On Mon, Mar 18, 2019 at 09:45:16PM +0100, Michal Wajdeczko wrote:
> >> > Make things look a bit nicer by passing dev_priv to
> >>
> >> In other places we are changing naming from dev_priv
Hi Dave and Daniel,
Here goes the first round of fixes for 5.1-rc cycle.
I will be out on vacation next week, so next week's pull request
might come from Jani. Although things looks calm right now.
only 3 patches on top of -rc1:
drm-intel-fixes-2019-03-20:
A protection on our mmap against atte
On Thu, Mar 21, 2019 at 11:50:18AM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Sorry that I might miss 5.1-rc1 window as I was in full day event
> during this week.
hmm... my bad. I should had remembered that you had stuff queued for
-fixes that we didn't put in -next-fixes
I'm sorry.
> Here's r
("drm/i915: Allocate enough DDB for the cursor")
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 7 +
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Signed-off-by
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu
_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
Cc: Bob Paauwe
Cc: Chris Wilson
Cc: José Roberto de Souza
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
Reviewed-by: Bob Paauwe
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 9 insertions
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: Bob Paauwe
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1
_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
v4: (Rodrigo): - remove ppgtt type added on v3. Jose pointed it is not
needed.
Cc: Bob Paauwe
Cc: Chris Wilson
Cc: José Roberto de Souza
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
Reviewed-by: B
Hi Stephen,
On Fri, Mar 22, 2019 at 10:57:28AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the drm-intel tree got a conflict in:
>
> drivers/gpu/drm/i915/gvt/mmio_context.c
>
> between commit:
>
> 1e8b15a1988e ("drm/i915/gvt: Add in context mmio 0x20D8 to gen9
_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
v4: (Rodrigo): - remove ppgtt type added on v3. Jose pointed it is not
needed.
Cc: Bob Paauwe
Cc: Chris Wilson
Cc: José Roberto de Souza
Signed-off-by: James Ausmus
Signed-off-by: Rodrigo Vivi
Reviewed-by: B
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: Bob Paauwe
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Signed-off-by
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 9 insertions
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus DSI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 7 +
On Wed, Jun 05, 2019 at 06:05:23PM -0700, Souza, Jose wrote:
> This is the same as WHL, we added the AML separated just in case it
> needed some different workaround or code path but looks like it don't
> need at all.
>
> Any objection with this change Rodrigo?
Nope.
Revie
l.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
>
> Before reading any part of the firmware file, validate the input first.
>
> Fixes: eb805623d8b1 ("drm/i915/skl: Add support to load SKL CSR firmware.")
> Cc: sta...@vger.kernel.org
> Signed-off-by:
On Thu, Jun 06, 2019 at 10:36:39AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> These two are only used from within i915_gem_gtt.c and can trivially be
> made static.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm
On Thu, Jun 06, 2019 at 10:36:38AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> These functions operate on ggtt so make them take that directly as
> parameter.
This patch makes me wonder where we really want and need to go.
We need to move out of dev_priv and global i915...
but do we
On Thu, Jun 06, 2019 at 10:36:35AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Replace some gen6/7 open coded rmw with intel_uncore_rmw.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i91
On Wed, Jun 05, 2019 at 03:15:22PM -0700, Matt Roper wrote:
> On Wed, Jun 05, 2019 at 02:51:08PM -0700, Manasi Navare wrote:
> > On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote:
> > > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that
> > > this just extends the upper l
ingly clean operation.
> >
> > Cc: Chris Wilson
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
> > Cc: Ville Syrjälä
> > Signed-off-by: Jani Nikula
>
> Only surprisingly clean because you already
tions (i.e.
> along the lines of DIRTYFB). However, the implicit back-channel
> notifications are much easier to organise.
>
> > Cc: Chris Wilson
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
> > Cc: Vill
; >
> > > > v3: Fix build break in selftest. Rebase to newer base tree and fix
> > > > merge conflict.
> > > >
> > > > v4: More rebasing. Rmoved relative addressing support from Gen7-9 only
> > > > code paths [review feed
On Thu, Jun 13, 2019 at 01:28:42PM +0100, Chris Wilson wrote:
> refcount_t is our first line of defence against use-after-free, so let's
> enable it for debugging.
It seems a nice thing to have on debug by default and they promise no
performance impact.
Acked-by: Rodrigo Vivi
Well,
On Thu, Jun 13, 2019 at 09:48:16AM -0700, Lucas De Marchi wrote:
> On Thu, Jun 13, 2019 at 09:29:48AM -0700, Lucas De Marchi wrote:
> > On Thu, Jun 13, 2019 at 04:12:37PM +0300, Jani Nikula wrote:
> > > On Wed, 12 Jun 2019, Lucas De Marchi wrote:
> > > > We are slowly converting dev_priv to i915 e
On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Start using the newly introduced struct intel_gt to fuse together correct
> logical init flow with uncore for more removal of implicit dev_priv in
> mmio access.
>
> v2:
> * Move code to i915_gem_fence_re
On Fri, Jun 14, 2019 at 04:17:00PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Most of v3 review feedback plus more of:
>
> Also, while nosing around in the code I have spotted more opportunities to
> compartmentalize, either using intel_gt, or some other object as appropriate.
>
On Fri, Jun 14, 2019 at 04:17:03PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> As it will grow in a following patch make a new home for it.
>
> v2:
> * Convert mock_gem_device as well. (Chris)
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
tel_gt in order to initialize
> the hardware.
>
> GuC and engines are the only odd ones out remaining.
we can take care of them later, but soon :)
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gem.c | 66
On Fri, Jun 14, 2019 at 04:17:15PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> More legacy mmio accessor removal. We pass in intel_gt explicitly allowing
> code to use new intel_uncore_read/write helpers.
>
> Signed-off-by: Tvrtko Ursulin
Reviewe
most sense for them instead of
> the global struct drm_i915_private.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +++--
> 1 file changed, 21 insertions(+), 10 deletions(-)
>
On Fri, Jun 14, 2019 at 04:36:57PM +0100, Tvrtko Ursulin wrote:
>
> On 14/06/2019 16:25, Rodrigo Vivi wrote:
> > On Fri, Jun 14, 2019 at 04:17:06PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Start using the newly introduced s
On Fri, Jun 14, 2019 at 05:21:39PM +0100, Tvrtko Ursulin wrote:
>
> On 14/06/2019 17:16, Rodrigo Vivi wrote:
> > On Fri, Jun 14, 2019 at 04:36:57PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 14/06/2019 16:25, Rodrigo Vivi wrote:
> > > > On Fri, Jun 14
On Fri, Jun 14, 2019 at 04:17:19PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This will come useful in the following patch.
>
> Signed-off-by: Tvrtko Ursulin
an individual commit message would be better, but let's focus
on the content:
Revie
gned-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 4 file
>
> @@ -3716,6 +3720,11 @@ void i915_gem_restore_gtt_mappings(struct
> drm_i915_private *dev_priv)
> ggtt->invalidate(ggtt);
>
> mutex_unlock(&ggtt->vm.mutex);
> +}
> +
> +void i915_gem_restore_gt
f0566a641f9 ("drm/i915: move modesetting core code under display/")
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> Documentation/gpu/i915.rst | 66 +++
gens so lets force a PSR exit.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110799
:(
Reviewed-by: Rodrigo Vivi
and if bugs persist or this brings back older bugs it is time
to consider removing psr support at all for gen < 9 :-/
> Cc: Dhinakaran Pandiyan
> Cc: Ro
the top level to work around
> >the layering violation. (Chris)
> >
> > v3:
> > * Handle selftests.
> >
> > v4:
> > * Move call to intel_gt_init_hw into mock_init_ggtt. (Chris)
> >
> > Signed-off-by: Tvrtko Ursulin
> > Reviewed-by
. (Chris)
> >
> > v3:
> > * Rename to intel_gt_init_early and move call site to i915_drv.c. (Chris)
> >
> > Signed-off-by: Tvrtko Ursulin
> > Reviewed-by: Rodrigo Vivi # v2
> > ---
> > drivers/gpu/drm/i915/Makefile| 1 +
> >
On Wed, Jun 19, 2019 at 02:24:26PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Rebase + a couple fixes for mock tests.
>
> Some patches need r-b and/or r-b upgrades.
I updated my 2 rv-b and I quickly glanced through the rest and didn't
find anything else, so I believe we are ready
gt; > > v4: More rebasing. Rmoved relative addressing support from Gen7-9 only
> > > code paths [review feedback from Chris W].
> > >
> > > v5: More rebasing (new 'gt' directory). Fix white space issue. Use
> > > COPY class rather than BCS0
Hi Chunyu,
First of all sorry for the delay on the response here.
Many of us were out on vacation and holidays.
Also in general please use https://bugs.freedesktop.org/
to report bugs.
Please make sure you read this before:
https://01.org/linuxgraphics/documentation/how-report-bugs
(more inline
On Mon, Jul 08, 2019 at 04:16:09PM -0700, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h
On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> From: Mika Kahola
>
> Add power well 5 to support 4th pipe and transcoder on TGL.
>
> Cc: James Ausmus
> Cc: Imre Deak
> Signed-off-by: Mika Kahola
> Signed-off-by: Lucas De Marchi
> ---
> .../drm/i915/display/intel_display_
On Tue, Jun 25, 2019 at 10:54:17AM -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
> register (and format).
>
> Cc: Ingo Molnar
> Cc: H. Peter Anvin
> Cc: x...@kernel.org
> Cc: Rodrigo
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