o Chehab
same here, not checked if these would be all the files, but it is reasonable
Reviewed-by: Rodrigo Vivi
> ---
>
> To avoid mailbombing on a large number of people, only mailing lists were C/C
> on the cover.
> See [PATCH v2 00/39] at:
> https://lore.kernel.org/all/c
ill consider them to be placed at the wrong place.
>
> Fix (1) and change the way the parameters are described, using
> a list, in order for it to be properly parsed during documentation
> build time.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Rodrigo Vivi
> ---
&g
On Wed, Jul 13, 2022 at 09:12:18AM +0100, Mauro Carvalho Chehab wrote:
> There are several documented GT kAPI that aren't currently part
> of the docs. Add them, as this allows identifying issues with
> badly-formatted tags.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
>
> To avoid mailbombing
On Wed, Jul 13, 2022 at 09:12:22AM +0100, Mauro Carvalho Chehab wrote:
> There are several documented GEM/TTM kAPI that aren't currently part
> of the docs. Add them, as this allows identifying issues with
> badly-formatted tags.
>
> Signed-off-by: Mauro Carvalho Chehab
On Wed, Jul 13, 2022 at 09:12:21AM +0100, Mauro Carvalho Chehab wrote:
> Both intel_runtime_pm.h and intel_pm.c contains kAPI for
> runtime PM. So, add them to the documentation.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Rodrigo Vivi
> ---
>
> To avoid m
On Wed, Jul 13, 2022 at 09:12:25AM +0100, Mauro Carvalho Chehab wrote:
> This is a large struct used to describe gem objects. It is
> currently partially documented. Finish its documentation, filling
> the gaps from git logs.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-b
On Wed, Jul 13, 2022 at 09:12:24AM +0100, Mauro Carvalho Chehab wrote:
> commit d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr")
> added a rbtree list to allow searching for obj/ctx.
>
> Document it.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by:
On Wed, Jul 13, 2022 at 09:12:26AM +0100, Mauro Carvalho Chehab wrote:
> The intel_gt_pm.h file contains some convenient macros to be used
> in GT code in order to get/put runtime PM references and for
> checking them.
>
> Add descriptions based on the ones at intel_wakeref.h and
> intel_runtime_p
On Wed, Jul 13, 2022 at 09:12:19AM +0100, Mauro Carvalho Chehab wrote:
> There are several documented GuC kAPI that aren't currently part
> of the docs. Add them, as this allows identifying issues with
> badly-formatted tags.
>
> Signed-off-by: Mauro Carvalho Chehab
Revie
On Wed, Jul 13, 2022 at 09:12:27AM +0100, Mauro Carvalho Chehab wrote:
> Currently, functions inside GuC aren't presented as part of the
> GuC documentation.
>
> Add them.
>
> Signed-off-by: Mauro Carvalho Chehab
could be squashed to the other guc patch, but anyways:
Re
On Wed, Jul 13, 2022 at 09:12:23AM +0100, Mauro Carvalho Chehab wrote:
> There are other files with kernel-doc markups:
>
> $ git grep -l "/\*\*" $(git ls-files|grep drivers/gpu/drm/i915/)
> >kernel-doc-files
> $ for i in $(cat kernel-doc-files); do if [ "$(git grep $i
> Documentatio
gt; parameter or member 'flags' not described in 'i915_ttm_restore_region'
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c:199: warning: Excess
> function parameter 'allow_gpu' description in 'i915_ttm_restore_region'
>
> Signed-off-by: Mau
On Mon, Aug 08, 2022 at 04:05:55PM +0530, Anshuman Gupta wrote:
> As per PCIe Spec Section 5.3,
> When a Type 1 Function associated with a Switch/Root
> Port (a “virtual bridge”) is in a non-D0 power state,
> it will emulate the behavior of a conventional PCI bridge
> in its handling of Memory, I/O
Hi Dave and Daniel,
And here is the right one. And now including all the
fixes.
Here goes drm-intel-next-fixes-2022-08-11:
- disable pci resize on 32-bit systems (Nirmoy)
- don't leak the ccs state (Matt)
- TLB invalidation fixes (Chris)
[now with all fixes of fixes]
Thanks,
Rodrigo.
The follo
read for obtaining
> the correct efficient frequency for Gen9+.
>
> We see much better perf numbers with benchmarks like glmark2 with
> efficient frequency usage enabled as expected.
>
> v2: Address review comments (Rodrigo)
>
> BugLink: https://gitlab.freedesktop.org/drm
On Mon, Aug 15, 2022 at 10:38:55AM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's one gvt-fixes pull for 6.0-rc. Major one is Cometlake regression
> fix for mmio table rework, and others are left kernel doc fixes not pushed
> yet.
>
> Thanks
> --
> The following changes since commit a7a47a5dfa9a9
On Mon, Aug 22, 2022 at 11:12:15AM +0800, Zhenyu Wang wrote:
>
> (resend after fixing sign-off after rebase)
>
> Hi,
>
> Here's one gvt-fixes pull for 6.0-rc. Major one is Cometlake
> regression fix for mmio table rework, and others are left kernel doc
> fixes not pushed yet.
Pulled, thanks!
>
On Mon, Apr 11, 2022 at 08:47:30PM +, Sean Paul wrote:
> From: Sean Paul
>
> This patch moves the hdcp atomic check from i915 to drm_hdcp so other
> drivers can use it. No functional changes, just cleaned up some of the
> code when moving it over.
Reviewed-by: Rodrigo Vivi
* that the driver try CP enable.
> + */
> + if (new_hdcp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
> + new_conn_state->crtc != old_conn_state->crtc)
> + return true;
I'm with the feeling that this chunk should deserve a separated pat
On Mon, Apr 11, 2022 at 08:47:32PM +, Sean Paul wrote:
> From: Sean Paul
>
> This patch updates the connector's property value in 2 cases which were
> previously missed:
>
> 1- Content type changes. The value should revert back to DESIRED from
>ENABLED in case the driver must re-authenti
On Mon, Apr 11, 2022 at 08:47:35PM +, Sean Paul wrote:
> From: Sean Paul
>
> The shim functions return error codes, but they are discarded in
> intel_hdcp.c. This patch plumbs the return codes through so they are
> properly handled.
Reviewed-by: Rodrigo Vivi
>
>
On Mon, Apr 11, 2022 at 08:47:34PM +, Sean Paul wrote:
> From: Sean Paul
>
> Stick all of the setup for HDCP into a dedicated function. No functional
> change, but this will facilitate moving HDCP logic into helpers.
Reviewed-by: Rodrigo Vivi
>
> Acked-by: Jani Nikul
On Mon, Apr 11, 2022 at 08:47:29PM +, Sean Paul wrote:
> From: Sean Paul
>
> Rebased set from November. Fixed a nit from Stephen in the msm patch and
> moved hdcp registers into the trogdor dtsi file to avoid differences
> with sc7180-based windows devices. The set is 4 patches lighter since
_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
> + } else if (IS_ALDERLAKE_P(dev_priv)) {
> dmc->fw_path = ADLP_DMC_PATH;
> dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
> dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
probably worth to rename the dev_priv to i915 on these functions you are
touching in here...
anyway:
Reviewed-by: Rodrigo Vivi
> --
> 2.25.1
>
;s reserve for PCODE.
Bit 4: Let's reserve for PSMI.
Cc: Tilak Tangudu
Cc: Mika Kuoppala
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
On Thu, Apr 14, 2022 at 03:58:02PM +, Sean Paul wrote:
> On Tue, Apr 12, 2022 at 09:25:59AM -0400, Rodrigo Vivi wrote:
> > On Mon, Apr 11, 2022 at 08:47:32PM +, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > This patch updates the connector&#x
On Thu, Apr 14, 2022 at 03:31:07PM -0700, Dixit, Ashutosh wrote:
> On Thu, 14 Apr 2022 06:28:57 -0700, Jani Nikula wrote:
> >
> > On Wed, 13 Apr 2022, Ashutosh Dixit wrote:
> > > Each gt contains an independent instance of pcode. Extend pcode functions
> > > to interface with pcode on different gt
_info to
> identify these platforms and set it for XEHPSDV and DG2/ATS-M.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/
On Wed, Apr 13, 2022 at 11:11:05AM -0700, Ashutosh Dixit wrote:
> Add a couple of helpers to help formatting pcode commands and improve code
> readability.
>
> Cc: Mike Ruhl
> Cc: Rodrigo Vivi
> Original-author: Dale B Stimson
The right thing to do here is to git commit --am
since
DC9 is a software thing, it is better to disable DC5 before
to avoid any conflict. And respect the spec to avoid potential
future issues.
Cc: Imre Deak
Cc: Anshuman Gupta
Cc: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
1
On Wed, Apr 20, 2022 at 10:21:19PM +0300, Imre Deak wrote:
> On Wed, Apr 20, 2022 at 03:09:21PM -0400, Rodrigo Vivi wrote:
> > According to BSPec:
> > Sequence to Allow DC9:
> > 1. Follow Sequence to Disallow DC5.
> >
> > which is:
> &g
adds the following sysfs files to gt/gtN sysfs:
> * media_freq_factor
> * media_freq_factor.scale
>
> Cc: Rodrigo Vivi
> Cc: Joonas Lahtinen
> Signed-off-by: Dale B Stimson
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h |
return (status & huc->status.mask) == huc->status.value;
oh, these variable names look so generic, while it looks like the only usage
for them is for mask = loaded and value = loaded...
But anyway it is better this indirection with some generic name than duplicating
the defini
vior.
>
> Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 11 ++-
> 2 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu
userspace to revert to default values when needed.
>
> This patch adds the following sysfs files to gt/gtN/.defaults:
> * default_min_freq_mhz
> * default_max_freq_mhz
> * default_boost_freq_mhz
>
> Cc: Rodrigo Vivi
> Cc: Andi Shyti
> Cc: Joonas Lahtinen
> Signed-off
On Thu, Apr 28, 2022 at 05:39:43PM -0700, Ashutosh Dixit wrote:
> Add the following sysfs file to gt/gtN/.defaults:
> * media_freq_factor
>
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i91
out this earlier.
but some comments below...
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Andi Shyti
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 17 +++
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +
> drivers/gpu/drm/i915/i915_d
o eliminate needless #defines (Rodrigo)
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Andi Shyti
> Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c| 4 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 6 +-
On Mon, May 02, 2022 at 09:34:10AM -0700, Matt Roper wrote:
> The SoC registers, including RP_STATE_CAP, have moved to a new location
> in GTTMMADR on Ponte Vecchio. We need to update the register offset
> accordingly.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Matt Roper
Reviewe
go on a RIL system showed promising
> results when dc5 was completely diabled and i915 took only dc9 paths.
>
> Sending this so we can check the CI results to confirm the
> findings from local testing which will hopefully help narrow
> down the root cause of MMIO BAR lost issue
>
On Tue, Nov 09, 2021 at 02:48:50PM +0300, Dan Carpenter wrote:
> The "ret" variable is checked on the previous line so we know it's
> zero. No need to check again.
>
> Signed-off-by: Dan Carpenter
Reviewed-by: Rodrigo Vivi
and pushed.
thanks for the patch
&g
Hi Dave and Daniel,
Here goes drm-intel-next-fixes-2021-11-09:
Couple Reverts, build fix, couple virtualization fixes,
blank screen and other display rates fixes, and more.
Four patches targeting stable in here.
Display Fixes:
- DP rates related fixes (Imre, Jani)
- A Revert on disaling dual eD
On Wed, Nov 10, 2021 at 01:46:46PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 10, 2021 at 10:59:26AM +0530, Tilak Tangudu wrote:
> > Enable runtime pm autosuspend by default for gen12 and
> > later versions.
> >
> > Signed-off-by: Tilak Tangudu
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c
On Mon, Nov 15, 2021 at 01:44:57PM +0200, Jani Nikula wrote:
> On Mon, 15 Nov 2021, Tilak Tangudu wrote:
>
> The actual commit message with explanations why it will work now and
> didn't work before go here.
The truth is that:
1. We don't have a good track of *all* the issues with the past atte
x27;s move the DSS lookup for a DG2 workaround into a helper function
> that will only get called after we've already decided that we're on a
> DG2 platform.
>
> Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
> Signed-off-by: Matt Ro
On Fri, Nov 12, 2021 at 09:38:05PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
> definition to match. And while at it let's also add the define
> for the current field readback.
>
> We can also get rid of the gen2 vs. gen3
On Fri, Nov 12, 2021 at 09:38:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for FPGA_DBG/CLAIM_ER bits.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8
> 1 file
On Fri, Nov 12, 2021 at 09:38:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for DPINVTT/VLV_DPFLIPSTAT bits.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/
On Fri, Nov 12, 2021 at 09:38:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the CRC registers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 77 ++
On Fri, Nov 12, 2021 at 09:38:06PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for PIPEMISC* bits, and while at it
> fill in the missing dithering bits since we already had some
> of them defined.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/displ
ernal experiments for s3/s4 failed with that
and this approach here was the safest one, so let's move with this and
prevent the d3cold for now and then allow the runtime_pm autosuspend
enabled by default everywhere.
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.c | 19
On Mon, Nov 15, 2021 at 02:20:36PM -0500, Rodrigo Vivi wrote:
> On Mon, Nov 15, 2021 at 09:10:54PM +0530, Tilak Tangudu wrote:
> > s2idle and runtime pm puts the pci gfx device in D3Hot, ACPI runtime
> > monitors the pci tree,if it sees complete tree as D3Hot,it transitions
&g
On Mon, Nov 15, 2021 at 09:58:56AM -0500, Rodrigo Vivi wrote:
> On Mon, Nov 15, 2021 at 01:44:57PM +0200, Jani Nikula wrote:
> > On Mon, 15 Nov 2021, Tilak Tangudu wrote:
> >
> > The actual commit message with explanations why it will work now and
> > didn't wor
On Tue, Nov 16, 2021 at 03:58:13PM +0200, Jani Nikula wrote:
> Use <> not "" for including headers from include/drm.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 ++-
> drivers/gpu/dr
On Tue, Nov 16, 2021 at 02:49:16PM +0300, Dan Carpenter wrote:
> The intel_engine_create_virtual() function does not return NULL. It
> returns error pointers.
>
> Fixes: e5e32171a2cf ("drm/i915/guc: Connect UAPI to GuC multi-lrc interface")
> Signed-off-by: Dan Carpent
.html?
hmm... I could swear that I had seen the ADL-P green there a few
days ago as well... But right now I couldn't see ADL-P there...
So that fails on having a *reliable* green CI picture...
Any idea why that is down at this moment?
>
> Cc: Rodrigo Vivi
>
> Signed-o
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-11-18:
One quick fix for return error handling, one fix for ADL-P display
and one revert targeting stable 5.4, for TGL's DSI display clocks
Thanks,
Rodrigo.
The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:
Linux 5
On Mon, Nov 22, 2021 at 01:15:04PM +0200, Jani Nikula wrote:
> Follow the convention of corresponding .h for .c.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
for the series
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> drivers/gpu/drm/i915
On Mon, Nov 22, 2021 at 09:57:30AM +0530, Tejas Upadhyay wrote:
> Please do not merge this is trybot patch to run CI with PXP
> and MEI PXP enabled to get premegre results for
> https://patchwork.freedesktop.org/series/96658/#rev3 change.
Please don't send this kind of tests to intel-gfx ml.
Plea
> > platforms(Syrjala Ville)
> >
> > v3: Change commit message(Nikula Jani)
> It would require to reorder the commit log, version log
> need to move after commit message.
Well noticed. I changed while pushing.
So, for the record:
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ro
On Wed, Nov 17, 2021 at 02:49:55PM -0800, Vinay Belgaumkar wrote:
> From: Chris Wilson
>
> While the power consumption is proportional to the frequency, there is
> also a static draw for active gates. The longer we are able to powergate
> (rc6), the lower the static draw. Thus there is a sweetspo
balancing (always like in the initial implementation vs
only once like the in 90a987205c6c).
If this one is really fixing the regression by itself:
Acked-by: Rodrigo Vivi
on this patch here.
But I still don't want to take the risk with touching the freq with
race to idle, until not con
On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
>
> On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > >
> > > On 17/11/2021 22:49, Vinay Belgaumkar wrote:
> > > > From: Chris
On Wed, Nov 24, 2021 at 08:55:39AM -0500, Rodrigo Vivi wrote:
> On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
> >
> > On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > > >
Hi Dave and Daniel,
Only one fix for this round. Sending earlier today due to Holiday in US
tomorrow.
Here goes drm-intel-fixes-2021-11-24:
Fix wakeref handling of PXP suspend.
Thanks,
Rodrigo.
The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6:
Linux 5.16-rc2 (2021
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-12-02:
- Fixing a regression where the backlight brightness control stopped working.
- Fix the Intel HDR backlight support detection.
- Reverting a w/a to fix a gpu Hang in TGL. The w/a itself was also
for a hang, but in a much rarer scenario.
instead of
this
if we should be listing the devices individually, probably using the
DECLARE_PCI_FIXUP_HEADER or some other way to make it clear and explicit the
opt-in
on the quirk.
Anyway, the addition of this one here is needed and the rest can be in a
follow-up:
Reviewed-by: Rodrigo Vivi
Cc: Baolu Lu
Cc: David Woodhouse
Baolu, David, could we push this through drm-intel?
> return;
>
> if (risky_device(dev))
> --
> 2.34.1
>
On Thu, Feb 17, 2022 at 06:02:23PM +0530, Tejas Upadhyay wrote:
> We dont need to implement reset_domain in intel_engine
> _setup(), but can be done as a helper. Implemented as
> engine->reset_domain = get_reset_domain().
>
> Cc: Rodrigo Vivi
> Signed-off-by: Tejas Upadhy
drm/i915/dg2: Add Wa_22011450934
drm/i915: align the plane_vma to min_page_size of stolen mem
drm/i915: More gt idling time with guc submission
Rodrigo Vivi (1):
Merge tag 'drm-intel-gt-next-2022-02-17' of
git://anongit.freedesktop.org/drm/drm-intel into drm-intel-n
On Thu, Feb 24, 2022 at 02:15:44PM +, Souza, Jose wrote:
> + Rodrigo
>
> On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote:
> > > > On Thu, 2022-02-24 at 1
On Thu, Jan 27, 2022 at 09:20:14AM +0100, Maarten Lankhorst wrote:
> Op 26-01-2022 om 14:09 schreef Jouni Högander:
> > We should now rely on userspace doing dirtyfb. There is no
> > need to have separate frontbuffer tracking hooks in gem code.
> >
> > This patch is removing all frontbuffer trackin
On Thu, Jan 27, 2022 at 11:51:15AM +0300, Dan Carpenter wrote:
> This "ret" declaration shadows an existing "ret" variable at the top of
> the function. Delete it.
>
> Signed-off-by: Dan Carpenter
Reviewed-by: Rodrigo Vivi
and pushing right now
> ---
>
. They shouldn't be seen on anything properly supported.
>
> 2) This seems all to be a layer below drm anyway and could even be used
> in places outside easy access to a drm pointer.
>
> So, it seems the benefit of using the subsystem-specific drm_WARN_ONCE
> doesn'
On Fri, Feb 04, 2022 at 06:45:51PM +0100, Andi Shyti wrote:
> Hi Dan,
>
> > There were two error paths in __cancel_reset() which return success
> > instead of a negative error code as expected.
> >
> > Fixes: 4e6835466771 ("drm/i915/selftests: Add a cancel request selftest
> > that triggers a re
/i915/gvt: Constify intel_gvt_sched_policy_ops
drm/i915/gvt: Constify gvt_mmio_block
drm/i915/gvt: Constify cmd_interrupt_events
drm/i915/gvt: Constify formats
drm/i915/gvt: Constify gtt_type_table_entry
drm/i915/gvt: Constify vgpu_types
Rodrigo Vivi (2):
Merge tag
On Thu, Dec 16, 2021 at 09:52:26AM +, Tvrtko Ursulin wrote:
>
>
> On 09/12/2021 12:01, Tejas Upadhyay wrote:
> > Most code paths does full reset with preparing all
> > engines for reset except below two :
> >
> > 1. Single engine reset needs to prepare engines for
> > reset based on its rese
On Tue, Aug 09, 2022 at 05:03:06PM -0700, Vinay Belgaumkar wrote:
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had disa
read for obtaining
> the correct efficient frequency for Gen9+.
>
> We see much better perf numbers with benchmarks like glmark2 with
> efficient frequency usage enabled as expected.
>
> BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/5468
>
> Cc: Rodrigo Vivi
Firs
w get these freq set up so we can inform PCODE.
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/driv
On Thu, Aug 25, 2022 at 06:23:15PM -0400, Rodrigo Vivi wrote:
> We need to inform PCODE of a desired ring frequencies so PCODE update
> the memory frequencies to us. rps->min_freq and rps->max_freq are the
> frequencies used in that request. However they were unset when SLPC wa
h): if SLPC is in use, let's pick the right
frequencies from the get_ia_constants instead of the fake init of
rps' min and max.
Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: # v5.15+
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
S
ix kernel-doc
drm/i915/gvt: Fix kernel-doc
drm/i915/gvt: Fix kernel-doc
Jouni Högander (1):
drm/i915/backlight: Disable pps power hook for aux based backlight
Julia Lawall (1):
drm/i915/gvt: fix typo in comment
Matthew Auld (1):
drm/i915/ttm: fix CCS handling
Rodrig
"drm/i915/guc: Make GuC log sizes runtime configurable")
> Signed-off-by: Joonas Lahtinen
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: John Harrison
> Cc: Alan Previn
> Reviewed-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> driver
Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_llc.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
b/drivers/gpu/drm/i915/gt/intel_llc.c
index 14fe6
Fix for intel_guc_slpc_set_min_freq() warn: inconsistent returns '&slpc->lock'.
Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency")
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: # v5.15+
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_llc.c | 19 ---
drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
.
Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency")
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 40 ++---
1 file changed, 20 inser
Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining
the "raw format"
Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: # v5.15+
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
5/ttm: fix CCS handling
Rodrigo Vivi (1):
Merge tag 'gvt-fixes-2022-08-22' of https://github.com/intel/gvt-linux
into drm-intel-fixes
Ville Syrjälä (1):
drm/i915: Skip wm/ddb readout for disabled pipes
Łukasz Bartosik (1):
drm/i915: fix null pointer dereference
drive
On Wed, Aug 31, 2022 at 03:17:26PM -0700, Dixit, Ashutosh wrote:
> On Wed, 31 Aug 2022 14:45:38 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > We need to inform PCODE of a desired ring frequencies so PCODE update
> > the memory frequencies to us. rps->m
sensitive.
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_rps.c | 3 ---
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers
Specially in GT reset case this could be triggered and try
to disable things that had never been enabled. Let's add
some protection here.
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/driver
Specially in GT reset case this could be triggered and try
to disable things that had never been enabled. Let's add
some protection here.
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_rps.c | 3 +++
1 file changed, 3 inser
SLPC has its own waiboost variables and lock mechanism.
No need for these extra stuff, in special no need for the
timer.
Cc: Ashutosh Dixit
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
On Fri, Sep 02, 2022 at 04:52:57PM -0700, Ashutosh Dixit wrote:
> From: Matt Roper
>
> We're going to introduce an additional intel_gt for MTL's media unit
> soon. Let's provide a bit more multi-GT initialization framework in
> preparation for that. The initialization will pull the list of GTs
On Fri, Sep 02, 2022 at 04:53:00PM -0700, Ashutosh Dixit wrote:
> From: Tilak Tangudu
>
> Add perf_limit_reasons in debugfs. Unlike the lower 16 perf_limit_reasons
> status bits, the upper 16 log bits remain set until cleared, thereby
> ensuring the throttling occurrence is not missed. The clear
SLPC has its own waiboost variables and lock mechanism.
No need for these extra stuff, in special no need for the
timer.
v2: At early stages we can't use uc's 'uses' function, but the
'wants' ones in order to make those decisions.
Cc: Ashutosh Dixit
Signed-off-
uC's SLPC is in use. (Rodrigo)
- Implement Workaround for eDP. (Ville)
- Fix has_flat_ccs selection for DG1. (Matt)
Matthew Auld (1):
drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
Rodrigo Vivi (1):
drm/i915
story here
to indicate what changed from the previous submission,
something like
v2: re-organizing the blocks to group gtt stuff.
that helps reviewers to know if their change requested was
addressed or not.
but anyways:
Reviewed-by: Rodrigo Vivi
> Signed-off-by: Mauro Carvalho Chehab
> -
les); do if [ "$(git grep $i
> Documentation/)" == "" ]; then echo "$i"; fi; done >aaa
>
> Add them to i915.rst as well.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Rodrigo Vivi
> ---
>
> To avoid mailbombing on a large number of peo
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