Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80818
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu
While sending DPI SHUTDOWN command, we cannot wait for FIFO empty as
pipes are not disabled at that time. In case of MIPI we disable port
first and send SHUTDOWN command while pipe is still running and FIFOs
will not be empty, causing spurious error log
Signed-off-by: Shobhit Kumar shobhit.ku
Ensure that the DSI packets for a particular sequence are completely
sent before going ahead in the enabling or disabling of the panel
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 8
drivers/gpu/drm/i915/intel_dsi_cmd.c | 16
.
Regards
Shobhit
Shobhit Kumar (3):
drm/i915: Add get_config implementation for DSI encoder
drm/i915: wait for all DSI FIFOs to be empty
drm/i915: Add support for Video Burst Mode for MIPI DSI
drivers/gpu/drm/i915/intel_bios.h | 3 +-
drivers/gpu/drm/i915/intel_display.c | 7
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_bios.h | 3 ++-
drivers/gpu/drm/i915/intel_dsi.c | 22 ++---
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 38
Call to vlv_crtc_clock_get is not needed for DSI and was causing dpio
read WARN dumps as well. Absence of -get_config was casuing othet WARN
dumps as well. With this the last of the known WARN dumps for DSI should
be fixed.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm
-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4
drivers/gpu/drm/i915/intel_dsi.c | 21 +++-
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 46
4 files changed
: Address review comments by Imre
- Proper masking of P1, M1 fields while computing divisors
- assert in case of bpp mismatch
- guard for divide by 0 while computing pclk
- Use ARRAY_SIZE instead of direct calculation
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu
module option and disable psr by default
drm/i915: Adding global I915_PARAM for PSR ENABLED.
drm/i915: Add functions to force psr exit
drm/i915: Hook PSR functionality
Shobhit Kumar (2):
drm: Added SDP and VSC structures for handling PSR for eDP
drm/i915: Read the EDP DPCD and PSR
/i915: Extract vlv_prepare_pll
gmch pll moved out of crtc mode_set callbacks into -enable hooks
Reviewer: Shobhit Kumar
I will be on vacation till next weekend, so will get to these after
that. Keep on my name if that is okay.
Regards
Shobhit
Thanks Damien for your review
On Thursday 15 May 2014 10:18 PM, Damien Lespiau wrote:
On Mon, Apr 14, 2014 at 11:18:27AM +0530, Shobhit Kumar wrote:
This driver makes use of the generic panel information from the VBT.
Panel information is classified into two - panel configuration and panel
On Monday 19 May 2014 07:53 PM, Damien Lespiau wrote:
On Mon, Apr 14, 2014 at 11:18:27AM +0530, Shobhit Kumar wrote:
+#define NS_MHZ_RATIO 100
[...]
+static bool generic_init(struct intel_dsi_device *dsi)
+{
[...]
+ /*
+* ui(s) = 1/f [f in hz]
+* ui(ns) = 10^9
of lp_to_hs switch and hs_to_lp switch while computing
hs_lp_switch_count
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 2 +
drivers
we can figure out what is the LFP type and initialize MIPI only if MIPI
is found.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c| 20 +++-
drivers/gpu/drm/i915/intel_display.c | 4 +++-
3
parse_mipi and intel_dsi_init insted of outside
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c | 14 ++
drivers/gpu/drm/i915/intel_bios.h | 4
drivers/gpu/drm/i915/intel_dsi.c | 4
4 files
Fix warnings introduced by the following commit -
commit 9c92da2c7c17eea79b6321b37592df0a002d24df
Author: Shobhit Kumar shobhit.ku...@intel.com
Date: Fri May 23 21:35:27 2014 +0530
drm/i915: Add support for Generic MIPI panel driver
Fixed all except the DRM logging which go beyond line 80
parse_mipi and intel_dsi_init insted of outside
v3: Make has_mipi as a bitfield as suggested
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c | 14
detection works across platforms
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_bios.h | 10 +-
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
2 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers
For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
during the DSI enable sequence
Causing WARN dump otherwise in dpio_reads
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions
For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
during the DSI enable sequence
Causing WARN dump otherwise in dpio_reads
v2: Add IS_CHERRYVIEW check as suggested by Ville
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj
On Wednesday 20 November 2013 07:09 AM, Shobhit Kumar wrote:
On Friday 15 November 2013 02:25 PM, Daniel Vetter wrote:
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Basically ULPS handling during enable/disable
On Friday 15 November 2013 01:57 PM, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase
to dsi_post_disable
- Replace hardcoding with AFE_LATCHOUT
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 110 +++
drivers/gpu/drm/i915/intel_dsi.h | 2 +
2
vijayakumar.balakrish...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 89 +---
1 file changed, 31 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915
implemntation based on VBT design enhancments to support multiple panels
v2: Mask away the port_bits before use
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 29 ++---
drivers/gpu
v2: Rebased on latest code
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Reviewed-by: Jani Nikulajani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1
details
- Move the new parameters out of this patch
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 9 -
drivers/gpu/drm/i915/intel_dsi.h | 5 +
2 files changed, 13
that we need not do
read/modify/write and
can just write the value
- Moved the sub-encoder hook in dsi_pre_enable and dsi_post_enable
- Minor coding tidbits are fixed
Regards
Shobhit
Shobhit Kumar (7):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use FLISDSI interface
DSI PLL will get configured during crtc_enable using -pre_pll_enable
and no need to do in -mode_set
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
vijayakumar.balakrish...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index
On Wednesday 11 December 2013 04:32 PM, Jani Nikula wrote:
On Tue, 10 Dec 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable
to dsi_post_disable
- Replace hardcoding with AFE_LATCHOUT
v4: Make intel_dsi_device_ready and intel_dsi_clear_device_ready static
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Wednesday 11 December 2013 06:36 PM, Daniel Vetter wrote:
On Wed, Dec 11, 2013 at 05:52:05PM +0530, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable sequences
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 5 +-
drivers/gpu/drm
-encoder driver in the existing design
to support
MIPI. Followup patches for this driver will come next.
Regards
Shobhit
Shobhit Kumar (2):
drm/i915: Update VBT data structures to have MIPI block enhancements
drm/i915: Add parsing support for new MIPI blocks in VBT
drivers/gpu/drm/i915
The parser extracts the config block(#52) and sequence(#53) data
and store in private data structures.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 175 --
drivers/gpu
Hi
On Thursday 13 February 2014 12:47 PM, Jani Nikula wrote:
On Thu, 13 Feb 2014, Shobhit Kumar shobhit.ku...@intel.com wrote:
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable
and memcpy
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 162 --
drivers/gpu/drm/i915/intel_bios.h | 34
3 files changed, 197 insertions(+), 5 deletions
structure improvements for cleaner code
- Adding units for the pps delays, all in ms
- change data structure to be more cleaner and simple
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 4 +-
drivers/gpu/drm/i915/intel_bios.h | 174
error detection during parsing MIPI sequence block
Regards
Shobhit
Shobhit Kumar (2):
drm/i915: Update VBT data structures to have MIPI block enhancements
drm/i915: Add parsing support for new MIPI blocks in VBT
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 164
structure improvements for cleaner code
- Adding units for the pps delays, all in ms
- change data structure to be more cleaner and simple
v3: Corrected the unit for pps delays as 100us
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index
Some MIPI panels might not have resolution which is a multiple of 64 like
1366x768. Enable this feature for such panels by default
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 7 ++-
1 file changed
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index dfcdb10
Shobhit Kumar (7):
drm/i915: Program Rcomp and band gap reset everytime we resume from power gate
drm/i915: Enable MIPI port before the plane and pipe enable
drm/i915: Disable DPOunit clock gating
drm/i915: Parameterize the Clockstop and escape_clk_div
drm/i915: Panel commands can be sent
In preparation for Generic driver
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 11 +--
drivers/gpu/drm/i915/intel_dsi.h | 4 +++-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git
As per the hw team's recommendation we need to enable the MIPI port
before enabling the plane and pipe. So call MIPI port enable in
pre_enable phase itself
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c
Otherwise, this can stall pipe. We also need DPLL REFA always
enabled
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff
Though HS mode also should work.
v2: Change parameter as bool hs as suggested by Jani
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 5 +++--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 4 ++--
drivers
and memcpy
v3: More strict check while parsing VBT
- Ensure that at anytime we do not go beyond sequence block
while parsing
- On unknown element fail the whole parsing
v4: Style changes and spell check mostly as suggested by Jani
Signed-off-by: Shobhit Kumar shobhit.ku
panel driver
are done.
Regards
Shobhit
Shobhit Kumar (4):
drm/i915: Correct MIPI operation mode as per expected values from VBT
drm/i915: MIPI init count programming as generic parameter
drm/i915: MIPI PPS delays added
drm/i915: Add support for Generic MIPI panel driver
drivers/gpu/drm/i915
review comments by Jani
- Move all of the things in driver c file from header
- Make all functions static
- Make use of video/mipi_display.c instead of redefining
- Null checks during sequence execution
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2795782..09b9318 100644
In VBT fields operation mode is 0 for Video mode and 1 for command mode.
This field will be directly used as is in generic panel driver. So
adjust accordingly.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_dsi.c | 4
Added as generic parameters which will be initialized in the panel
driver and are specific to panels.
Backlight delays have also kept as placeholders and will be used used
once we have MIPI backlight enabling support
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915
This cleans up the checkpatch errors for the merged commit -
commit d3b542fcfc72d7724585e3fd2c5e75351bc3df47
Author: Shobhit Kumar shobhit.ku...@intel.com
Date: Mon Apr 14 11:00:34 2014 +0530
drm/i915: Add parsing support for new MIPI blocks in VBT
Signed-off-by: Shobhit Kumar shobhit.ku
a panel sub-encoder driver is added. Proper detection or VBT is still
pending.
Regards
Shobhit
Shobhit Kumar (4):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use FLISDSI interface for band gap reset
drm/i915: Compute dsi_clk from pixel clock
drm/i915: Parameterize the MIPI
Also add new fields in intel_dsi to have all dphy related parameters.
These will be useful even when we go for pure generic MIPI design
Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |9
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dsi.c | 47
Has been tested on couple of panels now.
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Vijaykumar Balakrishnan vijayakumar.balakrish...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 11 ++
drivers
Minor modification to m_n_p calculations as well
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 75 --
1 file changed, 63 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b
On 10/21/2013 6:53 PM, Ville Syrjälä wrote:
On Mon, Oct 21, 2013 at 05:51:07PM +0530, Shobhit Kumar wrote:
Has been tested on couple of panels now.
While it's nice to get patches, I can't say I'm very happy about the
shape of this one.
The patch contains several changes in one patch
On 10/21/2013 6:58 PM, Ville Syrjälä wrote:
On Mon, Oct 21, 2013 at 05:51:06PM +0530, Shobhit Kumar wrote:
Minor modification to m_n_p calculations as well
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 75
On 10/21/2013 7:14 PM, Jani Nikula wrote:
On Mon, 21 Oct 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Minor modification to m_n_p calculations as well
That should probably be a separate patch, unless it's a requirement for
what the main subject of this patch is. The commit message does
On 10/21/2013 6:57 PM, Jani Nikula wrote:
Hi Shobhit -
On Mon, 21 Oct 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Also add new fields in intel_dsi to have all dphy related parameters.
These will be useful even when we go for pure generic MIPI design
I feel like we have a different
Hi Jani,
On 10/22/2013 05:23 PM, Jani Nikula wrote:
On Tue, 22 Oct 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
On 10/21/2013 6:57 PM, Jani Nikula wrote:
Hi Shobhit -
On Mon, 21 Oct 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
Also add new fields in intel_dsi to have all dphy
On 10/22/2013 04:19 PM, Ville Syrjälä wrote:
On Tue, Oct 22, 2013 at 02:36:18PM +0530, Shobhit Kumar wrote:
On 10/21/2013 6:53 PM, Ville Syrjälä wrote:
On Mon, Oct 21, 2013 at 05:51:07PM +0530, Shobhit Kumar wrote:
Has been tested on couple of panels now.
While it's nice to get patches, I
On 10/24/2013 01:54 PM, Jani Nikula wrote:
On Thu, 24 Oct 2013, Shobhit Kumar shobhit.ku...@intel.com wrote:
On 10/23/2013 07:52 PM, Jani Nikula wrote:
So I think let's keep trying to find the right abstractions to separate
the DSI core and the panel drivers, make it possible to support
. Will be added later.
- Other general code cleanup as suggested
- drm/i915: Use FLISDSI interface for band gap reset - has no changes and
is included
for completeness of the patch set
Regards
Shobhit
Shobhit Kumar (7):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use
Basically check for both +ive and -ive deviation from target clock and
pick the one with minimal error. If we get a direct match, break from
loop to acheive some optimization.
Signed-off-by: Vijayakumar Balakrishnan vijayakumar.balakrish...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku
details
- Move the new parameters out of this patch
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |9 -
drivers/gpu/drm/i915/intel_dsi.h |5 +
2 files changed, 13
the m-n-p changes into a separate patch
- Removed the parameter check for intel_dsi-dsi_clock_freq. This will be
bought back in if needed when appropriate panel drivers are done
Signed-off-by: Vijayakumar Balakrishnan vijayakumar.balakrish...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku
DSI PLL will get configured during crtc_enable using -pre_pll_enable
and no need to do in -mode_set
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Reviewed-by: Jani Nikulajani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915
implemntation based on VBT design enhancments to support multiple panels
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 27 +--
drivers/gpu/drm/i915/intel_dsi.h | 14 ++
2 files changed, 27 insertions(+), 14
- Moved parameter changes out into another patch
- Backlight enabling will be a new patch
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 11
drivers/gpu/drm/i915/intel_dsi.c
On 11/11/2013 02:20 PM, Thierry Reding wrote:
On Sat, Nov 09, 2013 at 11:28:16AM +0100, Daniel Vetter wrote:
On Sat, Nov 09, 2013 at 03:19:01PM +0530, Shobhit Kumar wrote:
Hi All -
These patches enhance the current support for MIPI DSI for Baytrail. They
continue on the sub-encoder design
On Wednesday 24 September 2014 02:31 PM, Daniel Vetter wrote:
On Wed, Sep 24, 2014 at 02:16:49PM +0530, Gaurav K Singh wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 35
On Thursday 25 September 2014 07:09 PM, Jani Nikula wrote:
On Thu, 25 Sep 2014, Shobhit Kumar shobhit.ku...@linux.intel.com wrote:
On Wednesday 24 September 2014 03:02 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
+ do {
Please never use
On Thursday 22 March 2012 02:32 AM, Daniel Vetter wrote:
On Wed, Mar 21, 2012 at 12:48:32PM -0700, Jesse Barnes wrote:
From: Shobhit Kumarshobhit.ku...@intel.com
HDMI register offsets are different in Valleyview. Add support for the
same.
Signed-off-by: Beeresh Gbeeres...@intel.com
In Haswell while disabling a pipe, we need to disable the DDI control as
well along with the PIPECONF. Otherwise we will hit assertions during crtc
disable
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |7 +++
1 files changed, 7 insertions
On 06/08/2012 07:20 PM, Eugeni Dodonov wrote:
On 06/08/2012 09:49 AM, Daniel Vetter wrote:
On Fri, Jun 08, 2012 at 11:44:23AM +0530, Shobhit Kumar wrote:
In Haswell while disabling a pipe, we need to disable the DDI control as
well along with the PIPECONF. Otherwise we will hit assertions
On 06/11/2012 12:38 PM, Daniel Vetter wrote:
On Mon, Jun 11, 2012 at 7:25 AM, Shobhit Kumarshobhit.ku...@intel.com wrote:
On 06/08/2012 07:20 PM, Eugeni Dodonov wrote:
On 06/08/2012 09:49 AM, Daniel Vetter wrote:
On Fri, Jun 08, 2012 at 11:44:23AM +0530, Shobhit Kumar wrote:
In Haswell
On 06/13/2012 01:35 PM, Daniel Vetter wrote:
On Tue, Jun 12, 2012 at 02:47:30PM -0700, Jesse Barnes wrote:
From: Shobhit Kumarshobhit.ku...@intel.com
VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This
in -
https://bugs.freedesktop.org/show_bug.cgi?id=85977
Requesting your comments to converge on best way of implementing this.
Regards
Shobhit
Shobhit Kumar (4):
drm/i915: Define a common data structure for Panel Info
drm/i915: Add a drm_panel over INTEL_SOC_PMIC
drm/i915/Kconfig: By default
This driver just add PANEL_ENABLE/DISABLE control using drm_panel
framework.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_drv.h| 3 +
drivers/gpu/drm/i915/intel_panel_pmic.c | 157
As of now this includes only PPS and BLC delays. New things can be added
as and when needed
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 11 +++
drivers/gpu/drm/i915/intel_dsi.h | 7 +--
drivers/gpu/drm/i915
This will be needed for enabling drm_panel driver over pmic
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 4e39ab3..3210dbb 100644
This initialize the drm_panel based on PMIC driver and uses drm_panel_*
for controlling the panel enable/disable states
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 20
drivers/gpu/drm/i915/intel_dsi.h | 6
Shobhit Kumar (4):
drm: Add support to find drm_panel by name
mfd: Add a new cell device for panel controlled by crystal cove pmic
drm/panel: Add new panel driver based on crystal cove pmic
drm/i915: Enable DSI panel enable/disable based on PMIC
drivers/gpu/drm/drm_panel.c
On BYT-T configuration, panel enable/disable signals are routed through
PMIC. Add a cell device for the same.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/mfd/intel_soc_pmic_crc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b
This allows for proper PPS during enable/disable of BYT-T platforms
where these signals are routed through PMIC. Needs DRM_PANEL to be
selected by default as well
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915
This driver provides support for the crystal_cove_panel cell device.
On BYT-T pmic has to be used to enable/disable panel.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/panel/Kconfig | 7 ++
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu
For scenarios where OF is not available, we can use panel identification by
name.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/drm_panel.c | 18 ++
include/drm/drm_panel.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm
On 01/16/2015 05:57 PM, Jani Nikula wrote:
Const is good for you. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Reviewed-By: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 17 +
1 file changed, 9 insertions
On 01/16/2015 05:57 PM, Jani Nikula wrote:
This series ports our DSI code over to the drm_panel and
mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the
end of the series, see commit message for patch 8 for details.
Patches 1-6 are prep work, fairly independent
While I
as native, nothing gets
changed, else mode_fixup function adjusts the mode accordingly keeping
timing as same and enabling scalar. Might not be useful in general, but
did find a use internally.
Either way
Reviewed-By: Shobhit Kumar shobhit.ku...@intel.com
return true;
}
@@ -269,9
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On 02/03/2015 06:35 PM, Thierry Reding wrote:
On Wed, Jan 21, 2015 at 04:48:11PM +0530, Shobhit Kumar wrote:
On BYT-T configuration, panel enable/disable signals are routed
through PMIC. Add a cell device for the same.
Signed-off-by: Shobhit
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Hash: SHA1
On 02/03/2015 06:46 PM, Thierry Reding wrote:
On Wed, Jan 21, 2015 at 04:48:12PM +0530, Shobhit Kumar wrote:
This driver provides support for the crystal_cove_panel cell
device. On BYT-T pmic has to be used to enable/disable panel.
v2: Addressed
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