On 07/07/2014 22:24, Daniel Vetter wrote:
On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
I don't think it's unreasonable to use a macro that checks a global
list for whether to apply a given WA. They'll be scattered all over,
but at least it'll be easy to see:
On 24/07/2014 13:33, Daniel Vetter wrote:
On Thu, Jul 24, 2014 at 11:43:11AM +0100, Siluvery, Arun wrote:
On 07/07/2014 22:24, Daniel Vetter wrote:
On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
I don't think it's unreasonable to use a macro that checks a global
On 28/07/2014 20:22, Daniel Vetter wrote:
On Mon, Jul 28, 2014 at 08:00:39PM +0300, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:46PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
The workarounds at the moment are initialized in
On 28/07/2014 18:00, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:46PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
The workarounds at the moment are initialized in init_clock_gating() but
they are lost during reset; In case of execlists
On 28/07/2014 18:26, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:45PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
This patch moves BDW workarounds from init_clock_gating() to render ring
init fn otherwise they are lost when gpu is reset.
On 08/08/2014 10:57, Chris Wilson wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the
On 08/08/2014 13:20, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the
On 08/08/2014 15:12, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which captures register
On 20/08/2014 16:37, Thomas Wood wrote:
On 20 August 2014 15:52, Arun Siluvery arun.siluv...@linux.intel.com wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test
On 22/08/2014 12:06, Mika Kuoppala wrote:
Ville Syrjälä ville.syrj...@linux.intel.com writes:
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are
On 25/08/2014 13:18, Ville Syrjälä wrote:
On Fri, Aug 22, 2014 at 08:39:11PM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to
On 26/08/2014 11:09, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 10:33:16AM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to
On 26/08/2014 11:34, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 11:16:29AM +0100, Siluvery, Arun wrote:
On 26/08/2014 11:09, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 10:33:16AM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating
On 26/08/2014 13:53, Daniel Vetter wrote:
On Fri, Aug 22, 2014 at 01:10:26PM +0100, Siluvery, Arun wrote:
On 22/08/2014 12:06, Mika Kuoppala wrote:
Ville Syrjälä ville.syrj...@linux.intel.com writes:
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw
On 26/08/2014 06:59, Chris Wilson wrote:
On Mon, Aug 25, 2014 at 10:39:39PM +0200, Daniel Vetter wrote:
On Wed, Aug 20, 2014 at 04:36:05PM +0100, Chris Wilson wrote:
On Wed, Aug 20, 2014 at 04:29:24PM +0100, Thomas Daniel wrote:
These two functions make no sense in an Logical Ring Context
On 26/08/2014 15:37, Ville Syrjälä wrote:
On Tue, Aug 26, 2014 at 02:44:50PM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to
On 27/08/2014 16:44, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state
On 27/08/2014 17:23, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:17:11PM +0100, Siluvery, Arun wrote:
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some
On 29/08/2014 11:16, Chris Wilson wrote:
On Fri, Aug 29, 2014 at 11:02:01AM +0100, Arun Siluvery wrote:
From: Garry Lancaster garry.lancas...@intel.com
libdrm includes a scheme where freed buffer objects (BOs)
are held in a cache. This allows incoming allocation requests to be
serviced by
On 30/08/2014 16:50, Damien Lespiau wrote:
Hi Arun,
I've compiled a few patches that I think solve some small-ish issues around
your wa_regs series. Could you please have a look at them and comment/give your
r-b tag if you judge appropriate?
On top of those patches, I'd love some comments on
On 30/08/2014 16:10, Damien Lespiau wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support
On 01/09/2014 10:08, Daniel Vetter wrote:
On Sun, Aug 31, 2014 at 08:32:55PM +0100, Siluvery, Arun wrote:
On 30/08/2014 16:50, Damien Lespiau wrote:
Hi Arun,
I've compiled a few patches that I think solve some small-ish issues around
your wa_regs series. Could you please have a look at them
On 30/08/2014 16:50, Damien Lespiau wrote:
Those debugfs files are prefixed by i915, the name of the kernel module,
presumably to make the difference with files exposed by core DRM.
Also, add a ',' at the end of the last entry. This is to ease the
conflict resolution when rebasing internal
On 30/08/2014 16:51, Damien Lespiau wrote:
We have CHV code that already makes the test obsolete. Besides, when
num_wa_regs is 0 (platforms not gathering that W/A data), we expose
something sensible already.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On 01/09/2014 15:06, Damien Lespiau wrote:
On Mon, Sep 01, 2014 at 02:28:53PM +0100, Arun Siluvery wrote:
Now w/a are organized in an array so we know exactly how many of them
are applied; use the same array while exporting data to debugfs and
remove the temporary array we currently have in
On 30/08/2014 22:46, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tests/gem_workarounds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 6826562..32156d2 100644
---
On 30/08/2014 16:50, Damien Lespiau wrote:
Hi Arun,
I've compiled a few patches that I think solve some small-ish issues around
your wa_regs series. Could you please have a look at them and comment/give your
r-b tag if you judge appropriate?
On top of those patches, I'd love some comments on
On 09/05/2014 22:18, Volkin, Bradley D wrote:
On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds support to have gem objects of variable size.
The size of the gem object obj-size is always constant
On 12/05/2014 18:02, Eric Anholt wrote:
arun.siluv...@linux.intel.com writes:
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds support to have gem objects of variable size.
The size of the gem object obj-size is always constant and this fact
is tightly coupled in the driver
Hi,
I am working on a feature to implement support for gem objects to have
variable size and realized a problem with the current implementation.
Please advice me how to handle this situation efficiently.
In this implementation the backing store of the object is replaced with
scratch pages
On 12/06/2014 08:26, Daniel Vetter wrote:
On Thu, Jun 12, 2014 at 12:49:47AM +0100, Siluvery, Arun wrote:
Hi,
I am working on a feature to implement support for gem objects to have
variable size and realized a problem with the current implementation.
Please advice me how to handle
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm wondering is how fitting the size parameter really is
when talking
On Tue, 2014-02-25 at 11:52 +, Arun Siluvery wrote:
Hi Everyone,
There is a requirement to defer physical mapping of higher level
mipmaps. Texture download and usage are separate and you cannot know
beforehand whether higher level mipmaps are required at the time of
allocation.
On 27/03/2014 22:23, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 03:28:26PM +, arun.siluv...@linux.intel.com wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patch series adds a new ioctl to resize a gem object.
I'm tired, but off the top of my head, I think you can do away
On 27/03/2014 22:23, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 03:28:26PM +, arun.siluv...@linux.intel.com wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patch series adds a new ioctl to resize a gem object.
I'm tired, but off the top of my head, I think you can do away
From: Siluvery, Arun arun.siluv...@intel.com
When a mapping is requested and if there is no space the mapping fails
and the region is not physically backed. This results in
signal 7(SIGBUS), code 2 (BUS_ADRERR) when it is actually accessed.
This patch handles this error, continues to wait
From: Siluvery, Arun arun.siluv...@intel.com
This patchset contains changes for Timeout detection and recovery (TDR) which
provides per-engine hang detection and recovery.
The current driver performs full gpu reset in case of a hang, TDR attempts to
only reset the engine that is hung and it falls
From: Siluvery, Arun arun.siluv...@intel.com
Instead of full GPU reset, where possible a single ring can be reset
individually. This patch adds functions to save ring's current state and
it will be restored with the same state after reset. The state comprises
of a set of ring specific registers
From: Siluvery, Arun arun.siluv...@intel.com
TDR provides per-engine hang detection and recovery. If an engine hangs then
the TDR will attempt to reset the engine and advance the command streamer to
the next instruction in the ring. If it was in the middle of processing a
batch buffer
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds changes to keep track of the number of the times TDR is
triggered and the results for each ring are made available through debugfs.
Signed-off-by: Siluvery, Arun arun.siluv...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 62
On Mon, 2013-11-11 at 16:31 +0100, Daniel Vetter wrote:
On Mon, Nov 11, 2013 at 02:58:31PM +, Siluvery, Arun wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patchset contains changes for Timeout detection and recovery (TDR)
which
provides per-engine hang detection
Hi All,
I am running a repetitive test on HSW with max available RAM limited to
1GB (max TOLUD is 1GB) and it fails with NULL pointer dereference in
execbuf ioctl.
Debug showed that the batch_obj-gtt_space which was valid becomes NULL
before it is dispatched. During debug I stored
On 07/10/2014 15:21, Mika Kuoppala wrote:
If we build the workaround list in ring initialization
and decouple it from the actual writing of values, we
gain the ability to decide where and how we want to apply
the values.
The advantage of this will become more clear when
we need to initialize
On 07/10/2014 15:21, Mika Kuoppala wrote:
As the workaround list has the value as initialization time
constant, we can do the simple checking on the go without
negleting igt.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++---
1
On 07/10/2014 15:21, Mika Kuoppala wrote:
If we build the workaround list in ring initialization
and decouple it from the actual writing of values, we
gain the ability to decide where and how we want to apply
the values.
The advantage of this will become more clear when
we need to initialize
On 22/10/2014 08:35, Ville Syrjälä wrote:
On Tue, Oct 21, 2014 at 07:40:35PM +0200, Daniel Vetter wrote:
On Tue, Oct 21, 2014 at 02:58:08PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, a simple cat to the debugfs file can make the machine use
much more
On 23/10/2014 14:41, Ville Syrjälä wrote:
On Thu, Oct 23, 2014 at 01:50:23PM +0100, Chris Wilson wrote:
On Thu, Oct 23, 2014 at 01:42:38PM +0100, Damien Lespiau wrote:
On Thu, Oct 23, 2014 at 02:21:02PM +0200, Daniel Vetter wrote:
On Wed, Oct 22, 2014 at 06:59:52PM +0100, Arun Siluvery wrote:
On 23/10/2014 16:51, Daniel Vetter wrote:
On Thu, Oct 23, 2014 at 04:29:30PM +0100, Arun Siluvery wrote:
We would want to apply some of the workarounds based on a condition to a
particular platform or Gen but we may not know all possible controlling
parameters in advance hence allow to define
On 28/10/2014 12:23, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
WaDisableInstructionShootdown:chv
WaForceEnableNonCoherent:chv
WaHdcDisableFetchWhenMasked:chv
WaDisableFenceDestinationToSLM:chv (pre-production)
On 28/10/2014 17:06, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 03:48:24PM +, Arun Siluvery wrote:
+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
On 28/10/2014 18:33, Arun Siluvery wrote:
The patches in this series adds two new workarounds for CHV and
removes pre-production ones.
Based on review comments from Ville, add/remove patches are split-up
which helps in reverting them if required.
The initial patch can be found at,
On 04/11/2014 19:23, Rodrigo Vivi wrote:
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
This patch is currently not relevant, rebased version is already sent to
the list for review.
https://patchwork.kernel.org/patch/5178771/
On 17/11/2014 15:54, Daniel, Thomas wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Arun Siluvery
Sent: Monday, November 17, 2014 3:48 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Free
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel
On 05/12/2014 17:36, Jani Nikula wrote:
On Fri, 05 Dec 2014, Siluvery, Arun arun.siluv...@linux.intel.com wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
For dual link MIPI Panels
Hi,
Could someone explain the significance of Null context/Golden state?
I understand we are initializing 3D state in this batch and we send this
at the beginning to start the HW with a known state but what are
implications of not doing this? what kind of issues we can expect if we
don't do
On 01/08/2014 17:34, Jesse Barnes wrote:
On Thu, 31 Jul 2014 12:08:20 -0700
Rodrigo Vivi rodrigo.v...@intel.com wrote:
WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle
v2: Improve variable names and fix allocated size.
Reviewed-by: Ben Widawsky
On 21/01/2015 17:37, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Wa4x4STCOptimizationDisable got only implemented for BDW, but according
to the w/a database CHV needs it too, so add it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On 02/03/2015 11:02, Arun Siluvery wrote:
Please ignore this one. I used message id of cover letter instead of v1
of this patch. Latest patches are sent in reply to their initial revisions.
regards
Arun
From: Namrta namrta.salo...@intel.com
This can be used to enable WA BB infrastructure
On 02/03/2015 10:10, Michel Thierry wrote:
On 25/02/15 17:54, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are
On 02/03/2015 17:43, Daniel Vetter wrote:
On Mon, Mar 02, 2015 at 11:07:20AM +, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround
On 05/06/2015 11:56, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are
On 05/06/2015 12:36, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 12:24:58PM +0100, Siluvery, Arun wrote:
ok, it is possible to do the allocation and setup in
logical_ring_init() itself. I wanted to group it with other wa which
are setup in init_context().
Phew, I had worried I had missed
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would simplify
vma/mm management. A trick might be to allocate the scratch page at the
start, then offset the lrc regs etc - that would then be consistent
amongst gen and be easy enough to extend
On 09/06/2015 16:27, Dave Gordon wrote:
On 05/06/15 11:34, Arun Siluvery wrote:
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid
On 02/06/2015 19:47, Dave Gordon wrote:
On 02/06/15 19:36, Siluvery, Arun wrote:
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would simplify
vma/mm management. A trick might be to allocate the scratch page at the
start, then offset the lrc
On 22/06/2015 16:36, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 06:50:36PM +0100, Chris Wilson wrote:
On Fri, Jun 19, 2015 at 06:37:10PM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before
On 22/06/2015 17:21, Ville Syrjälä wrote:
On Fri, Jun 19, 2015 at 06:37:15PM +0100, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
On 22/06/2015 16:41, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 07:07:01PM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are
On 22/06/2015 17:59, Siluvery, Arun wrote:
On 22/06/2015 17:21, Ville Syrjälä wrote:
On Fri, Jun 19, 2015 at 06:37:15PM +0100, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed
On 23/06/2015 15:36, Imre Deak wrote:
On ti, 2015-06-23 at 15:31 +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 05:26:13PM +0300, Imre Deak wrote:
On the GEN!=8 error path we call kmap_atomic() which returns in atomic
context and then lrc_destroy_wa_ctx_obj() which can be called only in
On 23/06/2015 17:01, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 06:58:42PM +0300, Imre Deak wrote:
On ti, 2015-06-23 at 16:44 +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 06:18:21PM +0300, Imre Deak wrote:
On ti, 2015-06-23 at 16:13 +0100, Siluvery, Arun wrote:
On 23/06/2015 15:36
On 15/06/2015 06:20, Daniel Vetter wrote:
On Wed, Jun 3, 2015 at 6:14 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
I was going to suggest removing the same thing from the
lrc_setup_hardware_status_page(), but after another look it seems we
sometimes call .init_hw() before the context
On 19/06/2015 19:09, Chris Wilson wrote:
On Fri, Jun 19, 2015 at 06:37:14PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with
On 19/06/2015 18:37, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
On 19/06/2015 10:27, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 06:33:24PM +0100, Arun Siluvery wrote:
Totally minor worries now.
+/**
+ * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
+ *
+ * @ring: only applicable for RCS
+ * @wa_ctx_batch: page in which WA are loaded
+
On 16/06/2015 11:39, Abdiel Janulgue wrote:
GEN8 and above uses Execlists by default instead of the legacy
ringbuffer for batch execution. This patch enables the resource
streamer bits when required.
Patch is based on the initial work by Minu Mathai minu.mat...@intel.com
This version also adds
On 15/06/2015 11:41, Daniel Vetter wrote:
On Thu, Jun 04, 2015 at 03:30:56PM +0100, Siluvery, Arun wrote:
On 02/06/2015 19:47, Dave Gordon wrote:
On 02/06/15 19:36, Siluvery, Arun wrote:
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would
On 12/06/2015 18:03, Dave Gordon wrote:
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM
On 15/06/2015 16:22, Daniel Vetter wrote:
On Fri, Jun 05, 2015 at 12:00:54PM +0100, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
+ /* FIXME: fill unused locations with NOOPs.
+* Replace these instructions with WA
+*/
+while
On 05/06/2015 15:48, Ville Syrjälä wrote:
On Fri, Jun 05, 2015 at 02:56:48PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Arun Siluvery
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break
On 17/06/2015 19:48, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset,
+ uint32_t *num_dwords)
+{
+
On 17/06/2015 21:21, Chris Wilson wrote:
On Wed, Jun 17, 2015 at 07:48:16PM +0100, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring
On 16/06/2015 21:33, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
+{
+ int ret;
+ struct drm_device *dev = ring-dev;
You only use it once, keeping it as a local seems
On 15/06/2015 18:29, Dave Gordon wrote:
On 15/06/15 15:10, Siluvery, Arun wrote:
On 12/06/2015 18:03, Dave Gordon wrote:
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer
On 29/05/2015 19:16, Chris Wilson wrote:
On Fri, May 29, 2015 at 07:03:19PM +0100, Arun Siluvery wrote:
This patch adds functions to setup WA batch buffers but they are not yet
enabled in this patch. Some of the WA are to be applied during context save
but before restore and some at the end of
On 03/07/2015 17:57, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote:
This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.
The WARN that we use to warn user if WA batch support is not available
for a particular Gen
On 06/07/2015 12:52, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA
On 12/08/2015 16:41, Dave Gordon wrote:
On 11/08/15 15:44, Arun Siluvery wrote:
From Gen9, Push constant instruction parsing behaviour varies
according to
whether set shader is enabled or not. If we want legacy behaviour then it
can be achieved by disabling set shader.
Bugzilla:
On 04/08/2015 00:21, Ben Widawsky wrote:
On Mon, Aug 03, 2015 at 08:24:57PM +0100, Arun Siluvery wrote:
This WA is implemented in init_context as well as WA batch init.
There are also some dependent bits need to be set in other registers
for this to be complete.
Cc: Ben Widawsky
On 04/08/2015 09:58, Mika Kuoppala wrote:
Ben Widawsky benjamin.widaw...@intel.com writes:
On Mon, Aug 03, 2015 at 08:24:56PM +0100, Arun Siluvery wrote:
Cc: Ben Widawsky benjamin.widaw...@intel.com
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Signed-off-by: Arun Siluvery
On 05/08/2015 15:45, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
This WA is implemented in init_context as well as WA batch init.
There are also some dependent bits need to be set in other registers
for this to be complete.
v2: behaviour of disable gather at set
On 07/08/2015 12:52, Daniel Vetter wrote:
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
Daniel Vetter dan...@ffwll.ch writes:
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out
On 11/08/2015 13:25, Mika Kuoppala wrote:
Don't set the size of bindless surface state on rendercopy.
And as of doing so, take into account the workaround for setting
the command size.
This was tried during hunting for
https://bugs.freedesktop.org/show_bug.cgi?id=89959. But no
impact was found.
On 11/08/2015 21:58, Timo Aaltonen wrote:
On 11.08.2015 17:44, Arun Siluvery wrote:
Patch1 fixes a simple compile error in Patch2
Patch2 fixes gpu hang observed with a subtest of gem_concurrent_blit.
Arun Siluvery (1):
drm/i915/gen9: Disable gather at set shader bit
Mika Kuoppala (1):
On 08/08/2015 06:35, Ben Widawsky wrote:
On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote:
This WA doesn't have a name. According to the spec, driver need to reset
disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this
On 06/08/2015 14:51, Mika Kuoppala wrote:
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery arun.siluv...@linux.intel.com
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
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