Latest VLV doesn't need to force the gfx clock
or something like that. We are still doing this to reduce Vnn after all.
Apart from that this matches my observations so:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
+ if (dev-pdev-revision = 0xd) {
+ valleyview_set_rps
i915_fbc_fc_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (INTEL_INFO(dev)-gen 5)
+ return -ENODEV;
Did you test this on ILK/SNB? Bspec says the bit is MBZ before IVB.
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On Sat, Jul 12, 2014 at 07:16:15PM +0530, Deepak S wrote:
On Saturday 28 June 2014 04:33 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV wants even rps opcodes so make sure the min/max/rpe values are also
even.
Signed-off-by: Ville
On Fri, Jul 25, 2014 at 02:55:00PM +0300, Imre Deak wrote:
On Sat, 2014-06-28 at 02:04 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power
On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
On Sat, 2014-06-28 at 02:04 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add the TX wells for port D. The Punit subsystem numbers are a total
guess at this time. Also I'm not sure
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+
3 files changed, 114 insertions(+), 59 deletions(-)
--
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On Mon, Jul 28, 2014 at 08:47:22PM +0200, Daniel Vetter wrote:
On Mon, Jul 28, 2014 at 06:29:41PM +0300, Ville Syrjälä wrote:
On Tue, Jul 15, 2014 at 05:43:37PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
v2: Adding creation of rotation_property
On Mon, Jul 28, 2014 at 07:56:27PM +0100, rafael.barba...@intel.com wrote:
From: Rafael Barbalho rafael.barba...@intel.com
According to the specifications bit 6 is actually valid in the stride
register.
Cc: Jesse Barnes jbar...@virtuousgeek.org
Cc: Ville Syrjälä ville.syrj
On Mon, Jul 28, 2014 at 09:46:33PM +0100, Siluvery, Arun wrote:
On 28/07/2014 18:00, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:46PM +0100, arun.siluv...@linux.intel.com
wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
The workarounds at the moment are initialized
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from that pipe.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
---
drivers/gpu/drm/i915/intel_panel.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
)
+ return;
I'd move the intel_dp assignment after the encoder type check to avoid
anyone thinking that they're allowed to dereference it before we're
sure about the type.
Apart from that both patches are:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
+
+ if (!edp_have_panel_vdd
On Thu, Jun 19, 2014 at 05:41:24PM -0700, Matt Roper wrote:
On Mon, May 26, 2014 at 05:26:47PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add a flag to drm_device which will cause the vblank code to bypass the
disable timer and always
On Tue, Jul 29, 2014 at 08:04:59PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:04:25 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV supports DP training pattern
On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:03:57 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Looks like the Punit is supposed to support the 400MHz cdclk directly on
chv, so we don't need
On Tue, Jul 29, 2014 at 08:06:57PM +0200, Daniel Vetter wrote:
On Mon, Jun 30, 2014 at 02:52:12PM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:04:28 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When switching from one pipe
On Tue, Jul 29, 2014 at 11:27:55PM +0100, Siluvery, Arun wrote:
On 28/07/2014 18:26, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:45PM +0100, arun.siluv...@linux.intel.com
wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
This patch moves BDW workarounds from
Subject: [Intel-gfx] [PATCH 31/40] drm/i916: Init chv workarounds at render
ring init
From: Ville Syrjälä ville.syrj...@linux.intel.com
My bsw is an unhappy camper if we delay the workaround init until
init_clock_gating(). Move a bunch of it to the render ring init.
FIXME: need to do
count first and wait for it (taking wraparound into account obviously).
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On Wed, Jul 30, 2014 at 05:43:10PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them
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believe some people working on just that.
We could even change the pixel format, except a check was added to
drm_mode_page_flip_ioctl() to prevent that, so I guess it was
deemed that the API isn't meant to allow that.
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On Thu, Jul 31, 2014 at 08:20:20AM -0700, Keith Packard wrote:
Ville Syrjälä ville.syrj...@linux.intel.com writes:
Now that we have mmio flips in the kernel we can start to relax that
restriction. That still needs a bit more work in the mmio flip code
but I believe some people working
-mm.aliasing_ppgtt = ppgtt;
+ }
+
return 0;
}
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On Thu, Jul 31, 2014 at 02:05:49PM -0300, Paulo Zanoni wrote:
2014-07-31 12:16 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Thu, Jul 31, 2014 at 12:08:09PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Zhenyu Wang zhen
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;
}
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On Thu, Jul 31, 2014 at 05:16:21PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add defines for all the watermark registers on modernish gmch platforms.
VLV has increased the number of bits
On Thu, Jul 31, 2014 at 05:57:33PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just
it at that point anyways.
Dave.
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:
- unchanged
v3:
- call edp sanitizing from the encoder reset handler (Daniel)
It happens a bit earlier than with the earlier attempt, but if
it works it works.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reported-and-tested-by: Jarkko Nikula jarkko.nik...@linux.intel.com
Signed-off
On Thu, Jul 31, 2014 at 03:08:29PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The DDL registers can hold 7bit numbers. Make the most of those seven
bits by adjusting the threshold where we switch
On Tue, Jul 29, 2014 at 09:57:09AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:04:05 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Just an attempt to frob these bits. Apparently we should not need to
touch them (apart from maybe
to be handled
somewhere a bit higher up.
return 0;
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On Mon, Aug 04, 2014 at 03:59:23PM +0530, Jindal, Sonika wrote:
On 7/31/2014 9:39 AM, Jindal, Sonika wrote:
On 7/29/2014 4:00 PM, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 12:40:29PM +0300, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 08:47:22PM +0200, Daniel Vetter wrote
@lists.freedesktop.org
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On Mon, Aug 04, 2014 at 10:10:50AM +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at 02:55:22PM +0300, Ville Syrjälä wrote:
On Thu, Jul 31, 2014 at 08:59:08PM +1000, Dave Airlie wrote:
On 31 July 2014 17:37, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jul 31, 2014 at 1:49 AM, Dave
://lists.freedesktop.org/mailman/listinfo/intel-gfx
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high resolutions. So tune it down to a
level where only developers can see it.
Also drop some of the end-user fluff.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Both patches make sense to me so:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915
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to me so:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
+
return true;
}
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,
cdclk);
}
+
static int i945_get_display_clock_speed(struct drm_device *dev)
{
return 40;
--
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. It is attached to different planes.
v2: Moving the creation of property back to i915 (Ville) and resetting
property
after disabling plane (Ville)
The series looks good to me.
For the patches not authored by me:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Sonika Jindal (3):
drm
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On Tue, Aug 05, 2014 at 08:57:07PM +0530, Vandana Kannan wrote:
On Aug-05-2014 6:39 PM, Ville Syrjälä wrote:
On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote:
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before
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On Wed, Aug 06, 2014 at 03:08:25PM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 02:49:58PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We should update the last in drm_update_vblank_count() to avoid applying
the diff more than once
On Wed, Aug 06, 2014 at 03:23:01PM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 02:49:52PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently it's possible that the following will happen:
1. drm_wait_vblank() calls
On Wed, Aug 06, 2014 at 03:30:17PM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 02:50:00PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We call drm_vblank_off() during crtc sanitation to make sure the
software and hardware states
WARN check for clock and pixel size
- Simplified bit masking
- Use cursor_base instead of reg read
v3: Changed to bitwise shorthand operator for plane_dl assignment.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
to avoid multiple if-else
- Changed bit masking to customary form
- Changed to bitwise shorthand operator for sprite_dl assignment
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Looks good.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h
://bugs.freedesktop.org/show_bug.cgi?id=76554
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers
unconditionally anyway
References: https://bugs.freedesktop.org/show_bug.cgi?id=76554
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Yeah looks sensible to me. So based on my gut feeling just from the
seeing the w/a name this is:
Reviewed-by: Ville
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drm_device *dev)
{
--
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Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915
new_delay an int in case we overflow the u8 in the intermediate
computations. new_delay will get clamped at the end anyway. (Ville)
Cc: Deepak S deepa...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Ville
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On Mon, Aug 11, 2014 at 11:29:21AM -0300, Paulo Zanoni wrote:
2014-08-11 8:32 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Wed, Aug 06, 2014 at 06:26:01PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use
On Mon, Aug 11, 2014 at 02:57:44PM -0300, Paulo Zanoni wrote:
2014-08-11 11:42 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Mon, Aug 11, 2014 at 11:29:21AM -0300, Paulo Zanoni wrote:
2014-08-11 8:32 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Wed, Aug 06, 2014
:
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Pushed to -fixes, thanks for the patch and review.
BR,
Jani.
On Tue, Jun 24, 2014 at 3:59 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
BDW signals the flip done interrupt
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isn't enough since we don't clear that
when we disable the crtcs for system suspend. Maybe we should do that
instead?
Anyway this check seems fine to me regardless of how we deal with
connectors_active during system suspend, so:
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
*);
int crtc_mask;
enum hpd_pin hpd_pin;
};
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On Tue, Aug 12, 2014 at 03:36:01PM +0300, Imre Deak wrote:
On Tue, 2014-08-12 at 15:13 +0300, Ville Syrjälä wrote:
On Mon, Aug 11, 2014 at 09:54:15PM +0300, Imre Deak wrote:
Make sure these work handlers don't run after we system suspend or
unload the driver. Note that we don't cancel
On Tue, Aug 12, 2014 at 11:24:11AM +0300, Ville Syrjälä wrote:
On Mon, Aug 11, 2014 at 04:44:23PM -0300, Paulo Zanoni wrote:
2014-06-30 7:10 GMT-03:00 Jani Nikula jani.nik...@linux.intel.com:
On Thu, 26 Jun 2014, Rodrigo Vivi rodrigo.v...@gmail.com wrote:
I'm sure this might affect Wayne
The series seems fine to me.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
for the rest as well.
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On Thu, Aug 14, 2014 at 05:26:27PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 06:06:58PM +0300, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 04:42:01PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 02:54:27PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g
On Thu, Aug 14, 2014 at 06:07:44PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 5:45 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
My quick grep audit tells me the viewport check and
drm_primary_helper_update() are the only places in the core that care.
The latter is rather
On Thu, Aug 14, 2014 at 07:36:13PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 6:45 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Thu, Aug 14, 2014 at 06:07:44PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 5:45 PM, Ville Syrjälä
ville.syrj...@linux.intel.com
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On Thu, Aug 14, 2014 at 08:33:23PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 7:58 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
Sure but the user can supply any mode, doesn't have to be on any list.
And the only sane rule for the frobbing would be that you can (slightly
On Fri, Aug 15, 2014 at 01:21:52AM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Thomas asked me to repost my 830/ns2501 patches. So here they are. I added
a few more patches (trickle feed and unused ring init) to fix some post-resume
issues
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On Fri, Aug 15, 2014 at 01:47:18PM -0300, Paulo Zanoni wrote:
2014-08-15 5:39 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use
the problem or if bisecting
is the only reasonable option.
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On Mon, Aug 18, 2014 at 07:31:58AM +0200, Juergen Gross wrote:
On 08/15/2014 12:21 PM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter daniel.vet...@ffwll.ch
-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3f8e037..15fe3eb 100644
--- a/drivers/gpu
On Tue, Aug 19, 2014 at 10:36:52AM +0300, Jani Nikula wrote:
On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If we force vdd off warn if someone is still using it. With this
change the delayed vdd off work needs to check
On Tue, Aug 19, 2014 at 11:08:33AM +0300, Jani Nikula wrote:
On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
While wrestling with the VLV/CHV panel power sequencer I noticed the locking
in our edp vdd code was rather broken
On Tue, Aug 19, 2014 at 10:30:25AM +0300, Jani Nikula wrote:
On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Less pointless indentation is always nice. There will be a bit more
code in this function once the power sequencer
On Tue, Aug 19, 2014 at 10:33:15AM +0300, Jani Nikula wrote:
On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
On VLV/CHV the panel power sequencer may need to be kicked a bit to
lock onto the new port, and that needs to happen
]);
GT_RENDER_USER_INTERRUPT GEN8_VECS_IRQ_SHIFT |
GT_CONTEXT_SWITCH_INTERRUPT GEN8_VECS_IRQ_SHIFT
};
--
1.9.1
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last_backlight_off;
struct notifier_block edp_notifier;
--
1.8.3.2
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, it would
be ideal to augment WA values from during the setup state as opposed to
using a tool but that would be a follow up patch.
I'd still prefer just emitting the LRIs from code rather tha mucking
about with null batch. Less hoops to jump through when adding a new w/a.
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Widawsky benjamin.widaw...@intel.com
Date: Sat Nov 2 21:07:09 2013 -0700
drm/i915/bdw: Implement interrupt changes
v2: Kill the loop and init GT interrupts (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
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On Thu, Aug 21, 2014 at 05:14:35PM +0530, Jindal, Sonika wrote:
On 8/21/2014 2:03 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 11:45:41AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Primary planes support 180 degree rotation. Expose
On Thu, Aug 21, 2014 at 03:06:25PM +0300, Jani Nikula wrote:
Use the correct mask for the unlock bits. In theory this could have lead
to incorrect asserts but this is unlikely in practise.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj
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