On Mon, May 06, 2019 at 06:44:43PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
> On 5/6/2019 6:41 PM, Ville Syrjälä wrote:
> > On Mon, May 06, 2019 at 06:25:19PM +0530, Sharma, Shashank wrote:
> >> On 5/6/2019 5:55 PM, Ville Syrjälä wrote:
> >&
+13,6 @@
> > int intel_color_check(struct intel_crtc_state *crtc_state);
> > void intel_color_commit(const struct intel_crtc_state *crtc_state);
> > void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
> > +void intel_color_read_luts(struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_COLOR_H__ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
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fastboot_enabled(struct drm_i915_private
> *dev_priv)
> PIPE_CONF_CHECK_X(csc_mode);
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
> +
> + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut,
> pipe_config-&
On Tue, Apr 30, 2019 at 02:12:39PM -0700, Aditya Swarup wrote:
> On Tue, Apr 30, 2019 at 06:05:18PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote:
> > > From: Ville Syrjälä
> > >
> > > There is a bug in hdm
the relationship even more explicit.
>
> Reviewed-by: Clint Taylor
>
> -Clint
>
>
> On 5/3/19 12:08 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The pcode mailbox has two data registers. So far we've only ever used
> > the one, but that&
On Mon, May 06, 2019 at 03:38:43PM -0700, Clinton Taylor wrote:
>
> On 5/3/19 12:08 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL has so many planes that it can easily exceed the maximum
> > effective memory bandwidth of the system. We must therefore
> +};
> >> +
> >> +/* HDR Metadata as per 861.G spec */
> >> +struct hdr_static_metadata {
> >> + __u8 eotf;
> >> + __u8 metadata_type;
> >> + __u16 max_cll;
> >> + __u16 max_fall;
> >> + __u16 min_cll;
> >> +};
>
dmi_sink_is_deep_color() - no longer needed as checking pipe_bpp > 24
> > takes care of the deep color mode scenario.
> >
> > Separate patch for fixing switch from 12 bit to 10 bit deep color
> > mode.
> >
> > Co-developed-by: Aditya Swarup
On Tue, May 07, 2019 at 12:27:07AM +0530, Sharma, Swati2 wrote:
> On 07-May-19 12:03 AM, Ville Syrjälä wrote:
>
> > On Sat, May 04, 2019 at 10:41:40PM +0530, Swati Sharma wrote:
> >> v3: Rebase
> >> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal
On Tue, Apr 09, 2019 at 10:14:42PM +0530, Uma Shankar wrote:
> This patch enables modeset whenever HDR metadata
> needs to be updated to sink.
>
> v2: Addressed Shashank's review comments.
>
> v3: Added Shashank's RB.
>
> Signed-off-by: Ville Syrjälä
> Sign
r_output_metadata {
> + __u32 metadata_type;
> + union {
> + struct hdr_metadata_infoframe hdmi_metadata_type1;
> + };
> +};
> +
> +/* HDR Metadata as per 861.G spec */
> +struct hdr_static_metadata {
> + __u8 eotf;
> + __u8 metadata_type;
> + __u16 max_cll;
> + __u16 max_fall;
> + __u16 min_cll;
> +};
> +
> +struct hdr_sink_metadata {
> + __u32 metadata_type;
> + union {
> + struct hdr_static_metadata hdmi_type1;
> + };
> +};
> +
> #define DRM_MODE_PAGE_FLIP_EVENT 0x01
> #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
> #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
> --
> 1.9.1
>
> ___
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On Tue, May 07, 2019 at 01:25:42PM +0300, Ville Syrjälä wrote:
> On Tue, May 07, 2019 at 09:03:45AM +, Shankar, Uma wrote:
> >
> >
> > >-Original Message-
> > >From: Jonas Karlman [mailto:jo...@kwiboo.se]
> > >Sent: Saturday, May 4, 2019
0x0,
> + 0x8A68, 0x7918, 0xAC00,
> + 0x0, 0x7918, 0x6890,
> + },
> };
> const u16 *csc;
>
> --
> 2.17.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@
w value before ilk_lut_12p4_udw
> - Change the comments in description of fine and coarse segments,
> and try to make more sense.
> - use 8 * 128 instead of 1024
> - add 1 entry in LUT for GCMAX
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Cc: Daniel Vetter
&
On Tue, May 07, 2019 at 02:35:15PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> >Of Ville
> >Syrjälä
> >Sent: Tuesday, May 7, 2019 7:37 PM
>
On Thu, Apr 25, 2019 at 07:29:05PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On HSW the pipe A panel fitter lives inside the display power well,
> and the input MUX for the EDP transcoder needs to be configured
> appropriately to route the data through the power
sted color mode is 10 bit through max bpc property)
>
> Comparing pipe_bpp with bpc * 3 takes care of this condition where
> requested max bpc is 10 bit, so hdmi_deep_color_possible with 12 bit
> returns false when requested max bpc is 10.(Ville)
>
> v2:Add suggested by Ville
r = is_planar_yuv_format(pixel_format) ? 0 : 1;
> + tmpclk1 = (1 << 16) * mult - remainder;
> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> max_scale = min(tmpclk1, tmpclk2);
>
> --
> 2.17.1
>
+ u8 DB18; /* Content Type */
> + u8 DB19_31[13]; /* Reserved */
> +} __packed;
Isn't this the same thing we have for edp already? Just rename the edp
struct and add the missing stuff?
> +
> #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
> #define E
ivers/gpu/drm/i915/intel_drv.h
> @@ -1576,6 +1576,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> enum link_m_n_set m_n);
> +void intel_dp_ycb
.DB17.
> Add a setting of dynamic range bit to vsc_sdp.DB17.
> Change Content Type bit to "Graphics" from "Not defined".
> Change a dividing of pipe_bpp to muliplying to constant values on a
> switch-case statement.
>
> Cc: Ville Syrjälä
> Signed-off-by:
On Wed, May 08, 2019 at 12:46:09PM +0200, Maarten Lankhorst wrote:
> Op 25-04-2019 om 18:29 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > On HSW the pipe A panel fitter lives inside the display power well,
> > and the input MUX for the EDP transc
macro
> - missing shift entry in blue
> - pick correct entry for GCMAX
> - Added Ville's R-B
> Note: Tested and confirmed the programming sequence of odd/even
> registers in the HW. The correct sequence should be:
> ilk_lut_12p4_udw
> ilk_lut_12p4_ldw
On Thu, May 09, 2019 at 02:54:19PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, May 7, 2019 9:08 PM
> >To: Shankar, Uma
> >Cc: Sharma, Shashank ; intel-
> >
On Thu, May 09, 2019 at 03:08:40PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Thursday, May 9, 2019 8:28 PM
> >To: Shankar, Uma
> >Cc: Sharma, Shashank ; intel-
> >
IN_DISPLAY_CORE);
> +
> mutex_lock(&psr->lock);
>
> if (!psr->enabled || psr->dp != intel_dp)
> @@ -1294,6 +1297,9 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
> exit:
> mutex_unlock(&psr->lock);
> +
> + intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
> + wakeref);
> }
>
> bool intel_psr_enabled(struct intel_dp *intel_dp)
> --
> 2.17.1
--
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\
> + BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |\
> BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> @@ -2429,6 +2432,7 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> BIT_ULL(POWER_DOMAIN_INIT))
>
> #define CHV_DISPLAY_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |\
> BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> --
> 2.17.1
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didn't pay all that much attention to those patches.
Patches 5-11 lgtm.
Reviewed-by: Ville Syrjälä
>
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> drivers/gpu/drm/i915/intel_display.c| 2 +-
> drivers/gpu/drm/i915/intel_display.h| 2 +-
> drivers/
I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
> + PREOFF_YUV_TO_RGB_ME);
I think this could probably be a separate patch since it affects
BT.601/BT.709 as well. Oh, and the matrix coefficients for 601/709 seem
similarly off as what you had in this patch or
- 0x0, 0x7918, 0x6870,
> + 0x7E58, 0x7950, 0x0,
> + 0x8888, 0x7950, 0xADA8,
> + 0x0, 0x7950, 0x6870,
> },
> /*
>* BT.2020 Limited range YCbCr -> full range RGB
> --
> 1.9.1
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On Fri, May 10, 2019 at 05:42:09PM -0700, Matt Roper wrote:
> On Fri, May 03, 2019 at 10:08:31PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL has so many planes that it can easily exceed the maximum
> > effective memory bandwidth of the system. We mu
On Wed, May 08, 2019 at 09:05:06PM +, Sripada, Radhakrishna wrote:
> On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL has so many planes that it can easily exceed the maximum
> > effective memory bandwidth of the syst
m_connector *connector, const u8 *db)
> {
> @@ -4461,6 +4511,8 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> drm_parse_y420cmdb_bitmap(connector, db);
> if (cea_db_is_vcdb(db))
> drm_parse_vcdb(conn
here for consistency.
> + if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config,
> + conn_state)) {
> + DRM_DEBUG_KMS("bad DRM infoframe\n");
> + return -EINVAL;
> + }
> + }
> +
> return 0;
> }
>
> --
> 1.9.1
>
> ___
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_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> --
> 1.9.1
>
> ___
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On Thu, May 09, 2019 at 12:08:48AM +0530, Uma Shankar wrote:
> From: Ville Syrjälä
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> v3: Addressed Shashank's review com
On Thu, May 09, 2019 at 12:08:52AM +0530, Uma Shankar wrote:
> Added unpack function for DRM infoframe for dynamic
> range and mastering infoframe readout.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> driv
intel_read_infoframe(encoder, pipe_config,
> + HDMI_INFOFRAME_TYPE_DRM,
> + &pipe_config->infoframes.drm);
Dead code.
> }
>
> static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
&
On Tue, May 14, 2019 at 09:49:03AM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, May 14, 2019 12:49 AM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.
Rebase
> >
> > v6: Fixed checkpatch warnings with --strict option. Addressed
> > Shashank's review comments and added his RB.
> >
> > v7: Addressed Brian Starkey's review comments. Merged 2 patches
> > into one.
> >
> >
x b8a3ce6..057e8ac 100644
> --- a/drivers/gpu/drm/i915/intel_color.h
> +++ b/drivers/gpu/drm/i915/intel_color.h
> @@ -13,5 +13,6 @@
> int intel_color_check(struct intel_crtc_state *crtc_state);
> void intel_color_commit(const struct intel_crtc_state *crtc_state);
> void intel_c
\n"); \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_QUIRK(quirk) \
> ((current_config->quirks | pipe_config->quirks) & (quirk))
>
> @@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private
> *dev_priv)
> PIPE_CONF_CHECK_X(csc_mode);
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
> +
> + intel_color_get_bit_precision(pipe_config, &bp_gamma);
> + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
> }
>
> PIPE_CONF_CHECK_BOOL(double_wide);
> @@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private
> *dev_priv)
> #undef PIPE_CONF_CHECK_FLAGS
> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> #undef PIPE_CONF_QUIRK
> +#undef PIPE_CONF_CHECK_COLOR_LUT
>
> return ret;
> }
> --
> 1.9.1
--
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lude/uapi/drm/drm_mode.h
> @@ -630,6 +630,29 @@ struct drm_color_lut {
> __u16 reserved;
> };
>
> +/* HDR Metadata Infoframe as per 861.G spec */
> +struct hdr_metadata_infoframe {
> + __u8 eotf;
> + __u8 metadata_type;
> + struct {
> + __u16 x, y;
> + } display_primaries[3];
> + struct {
> + __u16 x, y;
> + } white_point;
> + __u16 max_display_mastering_luminance;
> + __u16 min_display_mastering_luminance;
> + __u16 max_cll;
> + __u16 max_fall;
> +};
> +
> +struct hdr_output_metadata {
> + __u32 metadata_type;
> + union {
> + struct hdr_metadata_infoframe hdmi_metadata_type1;
> + };
> +};
> +
> #define DRM_MODE_PAGE_FLIP_EVENT 0x01
> #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
> #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
> --
> 1.9.1
--
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ents. Merged 2 patches
> into one.
>
> v8: Addressed Jonas Karlman review comments.
>
> v9: Addressed Jonas Karlman review comments.
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Shashank Sharma
> ---
> drivers/gpu/drm/drm_edid.c |
On Tue, May 14, 2019 at 11:06:31PM +0530, Uma Shankar wrote:
> This patch enables modeset whenever HDR metadata
> needs to be updated to sink.
>
> v2: Addressed Shashank's review comments.
>
> v3: Added Shashank's RB.
>
> v4: Addressed Ville's review comm
NFOFRAME(avi);
> PIPE_CONF_CHECK_INFOFRAME(spd);
> PIPE_CONF_CHECK_INFOFRAME(hdmi);
> + PIPE_CONF_CHECK_INFOFRAME(drm);
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> --
> 1.9.1
--
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S][3] -> [FAIL][4]
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6081/shard-
> >iclb6/igt@kms_prop_b...@invalid-set-prop-any.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13017/shard-
> >iclb5/igt@kms_prop_b...@invalid-set-prop-any
id
> drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
> {
> @@ -4461,6 +4508,8 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> drm_parse_y420cmdb_bitmap(connector, db);
> if (cea_db_is_vcdb(db))
On Wed, May 15, 2019 at 07:33:10PM +, Jonas Karlman wrote:
> On 2019-05-15 21:10, Ville Syrjälä wrote:
> > On Tue, May 14, 2019 at 11:06:23PM +0530, Uma Shankar wrote:
> >> This patch adds a blob property to get HDR metadata
> >> information from userspace. This w
On Thu, May 16, 2019 at 10:54:14AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> >Of Ville
> >Syrjälä
> >Sent: Thursday, May 16, 2019 12:57 AM
> >To: Shank
On Thu, May 16, 2019 at 07:28:43AM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Thursday, May 16, 2019 1:02 AM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freede
> Why are you the first to suggest this, this is awesome!
Can't quite tell if that's irony or not. Anyways, this has been
suggested before but no volunteers stepped forward.
> drm_atomic_state is indeed not a state, but a transaction representing
> how we go from the old to the new state.
On a semi-related topic, I've occasionally pondered about moving
mode_changed & co. from the obj states to the top level
state/transaction (maybe stored as a bitmask). But that would
definitely not be a trivial sed job.
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GEN8+ GPUs. The second CRC is invalid even for BYT which
> >> is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.
> >>
> >> Cc: Jani Nikula
> >> Cc: Tomi Sarvela
> >> Cc: Petri Latvala
> >> Cc: Ville Syrjälä
> >> Cc: Maarten
On Thu, May 16, 2019 at 01:18:15PM +, Shankar, Uma wrote:
>
>
> >>
> >> >-Original Message-
> >> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >> >Sent: Thursday, May 16, 2019 1:02 AM
> >> >To: Shankar, U
On Fri, May 17, 2019 at 01:17:05PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Peres, Martin
> >Sent: Friday, May 17, 2019 6:39 PM
> >To: Ville Syrjälä ; Shankar, Uma
> >
> >Cc: intel-gfx@lists.freedesktop.org
> >Subject:
On Thu, May 16, 2019 at 09:54:55PM +0200, Mario Kleiner wrote:
> On Fri, Apr 26, 2019 at 6:32 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
> > the running with > 8bpc.
> >
On Thu, May 16, 2019 at 07:40:13PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> v3: Addressed Shashank's review com
HDMI_INFOFRAME_TYPE_DRM,
> + &crtc_state->infoframes.drm);
> }
>
> void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
> @@ -2386,6 +2425,11 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> re
>
> if (!HAS_GMCH(dev_priv))
> drm_connector_attach_max_bpc_property(connector, 8, 12);
> --
> 1.9.1
--
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> bug
> > > > > > we have no way to verify that. :/
> > > > >
> > > > > The problem is, if it works with rc6 disabled, it doesn't prove
> > > > > it's
> > > > > an
> > > > > rc6 bug eith
as to make igt i2c subtest
> patch [1] work on all connectors.
>
> [1]: https://patchwork.freedesktop.org/series/60357/
>
> Signed-off-by: Oleg Vasilev
> Cc: Arkadiusz Hiler
> Cc: Imre Deak
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> ---
> drivers/gpu/drm/i915/int
On Fri, May 17, 2019 at 09:44:46AM -0700, Rodrigo Vivi wrote:
> On Fri, May 17, 2019 at 07:34:23PM +0300, Ville Syrjälä wrote:
> > On Fri, May 17, 2019 at 09:17:39AM -0700, Rodrigo Vivi wrote:
> > > On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote:
> > >
On Thu, May 16, 2019 at 06:33:21PM +0200, Maarten Lankhorst wrote:
> Op 09-05-2019 om 14:21 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > With gtt remapping in place we can use arbitrarily large
> > framebuffers. Let's bump the limits to 16kx16k on ge
and cannot support that level, it shall set the
pre-emphasis level to the next highest level, 6dB."
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>
15_pm_...@module-reload.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13064/fi-icl-y/igt@i915_pm_...@module-reload.html
Sigh. Looks like pcode on this icl-y doesn't support the new commands
to retrieve the memory subsystem information. BIOS update maybe could
fix that?
-
tach HDR metadata property to connector
> drm/i915: Write HDR infoframe and send to panel
> drm/i915:Enabled Modeset when HDR Infoframe changes
> drm/i915: Added DRM Infoframe handling for BYT/CHT
> video/hdmi: Add Unpack function for DRM infoframe
> drm/i915: Add state reado
}
> - } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_disable_dc9(dev_priv);
> - bxt_display_core_init(dev_priv, true);
> - if (dev_priv->csr.dmc_payload &&
> - (dev_priv->csr.allowed_dc_mask &
On Tue, May 21, 2019 at 07:12:28PM +0530, Sharma, Swati2 wrote:
> On 14-May-19 9:40 PM, Ville Syrjälä wrote:
>
> > On Tue, May 14, 2019 at 03:13:21PM +0530, Swati Sharma wrote:
> >> v3: -Rebase
> >> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal
timeout signaling works
> properly and so there won't be any ERRORs/WARNs emitted.
>
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=110718
> Cc: Ville Syrjälä
> Reported-by: Ville Syrjälä
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
>
On Fri, May 24, 2019 at 06:36:14PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algo
a generic property based API that never really went anywhere. It's
a rather difficult problem making this generic as each hardware has
its own peculiar way of specifying colorkeying. The main problem
with the custom ioctl is that it's not atomic with other screen
updates.
gt; doesn't allow the switch back to 8 bit color.
Why not? Table 6-1 in HDMI 1.4a spec clearly lists 8bpc as a
valid setting for GCP.
>
> Signed-off-by: Clinton Taylor
> Signed-off-by: Aditya Swarup
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> C
On Tue, Apr 02, 2019 at 09:25:58AM -0700, Clinton Taylor wrote:
>
> On 4/2/19 8:54 AM, Clinton Taylor wrote:
> >
> > On 4/2/19 5:53 AM, Ville Syrjälä wrote:
> >> On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
> >>> From: Clinton Taylor
&g
l_hdmi_compute_config()
Nope. Please drop those hunsk.
>
> Ideally, hdmi_deep_color_possible() should be called only
> once to determine whether it is possible to set 10 or 12 bit
> deep color mode and adjust the desired bpp based on pipe_bpp
> instead of hard coding the values.
>
>
en a single lane count + rate combo works.
>
> Cc: Clint Taylor
> Cc: Ville Syrjälä
> Tested-by: Albert Astals Cid
> Tested-by: Emanuele Panigati
> Tested-by: Ralgor
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
> Signed-off-by: Manasi Navare
> ---
ma ; Roper, Matthew D
> >
> >Subject: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
> >
> >From: Ville Syrjälä
> >
> >Using the split gamma mode when we don't have to has the annoying
> >requirement of
> >loading a li
On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > > For certain eDP 1.4 panels, we need to use max lane count for the
> > &g
On Wed, Apr 03, 2019 at 12:07:35PM -0700, Manasi Navare wrote:
> On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> > > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > > &
ma ; Roper, Matthew D
> >
> >Subject: [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff
> >
> >From: Ville Syrjälä
> >
> >Rebased due to Uma's EXT_GC_MAX fix, and I added Matt's proposed behavioural
> >change (expose 1024 entry LUTs in split gamma m
On Thu, Apr 04, 2019 at 08:33:57AM +0100, Chris Wilson wrote:
> drivers/gpu/drm/i915/intel_cdclk.c:2116: warning: Function parameter or
> member 'dev_priv' not described in 'intel_cdclk_needs_cd2x_update'
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
tmp & 0x) + 1;
> + hsync_end = ((tmp >> 16) & 0x) + 1;
> + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
> + if (intel_dsi->dual_link) {
> + hsync_start *= 2;
> +
change values for pipe_bpp based on bw_constrained flag.
>
> v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
>
> Signed-off-by: Clinton Taylor
> Signed-off-by: Aditya Swarup
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Cc: Manasi Navare
> ---
change values for pipe_bpp based on bw_constrained flag.
>
> v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
>
> Signed-off-by: Clinton Taylor
> Signed-off-by: Aditya Swarup
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Cc: Manasi Navare
> ---
got flipped the wrong way around for some reason.
> skl_wa_827(dev_priv, crtc->pipe, true);
> - }
> +
> + /* Wa_2006604312:icl */
> + if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> + !needs_scalerclk_wa(dev_priv, pipe_config))
An
rm/i915/icl: Add support for multi segmented gamma mode
> drm/i915: Add gamma mode caps property
> drm/i915: Attach gamma mode property
>
> Ville Syrjälä (2):
> drm: Add gamma mode caps property
> drm/i915: Define color lut range structure
>
> drivers/gpu/drm/drm_a
led.
Do we have any igts that excecise plane enable/disable vs. FBC?
> intel_fbc_disable(intel_crtc);
> intel_disable_shared_dpll(old_intel_crtc_state);
>
> --
> 2.7.4
>
> ___
> Intel-gfx
quot;DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { "DPLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1,0 },
> { },
> };
>
> static const struct intel_dpll_mgr ehl_pll_mgr
On Fri, Apr 05, 2019 at 09:33:56PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 05, 2019 at 10:59:53AM -0700, Vivek Kasireddy wrote:
> > This patch adds support for DPLL4 on EHL that include the
> > following restrictions:
> >
> > - DPLL4 cannot be used with DDIA (comb
On Fri, Apr 05, 2019 at 04:33:30PM -0700, Vivek Kasireddy wrote:
> On Fri, 5 Apr 2019 21:39:11 +0300
> Ville Syrjälä wrote:
> Hi Ville,
>
> > On Fri, Apr 05, 2019 at 09:33:56PM +0300, Ville Syrjälä wrote:
> > > On Fri, Apr 05, 2019 at 10:59:53AM -0700, Vivek Kasireddy
On Mon, Apr 01, 2019 at 11:00:06PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä
>
> This defines the color lut ranges for 10bit and multi
> segmented gamma range for ICL.
>
> Signed-off-by: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/d
ut)
> gamma_mode |= PRE_CSC_GAMMA_ENABLE;
>
> @@ -1048,6 +1200,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state
> *crtc_state)
> if (!crtc_state->base.gamma_lut ||
> crtc_state_is_legacy_gamma(crtc_state))
> gamma_mode |= GAMMA_MODE_MODE_
On Mon, Apr 08, 2019 at 09:16:34AM +0300, Jani Nikula wrote:
> On Fri, 05 Apr 2019, Imre Deak wrote:
> > On Fri, Apr 05, 2019 at 05:13:49PM +0300, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> The only bpc information in pipe registers for BXT/GLK
On Mon, Apr 08, 2019 at 12:26:23PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> >Of Ville
> >Syrjälä
> >Sent: Friday, April 5, 2019 9:42 PM
> >To: Shankar,
On Mon, Apr 08, 2019 at 02:40:51PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Monday, April 8, 2019 6:01 PM
> >To: Shankar, Uma
> >Cc: dcasta...@chromium.org; intel-g
tarts support
> >colorkey, and is there a way to backport it to kernel 3.10.61?
How about actually reading my reply to your earlier mail?
https://lists.freedesktop.org/archives/intel-gfx/2019-April/194470.html
--
Ville Syrjälä
Intel
__
On Mon, Apr 08, 2019 at 03:40:39PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Monday, April 8, 2019 8:27 PM
> >To: Shankar, Uma
> >Cc: dcasta...@chromium.org; intel-g
m2),
> > + (5 * div1 * div2) << 22);
>
> You say the denominator here is a u64, so do you not need to cast
> (u64)(5 * d1 * d2) to ensure it doesn't overflow the shift?
It should fit into u32. The maximum value sh
On Mon, Apr 08, 2019 at 03:59:51PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> >Of Ville
> >Syrjälä
> >Sent: Monday, April 8, 2019 9:15 PM
> >To: Shankar,
ges in intel_hdmi_compute_config as desired_bpp
> > is needed to change values for pipe_bpp based on bw_constrained flag.
> >
> > v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
> >
> > v6: Fix comment formatting (Ville)
> >
> &g
33
>
> --
> 2.7.4
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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