[PATCH v2 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()

[Ville Syrjala]

From: Ville Syrjälä 

Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.

v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c  | 6 +++---
 drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct 
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
 }
 
 static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
 
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
   PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct 
intel_plane *plane,
  val);
}
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, 
plane->id),
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
  plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..e58930ff32ea 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
 #define _CUR_BUF_CFG_B 0x7117c
 #define CUR_BUF_CFG(pipe)  _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, 
_CUR_BUF_CFG_B)
 
+/* tgl+ */
+#define _SEL_FETCH_CUR_CTL_A   0x70880
+#define _SEL_FETCH_CUR_CTL_B   0x71880
+#define SEL_FETCH_CUR_CTL(pipe)_MMIO_PIPE((pipe), 
_SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B)
+
 #endif /* __INTEL_CURSOR_REGS_H__ */
-- 
2.44.1

[PATCH v2] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+

[Ville Syrjala]

From: Ville Syrjälä 

Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2.
Bump our limit to match.

v2: Bump for ADL-S as well (Jani)

Cc: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0faf2afa1c09..9ac670a40bc1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct 
intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int max_tmds_clock, vbt_max_tmds_clock;
 
-   if (DISPLAY_VER(dev_priv) >= 10)
+   if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_S(dev_priv))
+   max_tmds_clock = 60;
+   else if (DISPLAY_VER(dev_priv) >= 10)
max_tmds_clock = 594000;
else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
-- 
2.44.1

[PATCH v2 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id

[Ville Syrjala]

From: Ville Syrjälä 

Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.

v2: Don't break icl_nv12_y_plane_mask() (Jani)

Cc: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_crtc.c |  6 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +++
 .../drm/i915/display/intel_display_limits.h   | 21 ---
 .../gpu/drm/i915/display/intel_sprite_uapi.c  |  2 +-
 .../drm/i915/display/skl_universal_plane.c| 19 -
 5 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 339010384b86..ca6dc1dc56c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum 
pipe pipe)
crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
 
if (DISPLAY_VER(dev_priv) >= 9)
-   primary = skl_universal_plane_create(dev_priv, pipe,
-PLANE_PRIMARY);
+   primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
else
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum 
pipe pipe)
struct intel_plane *plane;
 
if (DISPLAY_VER(dev_priv) >= 9)
-   plane = skl_universal_plane_create(dev_priv, pipe,
-  PLANE_SPRITE0 + 
sprite);
+   plane = skl_universal_plane_create(dev_priv, pipe, 
PLANE_2 + sprite);
else
plane = intel_sprite_plane_create(dev_priv, pipe, 
sprite);
if (IS_ERR(plane)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb541..ee2df655b0ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct 
intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
 
if (icl_is_hdr_plane(dev_priv, plane->id)) {
-   if (linked->id == PLANE_SPRITE5)
+   if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
-   else if (linked->id == PLANE_SPRITE4)
+   else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
-   else if (linked->id == PLANE_SPRITE3)
+   else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
-   else if (linked->id == PLANE_SPRITE2)
+   else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h 
b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 5126d0b5ae5d..c4775c99dc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -60,16 +60,23 @@ enum transcoder {
  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
  */
 enum plane_id {
-   PLANE_PRIMARY,
-   PLANE_SPRITE0,
-   PLANE_SPRITE1,
-   PLANE_SPRITE2,
-   PLANE_SPRITE3,
-   PLANE_SPRITE4,
-   PLANE_SPRITE5,
+   /* skl+ universal plane names */
+   PLANE_1,
+   PLANE_2,
+   PLANE_3,
+   PLANE_4,
+   PLANE_5,
+   PLANE_6,
+   PLANE_7,
+
PLANE_CURSOR,
 
I915_MAX_PLANES,
+
+   /* pre-skl plane names */
+   PLANE_PRIMARY = PLANE_1,
+   PLANE_SPRITE0,
+   PLANE_SPRITE1,
 };
 
 enum port {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c 
b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
index a76b48ebc2d3..4853c4806004 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, 
void *data,
 * pipe simultaneously.
 */
if (DISPLAY_VER(dev_priv) >= 9 &&
-   to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+   to_intel_plane(plane)->id >= PLANE_3 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return 

[PATCH 6/7] drm/i915: Utilize edp_disable_dsc from VBT

[Ville Syrjala]

From: Ville Syrjälä 

Disable eDP DSC usage when instructed to do so by the VBT.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bios.c  | 4 
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c| 4 
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index b0a49b2f957f..97c6fcf0fe2b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1512,6 +1512,10 @@ parse_edp(struct drm_i915_private *i915,
if (i915->display.vbt.version >= 244)
panel->vbt.edp.max_link_rate =
edp->edp_max_port_link_rate[panel_type] * 20;
+
+   if (i915->display.vbt.version >= 251)
+   panel->vbt.edp.dsc_disable =
+   panel_bool(edp->edp_dsc_disable, panel_type);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9678c2b157f6..5e0372c14643 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -329,6 +329,7 @@ struct intel_vbt_panel_data {
u8 drrs_msa_timing_delay;
bool low_vswing;
bool hobl;
+   bool dsc_disable;
} edp;
 
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a15ef6c015c8..af298d5017d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1230,6 +1230,10 @@ bool intel_dp_has_dsc(struct intel_connector *connector)
if (connector->mst_port && !HAS_DSC_MST(i915))
return false;
 
+   if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
+   connector->panel.vbt.edp.dsc_disable)
+   return false;
+
if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
return false;
 
-- 
2.44.1

[PATCH 7/7] drm/i915: Remove bogus MST check in intel_dp_has_audio()

[Ville Syrjala]

From: Ville Syrjälä 

No idea what this MST checks is doing in intel_dp_has_audio().
Looks completely pointless, so get rid of it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index af298d5017d9..4a486bb6d48c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2806,7 +2806,6 @@ intel_dp_drrs_compute_config(struct intel_connector 
*connector,
 }
 
 static bool intel_dp_has_audio(struct intel_encoder *encoder,
-  struct intel_crtc_state *crtc_state,
   const struct drm_connector_state *conn_state)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -2815,8 +2814,7 @@ static bool intel_dp_has_audio(struct intel_encoder 
*encoder,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
 
-   if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
-   !intel_dp_port_has_audio(i915, encoder->port))
+   if (!intel_dp_port_has_audio(i915, encoder->port))
return false;
 
if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
@@ -2875,7 +2873,7 @@ intel_dp_audio_compute_config(struct intel_encoder 
*encoder,
  struct drm_connector_state *conn_state)
 {
pipe_config->has_audio =
-   intel_dp_has_audio(encoder, pipe_config, conn_state) &&
+   intel_dp_has_audio(encoder, conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
 
pipe_config->sdp_split_enable = pipe_config->has_audio &&
-- 
2.44.1

[PATCH 5/7] drm/i915: Reuse intel_dp_supports_dsc() for MST

[Ville Syrjala]

From: Ville Syrjälä 

intel_dp_supports_dsc() now works for MST as well, reuse it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp.h |  3 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 
 3 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6dfde22e5f9d..a15ef6c015c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1459,8 +1459,8 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp,
drm_dp_sink_supports_fec(connector->dp.fec_capability);
 }
 
-static bool intel_dp_supports_dsc(struct intel_connector *connector,
- const struct intel_crtc_state *crtc_state)
+bool intel_dp_supports_dsc(struct intel_connector *connector,
+  const struct intel_crtc_state *crtc_state)
 {
if (!intel_dp_has_dsc(connector))
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index c0d3e315559e..f1d90fc458d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -170,6 +170,9 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp,
   const struct intel_connector *connector,
   const struct intel_crtc_state *pipe_config);
 
+bool intel_dp_supports_dsc(struct intel_connector *connector,
+  const struct intel_crtc_state *crtc_state);
+
 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 
pipe_bpp);
 
 void intel_ddi_update_pipe(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b57753d2d82c..4a624c826604 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -400,18 +400,6 @@ static int intel_dp_mst_update_slots(struct intel_encoder 
*encoder,
return 0;
 }
 
-static bool
-intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state)
-{
-   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-
-   /*
-* FIXME: Enabling DSC on ICL results in blank screen and FIFO pipe /
-* transcoder underruns, re-enable DSC after fixing this issue.
-*/
-   return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state);
-}
-
 static int mode_hblank_period_ns(const struct drm_display_mode *mode)
 {
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
@@ -443,7 +431,7 @@ hblank_expansion_quirk_needs_dsc(const struct 
intel_connector *connector,
 }
 
 static bool
-adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector 
*connector,
+adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_connector *connector,
 const struct intel_crtc_state 
*crtc_state,
 struct link_config_limits *limits,
 bool dsc)
@@ -456,7 +444,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct 
intel_connector *conne
return true;
 
if (!dsc) {
-   if (intel_dp_mst_dsc_source_support(crtc_state)) {
+   if (intel_dp_supports_dsc(connector, crtc_state)) {
drm_dbg_kms(>drm,
"[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed 
by hblank expansion quirk\n",
crtc->base.base.id, crtc->base.name,
@@ -503,7 +491,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct 
intel_connector *conne
 
 static bool
 intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
-  const struct intel_connector *connector,
+  struct intel_connector *connector,
   struct intel_crtc_state *crtc_state,
   bool dsc,
   struct link_config_limits *limits)
@@ -602,7 +590,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder 
*encoder,
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
 
-   if (!intel_dp_mst_dsc_source_support(pipe_config))
+   if (!intel_dp_supports_dsc(connector, pipe_config))
return -EINVAL;
 
if (!intel_dp_mst_compute_config_limits(intel_dp,
-- 
2.44.1

[PATCH 4/7] drm/i915: Use intel_dp_has_dsc() during .compute_config()

[Ville Syrjala]

From: Ville Syrjälä 

Reuse intel_dp_has_dsc() during .compute_config() instead of
repeating some of the checks again by hand. We'll be adding
more checks to intel_dp_has_dsc() and this will make sure
we cover both .mode_valid() and .compute_config() with them.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a4703b71c498..6dfde22e5f9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1459,14 +1459,16 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp,
drm_dp_sink_supports_fec(connector->dp.fec_capability);
 }
 
-static bool intel_dp_supports_dsc(const struct intel_connector *connector,
+static bool intel_dp_supports_dsc(struct intel_connector *connector,
  const struct intel_crtc_state *crtc_state)
 {
+   if (!intel_dp_has_dsc(connector))
+   return false;
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 
!crtc_state->fec_enable)
return false;
 
-   return intel_dsc_source_support(crtc_state) &&
-   drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
+   return intel_dsc_source_support(crtc_state);
 }
 
 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
@@ -2213,7 +2215,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-   const struct intel_connector *connector =
+   struct intel_connector *connector =
to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
-- 
2.44.1

[PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()

[Ville Syrjala]

From: Ville Syrjälä 

Extract a helper to check whether the source+sink combo
supports DSC. That basic check is needed both during mode
validation and compute config. We'll also need to add extra
checks to both places, so having a single place for it is nicer.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1e88449fe5f2..7bf283b4df7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
   connector->force_bigjoiner_enable;
 }
 
+static bool intel_dp_has_dsc(struct intel_connector *connector)
+{
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+   if (!HAS_DSC(i915))
+   return false;
+
+   if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
+   return false;
+
+   return true;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *_connector,
struct drm_display_mode *mode)
@@ -1274,8 +1287,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode_rate = intel_dp_link_required(target_clock,
   
intel_dp_mode_min_output_bpp(connector, mode));
 
-   if (HAS_DSC(dev_priv) &&
-   drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
+   if (intel_dp_has_dsc(connector)) {
enum intel_output_format sink_format, output_format;
int pipe_bpp;
 
-- 
2.44.1

[PATCH 3/7] drm/i915: Handle MST in intel_dp_has_dsc()

[Ville Syrjala]

From: Ville Syrjälä 

Utilize intel_dp_has_dsc() for MST as well.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 -
 drivers/gpu/drm/i915/display/intel_dp.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7bf283b4df7f..a4703b71c498 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1220,13 +1220,16 @@ bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
   connector->force_bigjoiner_enable;
 }
 
-static bool intel_dp_has_dsc(struct intel_connector *connector)
+bool intel_dp_has_dsc(struct intel_connector *connector)
 {
struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
if (!HAS_DSC(i915))
return false;
 
+   if (connector->mst_port && !HAS_DSC_MST(i915))
+   return false;
+
if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index aad2223df2a3..c0d3e315559e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -90,6 +90,7 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
 bool intel_dp_is_edp(struct intel_dp *intel_dp);
 bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
+bool intel_dp_has_dsc(struct intel_connector *connector);
 int intel_dp_link_symbol_size(int rate);
 int intel_dp_link_symbol_clock(int rate);
 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c772ba19c547..b57753d2d82c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1434,8 +1434,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
return 0;
}
 
-   if (HAS_DSC_MST(dev_priv) &&
-   drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
+   if (intel_dp_has_dsc(intel_connector)) {
/*
 * TBD pass the connector BPC,
 * for now U8_MAX so that max BPC on that platform would be 
picked
-- 
2.44.1

[PATCH 1/7] drm/i915: Drop redundant dsc_decompression_aux check

[Ville Syrjala]

From: Ville Syrjälä 

If we have no dsc_decompression_aux (only possible on MST)
then we won't have the dsc_dpcd caps either. So checking
both is not needed.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index c0a3b6d50681..1e88449fe5f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1451,7 +1451,6 @@ static bool intel_dp_supports_dsc(const struct 
intel_connector *connector,
return false;
 
return intel_dsc_source_support(crtc_state) &&
-   connector->dp.dsc_decompression_aux &&
drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
 }
 
-- 
2.44.1

[PATCH 0/7] drm/i915: DSC stuff

[Ville Syrjala]

From: Ville Syrjälä 

Respect the VBT's edp_disable_dsc bit, and do a bunch
of refactoring around checking for DSC support.

Also threw in a bonus cleanup to intel_dp_has_audio()
that caught my eye.

Ville Syrjälä (7):
  drm/i915: Drop redundant dsc_decompression_aux check
  drm/i915: Extract intel_dp_has_dsc()
  drm/i915: Handle MST in intel_dp_has_dsc()
  drm/i915: Use intel_dp_has_dsc() during .compute_config()
  drm/i915: Reuse intel_dp_supports_dsc() for MST
  drm/i915: Utilize edp_disable_dsc from VBT
  drm/i915: Remove bogus MST check in intel_dp_has_audio()

 drivers/gpu/drm/i915/display/intel_bios.c |  4 ++
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 42 +--
 drivers/gpu/drm/i915/display/intel_dp.h   |  4 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 23 +++---
 5 files changed, 44 insertions(+), 30 deletions(-)

-- 
2.44.1

[PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+

[Ville Syrjala]

From: Ville Syrjälä 

Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2.
Bump our limit to match.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0faf2afa1c09..bd0ba4edcd1d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct 
intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int max_tmds_clock, vbt_max_tmds_clock;
 
-   if (DISPLAY_VER(dev_priv) >= 10)
+   if (DISPLAY_VER(dev_priv) >= 13)
+   max_tmds_clock = 60;
+   else if (DISPLAY_VER(dev_priv) >= 10)
max_tmds_clock = 594000;
else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
-- 
2.44.1

[PATCH] drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid()

[Ville Syrjala]

From: Ville Syrjälä 

Make life easier for drivers by filtering out unwanted YCbCr 4:2:0
only modes prior to calling the connector->mode_valid() hook.
Currently drivers will still see YCbCr 4:2:0 only modes in said
hook, which will likely come as a suprise when the driver has
declared no support for such modes (via setting
connector->ycbcr_420_allowed to false).

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10992
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_probe_helper.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 4f75a1cfd820..249c8c2cb319 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -474,6 +474,10 @@ static int __drm_helper_update_and_validate(struct 
drm_connector *connector,
if (mode->status != MODE_OK)
continue;
 
+   mode->status = drm_mode_validate_ycbcr420(mode, connector);
+   if (mode->status != MODE_OK)
+   continue;
+
ret = drm_mode_validate_pipeline(mode, connector, ctx,
 >status);
if (ret) {
@@ -486,10 +490,6 @@ static int __drm_helper_update_and_validate(struct 
drm_connector *connector,
else
return -EDEADLK;
}
-
-   if (mode->status != MODE_OK)
-   continue;
-   mode->status = drm_mode_validate_ycbcr420(mode, connector);
}
 
return 0;
-- 
2.44.1

[PATCH 12/13] drm/i915: Polish sprite plane register definitions

[Ville Syrjala]

From: Ville Syrjälä 

Group the sprite plane register definitions such that everything
to do wiht the same register is in one place.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_sprite_regs.h  | 231 ++
 1 file changed, 134 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h 
b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
index bb67705652b2..c27adbaf0f00 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -7,6 +7,8 @@
 #include "intel_display_reg_defs.h"
 
 #define _DVSACNTR  0x72180
+#define _DVSBCNTR  0x73180
+#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
 #define   DVS_ENABLE   REG_BIT(31)
 #define   DVS_PIPE_GAMMA_ENABLEREG_BIT(30)
 #define   DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
@@ -28,31 +30,67 @@
 #define   DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
 #define   DVS_TILEDREG_BIT(10)
 #define   DVS_DEST_KEY REG_BIT(2)
+
 #define _DVSALINOFF0x72184
+#define _DVSBLINOFF0x73184
+#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+
 #define _DVSASTRIDE0x72188
+#define _DVSBSTRIDE0x73188
+#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+
 #define _DVSAPOS   0x7218c
+#define _DVSBPOS   0x7318c
+#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
 #define   DVS_POS_Y_MASK   REG_GENMASK(31, 16)
 #define   DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
 #define   DVS_POS_X_MASK   REG_GENMASK(15, 0)
 #define   DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
+
 #define _DVSASIZE  0x72190
+#define _DVSBSIZE  0x73190
+#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
 #define   DVS_HEIGHT_MASK  REG_GENMASK(31, 16)
 #define   DVS_HEIGHT(h)REG_FIELD_PREP(DVS_HEIGHT_MASK, 
(h))
 #define   DVS_WIDTH_MASK   REG_GENMASK(15, 0)
 #define   DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
+
 #define _DVSAKEYVAL0x72194
+#define _DVSBKEYVAL0x73194
+#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+
 #define _DVSAKEYMSK0x72198
+#define _DVSBKEYMSK0x73198
+#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+
 #define _DVSASURF  0x7219c
+#define _DVSBSURF  0x7319c
+#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
 #define   DVS_ADDR_MASKREG_GENMASK(31, 12)
+
 #define _DVSAKEYMAXVAL 0x721a0
+#define _DVSBKEYMAXVAL 0x731a0
+#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+
 #define _DVSATILEOFF   0x721a4
+#define _DVSBTILEOFF   0x731a4
+#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
 #define   DVS_OFFSET_Y_MASKREG_GENMASK(31, 16)
 #define   DVS_OFFSET_Y(y)  REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
 #define   DVS_OFFSET_X_MASKREG_GENMASK(15, 0)
 #define   DVS_OFFSET_X(x)  REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
+
 #define _DVSASURFLIVE  0x721ac
+#define _DVSBSURFLIVE  0x731ac
+#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+
 #define _DVSAGAMC_G4X  0x721e0 /* g4x */
+#define _DVSBGAMC_G4X  0x731e0 /* g4x */
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + 
(5 - (i)) * 4) /* 6 x u0.8 */
+
 #define _DVSASCALE 0x72204
+#define _DVSBSCALE 0x73204
+#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
 #define   DVS_SCALE_ENABLE REG_BIT(31)
 #define   DVS_FILTER_MASK  REG_GENMASK(30, 29)
 #define   DVS_FILTER_MEDIUMREG_FIELD_PREP(DVS_FILTER_MASK, 0)
@@ -64,42 +102,18 @@
 #define   DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
 #define   DVS_SRC_HEIGHT_MASK  REG_GENMASK(10, 0)
 #define   DVS_SRC_HEIGHT(h)REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
+
 #define _DVSAGAMC_ILK  0x72300 /* ilk/snb */
-#define _DVSAGAMCMAX_ILK   0x72340 /* ilk/snb */
-
-#define _DVSBCNTR  0x73180
-#define _DVSBLINOFF0x73184
-#define _DVSBSTRIDE0x73188
-#define _DVSBPOS   0x7318c
-#define _DVSBSIZE  0x73190
-#define _DVSBKEYVAL0x73194
-#define _DVSBKEYMSK0x73198
-#define _DVSBSURF  0x7319c
-#define _DVSBKEYMAXVAL 0x731a0
-#define _DVSBTILEOFF   0x731a4
-#define _DVSBSURFLIVE  0x731ac
-#define _DVSBGAMC_G4X  0x731e0 /* g4x */
-#define _DVSBSCALE 0x73204
 #define _DVSBGAMC_ILK  0x73300 /* ilk/snb */
-#define 

[PATCH 13/13] drm/i915: Document which platforms use which sprite registers

[Ville Syrjala]

From: Ville Syrjälä 

Note which sprite registers are valid for which platforms.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_sprite_regs.h  | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h 
b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
index c27adbaf0f00..73021e3ced6d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -6,6 +6,7 @@
 
 #include "intel_display_reg_defs.h"
 
+/* g4x/ilk/snb video sprite */
 #define _DVSACNTR  0x72180
 #define _DVSBCNTR  0x73180
 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
@@ -111,6 +112,7 @@
 #define _DVSBGAMCMAX_ILK   0x73340 /* ilk/snb */
 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, 
_DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
 
+/* ivb/hsw/bdw sprite */
 #define _SPRA_CTL  0x70280
 #define _SPRB_CTL  0x71280
 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
@@ -140,8 +142,8 @@
 #define   SPRITE_TILED REG_BIT(10)
 #define   SPRITE_DEST_KEY  REG_BIT(2)
 
-#define _SPRA_LINOFF   0x70284
-#define _SPRB_LINOFF   0x71284
+#define _SPRA_LINOFF   0x70284 /* ivb */
+#define _SPRB_LINOFF   0x71284 /* ivb */
 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
 
 #define _SPRA_STRIDE   0x70288
@@ -181,24 +183,24 @@
 #define _SPRB_KEYMAX   0x712a0
 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
 
-#define _SPRA_TILEOFF  0x702a4
-#define _SPRB_TILEOFF  0x712a4
+#define _SPRA_TILEOFF  0x702a4 /* ivb */
+#define _SPRB_TILEOFF  0x712a4 /* ivb */
 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
 #define   SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
 #define   SPRITE_OFFSET_Y(y)   REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
 #define   SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
 #define   SPRITE_OFFSET_X(x)   REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
 
-#define _SPRA_OFFSET   0x702a4
-#define _SPRB_OFFSET   0x712a4
+#define _SPRA_OFFSET   0x702a4 /* hsw/bdw */
+#define _SPRB_OFFSET   0x712a4 /* hsw/bdw */
 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
 
 #define _SPRA_SURFLIVE 0x702ac
 #define _SPRB_SURFLIVE 0x712ac
 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
 
-#define _SPRA_SCALE0x70304
-#define _SPRB_SCALE0x71304
+#define _SPRA_SCALE0x70304 /* ivb */
+#define _SPRB_SCALE0x71304 /* ivb */
 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
 #define   SPRITE_SCALE_ENABLE  REG_BIT(31)
 #define   SPRITE_FILTER_MASK   REG_GENMASK(30, 29)
@@ -224,6 +226,7 @@
 #define _SPRB_GAMC17   0x7144c
 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) 
* 4) /* 3 x u2.10 */
 
+/* vlv/chv sprite */
 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
-- 
2.44.1

[PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.

Cc: Zhenyu Wang 
Cc: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c |  1 +
 .../gpu/drm/i915/display/i9xx_plane_regs.h| 98 +++
 .../gpu/drm/i915/display/intel_atomic_plane.c |  1 +
 drivers/gpu/drm/i915/display/intel_color.c|  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c  |  1 +
 drivers/gpu/drm/i915/gvt/cmd_parser.c |  1 +
 drivers/gpu/drm/i915/gvt/display.c|  1 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |  1 +
 drivers/gpu/drm/i915/i915_reg.h   | 87 +---
 drivers/gpu/drm/i915/intel_clock_gating.c |  1 +
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  1 +
 13 files changed, 110 insertions(+), 87 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ea4d8ba55ad8..1f05f9184cb2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 #include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h 
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
new file mode 100644
index ..0bf2cd42bce7
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __I9XX_PLANE_REGS_H__
+#define __I9XX_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _DSPAADDR_VLV  0x7017C /* vlv/chv */
+#define _DSPACNTR  0x70180
+#define   DISP_ENABLE  REG_BIT(31)
+#define   DISP_PIPE_GAMMA_ENABLE   REG_BIT(30)
+#define   DISP_FORMAT_MASK REG_GENMASK(29, 26)
+#define   DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+#define   DISP_FORMAT_BGRA555  REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+#define   DISP_FORMAT_BGRX555  REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+#define   DISP_FORMAT_BGRX565  REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+#define   DISP_FORMAT_BGRX888  REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+#define   DISP_FORMAT_BGRA888  REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+#define   DISP_FORMAT_RGBX101010   REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+#define   DISP_FORMAT_RGBA101010   REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+#define   DISP_FORMAT_BGRX101010   REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+#define   DISP_FORMAT_BGRA101010   REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+#define   DISP_FORMAT_RGBX161616   REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+#define   DISP_FORMAT_RGBX888  REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+#define   DISP_FORMAT_RGBA888  REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+#define   DISP_STEREO_ENABLE   REG_BIT(25)
+#define   DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define   DISP_PIPE_SEL_MASK   REG_GENMASK(25, 24)
+#define   DISP_PIPE_SEL(pipe)  REG_FIELD_PREP(DISP_PIPE_SEL_MASK, 
(pipe))
+#define   DISP_SRC_KEY_ENABLE  REG_BIT(22)
+#define   DISP_LINE_DOUBLE REG_BIT(20)
+#define   DISP_STEREO_POLARITY_SECOND  REG_BIT(18)
+#define   DISP_ALPHA_PREMULTIPLY   REG_BIT(16) /* CHV pipe B */
+#define   DISP_ROTATE_180  REG_BIT(15)
+#define   DISP_TRICKLE_FEED_DISABLEREG_BIT(14) /* g4x+ */
+#define   DISP_TILED   REG_BIT(10)
+#define   DISP_ASYNC_FLIP  REG_BIT(9) /* g4x+ */
+#define   DISP_MIRROR  REG_BIT(8) /* CHV pipe B */
+#define _DSPAADDR  0x70184
+#define _DSPASTRIDE0x70188
+#define _DSPAPOS   0x7018C /* reserved */
+#define   DISP_POS_Y_MASK  REG_GENMASK(31, 16)
+#define   DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, 
(y))
+#define   DISP_POS_X_MASK  REG_GENMASK(15, 0)
+#define   DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, 
(x))
+#define _DSPASIZE  0x70190
+#define   DISP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define   DISP_HEIGHT(h)   REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+#define   DISP_WIDTH_MASK  REG_GENMASK(15, 0)
+#define   DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, 
(w))
+#define _DSPASURF  0x7019C /* 965+ only */
+#define   DISP_ADDR_MASK   REG_GENMASK(31, 12)
+#define _DSPATILEOFF   0x701A4 /* 965+ only */
+#define   

[PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies

[Ville Syrjala]

From: Ville Syrjälä 

Add some notes indicatign which plane registers/bits are
valid for which platforms.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +--
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h 
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 929b26faf31e..d74a74d1f29a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -37,53 +37,53 @@
 #define   DISP_LINE_DOUBLE REG_BIT(20)
 #define   DISP_STEREO_POLARITY_SECOND  REG_BIT(18)
 #define   DISP_ALPHA_PREMULTIPLY   REG_BIT(16) /* CHV pipe B */
-#define   DISP_ROTATE_180  REG_BIT(15)
+#define   DISP_ROTATE_180  REG_BIT(15) /* i965+ */
 #define   DISP_TRICKLE_FEED_DISABLEREG_BIT(14) /* g4x+ */
-#define   DISP_TILED   REG_BIT(10)
+#define   DISP_TILED   REG_BIT(10) /* i965+ */
 #define   DISP_ASYNC_FLIP  REG_BIT(9) /* g4x+ */
 #define   DISP_MIRROR  REG_BIT(8) /* CHV pipe B */
 
-#define _DSPAADDR  0x70184
+#define _DSPAADDR  0x70184 /* pre-i965 */
 #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPAADDR)
 
-#define _DSPALINOFF0x70184
+#define _DSPALINOFF0x70184 /* i965+ */
 #define DSPLINOFF(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPALINOFF)
 
 #define _DSPASTRIDE0x70188
 #define DSPSTRIDE(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPASTRIDE)
 
-#define _DSPAPOS   0x7018C /* reserved */
+#define _DSPAPOS   0x7018C /* pre-g4x */
 #define DSPPOS(plane)  _MMIO_PIPE2(dev_priv, plane, 
_DSPAPOS)
 #define   DISP_POS_Y_MASK  REG_GENMASK(31, 16)
 #define   DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, 
(y))
 #define   DISP_POS_X_MASK  REG_GENMASK(15, 0)
 #define   DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, 
(x))
 
-#define _DSPASIZE  0x70190
+#define _DSPASIZE  0x70190 /* pre-g4x */
 #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASIZE)
 #define   DISP_HEIGHT_MASK REG_GENMASK(31, 16)
 #define   DISP_HEIGHT(h)   REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
 #define   DISP_WIDTH_MASK  REG_GENMASK(15, 0)
 #define   DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, 
(w))
 
-#define _DSPASURF  0x7019C /* 965+ only */
+#define _DSPASURF  0x7019C /* i965+ */
 #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASURF)
 #define   DISP_ADDR_MASK   REG_GENMASK(31, 12)
 
-#define _DSPATILEOFF   0x701A4 /* 965+ only */
+#define _DSPATILEOFF   0x701A4 /* i965+ */
 #define DSPTILEOFF(plane)  _MMIO_PIPE2(dev_priv, plane, 
_DSPATILEOFF)
 #define   DISP_OFFSET_Y_MASK   REG_GENMASK(31, 16)
 #define   DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
 #define   DISP_OFFSET_X_MASK   REG_GENMASK(15, 0)
 #define   DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
 
-#define _DSPAOFFSET0x701A4 /* HSW */
+#define _DSPAOFFSET0x701A4 /* hsw+ */
 #define DSPOFFSET(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPAOFFSET)
 
-#define _DSPASURFLIVE  0x701AC
+#define _DSPASURFLIVE  0x701AC /* g4x+ */
 #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASURFLIVE)
 
-#define _DSPAGAMC  0x701E0
+#define _DSPAGAMC  0x701E0 /* pre-g4x */
 #define DSPGAMC(plane, i)  _MMIO_PIPE2(dev_priv, plane, 
_DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
 
 /* CHV pipe B primary plane */
-- 
2.44.1

[PATCH 10/13] drm/i915: Polish pre-skl primary plane registers

[Ville Syrjala]

From: Ville Syrjälä 

Group the pre-skl primary plane register definitions
sensible, and toss in a few comments to indicate which
platforms have what.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/i9xx_plane_regs.h| 46 ---
 1 file changed, 29 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h 
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 0bf2cd42bce7..929b26faf31e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -9,7 +9,10 @@
 #include "intel_display_reg_defs.h"
 
 #define _DSPAADDR_VLV  0x7017C /* vlv/chv */
+#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPAADDR_VLV)
+
 #define _DSPACNTR  0x70180
+#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPACNTR)
 #define   DISP_ENABLE  REG_BIT(31)
 #define   DISP_PIPE_GAMMA_ENABLE   REG_BIT(30)
 #define   DISP_FORMAT_MASK REG_GENMASK(29, 26)
@@ -39,60 +42,69 @@
 #define   DISP_TILED   REG_BIT(10)
 #define   DISP_ASYNC_FLIP  REG_BIT(9) /* g4x+ */
 #define   DISP_MIRROR  REG_BIT(8) /* CHV pipe B */
+
 #define _DSPAADDR  0x70184
+#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPAADDR)
+
+#define _DSPALINOFF0x70184
+#define DSPLINOFF(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPALINOFF)
+
 #define _DSPASTRIDE0x70188
+#define DSPSTRIDE(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPASTRIDE)
+
 #define _DSPAPOS   0x7018C /* reserved */
+#define DSPPOS(plane)  _MMIO_PIPE2(dev_priv, plane, 
_DSPAPOS)
 #define   DISP_POS_Y_MASK  REG_GENMASK(31, 16)
 #define   DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, 
(y))
 #define   DISP_POS_X_MASK  REG_GENMASK(15, 0)
 #define   DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, 
(x))
+
 #define _DSPASIZE  0x70190
+#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASIZE)
 #define   DISP_HEIGHT_MASK REG_GENMASK(31, 16)
 #define   DISP_HEIGHT(h)   REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
 #define   DISP_WIDTH_MASK  REG_GENMASK(15, 0)
 #define   DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, 
(w))
+
 #define _DSPASURF  0x7019C /* 965+ only */
+#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASURF)
 #define   DISP_ADDR_MASK   REG_GENMASK(31, 12)
+
 #define _DSPATILEOFF   0x701A4 /* 965+ only */
+#define DSPTILEOFF(plane)  _MMIO_PIPE2(dev_priv, plane, 
_DSPATILEOFF)
 #define   DISP_OFFSET_Y_MASK   REG_GENMASK(31, 16)
 #define   DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
 #define   DISP_OFFSET_X_MASK   REG_GENMASK(15, 0)
 #define   DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
+
 #define _DSPAOFFSET0x701A4 /* HSW */
+#define DSPOFFSET(plane)   _MMIO_PIPE2(dev_priv, plane, 
_DSPAOFFSET)
+
 #define _DSPASURFLIVE  0x701AC
+#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, 
_DSPASURFLIVE)
+
 #define _DSPAGAMC  0x701E0
-
-#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
-#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
-#define DSPSTRIDE(plane)   _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
-#define DSPPOS(plane)  _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
-#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
-#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
-#define DSPTILEOFF(plane)  _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
-#define DSPLINOFF(plane)   DSPADDR(plane)
-#define DSPOFFSET(plane)   _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i)  _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - 
(i)) * 4) /* plane C only, 6 x u0.8 */
+#define DSPGAMC(plane, i)  _MMIO_PIPE2(dev_priv, plane, 
_DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
 
 /* CHV pipe B primary plane */
 #define _PRIMPOS_A 0x60a08
+#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
 #define   PRIM_POS_Y_MASK  REG_GENMASK(31, 16)
 #define   PRIM_POS_Y(y)REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
 #define   

[PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

PIPEGCMAX was left behind when all other gamma registers moved
into intel_color_regs.h.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h 
b/drivers/gpu/drm/i915/display/intel_color_regs.h
index bb99ea533842..61c18b4a7fa5 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -36,6 +36,11 @@
  _CHV_PALETTE_C, 
_CHV_PALETTE_C) + \
  (i) * 4)
 
+/* i965/g4x/vlv/chv */
+#define  _PIPEAGCMAX   0x70010
+#define  _PIPEBGCMAX   0x71010
+#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 
4) /* u1.16 */
+
 /* ilk+ palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52b029cd3981..f5e8833cc37e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1882,10 +1882,6 @@
 #define PIPEFRAMEPIXEL(pipe)   _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
 #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
 
-#define  _PIPEAGCMAX   0x70010
-#define  _PIPEBGCMAX   0x71010
-#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 
4) /* u1.16 */
-
 #define _PIPE_ARB_CTL_A0x70028 /* icl+ */
 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, 
_PIPE_ARB_CTL_A)
 #define   PIPE_ARB_USE_PROG_SLOTS  REG_BIT(13)
-- 
2.44.1

[PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits

[Ville Syrjala]

From: Ville Syrjälä 

Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c   | 34 +++
 .../gpu/drm/i915/display/intel_cursor_regs.h  |  9 +
 .../drm/i915/display/skl_universal_plane.c|  4 +--
 .../drm/i915/display/skl_universal_plane.h|  3 --
 4 files changed, 39 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 7983cbaf83f7..cea0cfed569d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,7 +24,6 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vblank.h"
-#include "skl_universal_plane.h"
 #include "skl_watermark.h"
 
 #include "gem/i915_gem_object.h"
@@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct 
intel_plane *plane,
}
 }
 
+static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+   if (!entry->end)
+   return 0;
+
+   return CUR_BUF_END(entry->end - 1) |
+   CUR_BUF_START(entry->start);
+}
+
+static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
+{
+   u32 val = 0;
+
+   if (level->enable)
+   val |= CUR_WM_EN;
+   if (level->ignore_lines)
+   val |= CUR_WM_IGNORE_LINES;
+   val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
+   val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
+
+   return val;
+}
+
 static void skl_write_cursor_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
 {
@@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
 
for (level = 0; level < i915->display.wm.num_levels; level++)
intel_de_write_fw(i915, CUR_WM(pipe, level),
- 
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+ 
skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
 
intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
- skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
+ skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
 
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
 
intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
- skl_plane_wm_reg_val(>sagv.wm0));
+ skl_cursor_wm_reg_val(>sagv.wm0));
intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
- skl_plane_wm_reg_val(>sagv.trans_wm));
+ skl_cursor_wm_reg_val(>sagv.trans_wm));
}
 
intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
- skl_plane_ddb_reg_val(ddb));
+ skl_cursor_ddb_reg_val(ddb));
 }
 
 /* TODO: split into noarm+arm pair */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index ab02d497fba6..307a850d54b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -78,6 +78,10 @@
 #define _CUR_WM_A_00x70140
 #define _CUR_WM_B_00x71140
 #define CUR_WM(pipe, level)_MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + 
(level) * 4)
+#define   CUR_WM_ENREG_BIT(31)
+#define   CUR_WM_IGNORE_LINES  REG_BIT(30)
+#define   CUR_WM_LINES_MASKREG_GENMASK(26, 14)
+#define   CUR_WM_BLOCKS_MASK   REG_GENMASK(11, 0)
 
 #define _CUR_WM_SAGV_A 0x70158
 #define _CUR_WM_SAGV_B 0x71158
@@ -94,6 +98,11 @@
 #define _CUR_BUF_CFG_A 0x7017c
 #define _CUR_BUF_CFG_B 0x7117c
 #define CUR_BUF_CFG(pipe)  _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, 
_CUR_BUF_CFG_B)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define   CUR_BUF_END_MASK REG_GENMASK(27, 16)
+#define   CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
+#define   CUR_BUF_START_MASK   REG_GENMASK(11, 0)
+#define   CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, 
(start))
 
 #define _SEL_FETCH_CUR_CTL_A   0x70880 /* mtl+ */
 #define _SEL_FETCH_CUR_CTL_B   0x71880
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6601baf18ae4..de51652358c9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state 
*plane_state,
return stride / skl_plane_stride_mult(fb, 

[PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()

[Ville Syrjala]

From: Ville Syrjälä 

Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
for the SEL_FETCH_PLANE registers. A bit more tedious to have
to define 8 raw register offsets for everything, but perhaps
a bit easier to understand since we use a standard mechanism
now instead of hand rolling the arithmetic.

Also bloat-o-meter says:
add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326)
Function old new   delta
icl_plane_update_arm 510 446 -64
icl_plane_disable_sel_fetch_arm.isra 158  54-104
icl_plane_update_noarm  18981740-158
Total: Before=2574502, After=2574176, chg -0.01%

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 
 .../i915/display/skl_universal_plane_regs.h   | 68 +++
 2 files changed, 68 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h 
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index f0bd0a726d7a..289c371c98d1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -251,51 +251,6 @@
 #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
 #define PIPE_SRCSZ_ERLY_TPT(pipe)  _MMIO_PIPE((pipe), 
_PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
 
-#define _SEL_FETCH_PLANE_BASE_1_A  0x70890
-#define _SEL_FETCH_PLANE_BASE_2_A  0x708B0
-#define _SEL_FETCH_PLANE_BASE_3_A  0x708D0
-#define _SEL_FETCH_PLANE_BASE_4_A  0x708F0
-#define _SEL_FETCH_PLANE_BASE_5_A  0x70920
-#define _SEL_FETCH_PLANE_BASE_6_A  0x70940
-#define _SEL_FETCH_PLANE_BASE_7_A  0x70960
-#define _SEL_FETCH_PLANE_BASE_CUR_A0x70880
-#define _SEL_FETCH_PLANE_BASE_1_B  0x71890
-
-#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
-_SEL_FETCH_PLANE_BASE_1_A, \
-_SEL_FETCH_PLANE_BASE_2_A, \
-_SEL_FETCH_PLANE_BASE_3_A, \
-_SEL_FETCH_PLANE_BASE_4_A, \
-_SEL_FETCH_PLANE_BASE_5_A, \
-_SEL_FETCH_PLANE_BASE_6_A, \
-_SEL_FETCH_PLANE_BASE_7_A, \
-_SEL_FETCH_PLANE_BASE_CUR_A)
-#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, 
_SEL_FETCH_PLANE_BASE_1_B)
-#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
-   _SEL_FETCH_PLANE_BASE_1_A + \
-   _SEL_FETCH_PLANE_BASE_A(plane))
-
-#define _SEL_FETCH_PLANE_CTL_1_A   0x70890
-#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
-  _SEL_FETCH_PLANE_CTL_1_A - \
-  _SEL_FETCH_PLANE_BASE_1_A)
-#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
-
-#define _SEL_FETCH_PLANE_POS_1_A   0x70894
-#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
-  _SEL_FETCH_PLANE_POS_1_A - \
-  _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_SIZE_1_A  0x70898
-#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
-   _SEL_FETCH_PLANE_SIZE_1_A - \
-   _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_OFFSET_1_A0x7089C
-#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
- _SEL_FETCH_PLANE_OFFSET_1_A - 
\
- _SEL_FETCH_PLANE_BASE_1_A)
-
 #define _ALPM_CTL_A0x60950
 #define ALPM_CTL(dev_priv, tran)   _MMIO_TRANS2(dev_priv, tran, 
_ALPM_CTL_A)
 #define  ALPM_CTL_ALPM_ENABLE  REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index cb3bdd71b6b2..a6528e0d719e 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -17,6 +17,17 @@
 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, 
reg_2_b) \
_MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), 
(reg_2_a), (reg_2_b)))
 
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, 
reg_5_b, reg_6_a, reg_6_b) \
+   _PICK_EVEN_2RANGES((plane), PLANE_5, \
+  _PIPE((pipe), (reg_1_a), (reg_1_b)), \
+ 

[PATCH 05/13] drm/i915: Rename selective fetch plane registers

[Ville Syrjala]

From: Ville Syrjälä 

Rename the selective fetch plane registers to match the spec.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h  | 10 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h 
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 47e3a2e2977c..f0bd0a726d7a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -276,23 +276,23 @@
_SEL_FETCH_PLANE_BASE_A(plane))
 
 #define _SEL_FETCH_PLANE_CTL_1_A   0x70890
-#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
+#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
   _SEL_FETCH_PLANE_CTL_1_A - \
   _SEL_FETCH_PLANE_BASE_1_A)
-#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
+#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
 
 #define _SEL_FETCH_PLANE_POS_1_A   0x70894
-#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
+#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
   _SEL_FETCH_PLANE_POS_1_A - \
   _SEL_FETCH_PLANE_BASE_1_A)
 
 #define _SEL_FETCH_PLANE_SIZE_1_A  0x70898
-#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
+#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
_SEL_FETCH_PLANE_SIZE_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
 
 #define _SEL_FETCH_PLANE_OFFSET_1_A0x7089C
-#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
+#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
  _SEL_FETCH_PLANE_OFFSET_1_A - 
\
  _SEL_FETCH_PLANE_BASE_1_A)
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d0bfee2ca643..6601baf18ae4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct 
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
 
-   intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+   intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
 }
 
 static void
@@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct 
intel_plane *plane,
 
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
val |= plane_state->uapi.dst.x1;
-   intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+   intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
 
x = plane_state->view.color_plane[color_plane].x;
 
@@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct 
intel_plane *plane,
 
val = y << 16 | x;
 
-   intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+   intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id),
  val);
 
/* Sizes are 0 based */
val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(_state->uapi.src) >> 16) - 1;
-   intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+   intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
 }
 
 static void
@@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct 
intel_plane *plane,
return;
 
if (drm_rect_height(_state->psr2_sel_fetch_area) > 0)
-   intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
- PLANE_SEL_FETCH_CTL_ENABLE);
+   intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id),
+ SEL_FETCH_PLANE_CTL_ENABLE);
else
icl_plane_disable_sel_fetch_arm(plane, crtc_state);
 }
-- 
2.44.1

[PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition

[Ville Syrjala]

From: Ville Syrjälä 

PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index b44809899502..7983cbaf83f7 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane,
 
intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
 
-   intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
+   intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
   PIPESRC_HEIGHT(et_y_position));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index df0d14a5023f..d49e869f6be2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2381,7 +2381,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct 
intel_crtc_state *crtc_st
if (!crtc_state->enable_psr2_su_region_et)
return;
 
-   intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
+   intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
   crtc_state->pipe_srcsz_early_tpt);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h 
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e14cb48f2614..47e3a2e2977c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -248,8 +248,8 @@
 
 /* PSR2 Early transport */
 #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
-
-#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)   _MMIO_TRANS2(dev_priv, trans, 
_PIPE_SRCSZ_ERLY_TPT_A)
+#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
+#define PIPE_SRCSZ_ERLY_TPT(pipe)  _MMIO_PIPE((pipe), 
_PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
 
 #define _SEL_FETCH_PLANE_BASE_1_A  0x70890
 #define _SEL_FETCH_PLANE_BASE_2_A  0x708B0
-- 
2.44.1

[PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()

[Ville Syrjala]

From: Ville Syrjälä 

Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c  | 6 +++---
 drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct 
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
 }
 
 static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
 
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
   PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct 
intel_plane *plane,
  val);
}
 
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, 
plane->id),
+   intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
  plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..ab02d497fba6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
 #define _CUR_BUF_CFG_B 0x7117c
 #define CUR_BUF_CFG(pipe)  _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, 
_CUR_BUF_CFG_B)
 
+#define _SEL_FETCH_CUR_CTL_A   0x70880 /* mtl+ */
+#define _SEL_FETCH_CUR_CTL_B   0x71880
+#define SEL_FETCH_CUR_CTL(pipe)_MMIO_PIPE((pipe), 
_SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
+#define   SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
+
 #endif /* __INTEL_CURSOR_REGS_H__ */
-- 
2.44.1

[PATCH 02/13] drm/i915: Clean up the cursor register defines

[Ville Syrjala]

From: Ville Syrjälä 

Group the cursor register defines such that everything to
do with one register is in one place.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_cursor_regs.h  | 52 +--
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index c2190af1e9f5..270c26c2e6df 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -9,6 +9,7 @@
 #include "intel_display_reg_defs.h"
 
 #define _CURACNTR  0x70080
+#define CURCNTR(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CURACNTR)
 /* Old style CUR*CNTR flags (desktop 8xx) */
 #define   CURSOR_ENABLEREG_BIT(31)
 #define   CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
@@ -38,61 +39,60 @@
 #define   MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
 #define   MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
 #define   MCURSOR_MODE_64_ARGB_AX  (0x20 | MCURSOR_MODE_64_32B_AX)
+
 #define _CURABASE  0x70084
+#define CURBASE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CURABASE)
+
 #define _CURAPOS   0x70088
-#define _CURAPOS_ERLY_TPT  0x7008c
+#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)
 #define   CURSOR_POS_Y_SIGNREG_BIT(31)
 #define   CURSOR_POS_Y_MASKREG_GENMASK(30, 16)
 #define   CURSOR_POS_Y(y)  REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
 #define   CURSOR_POS_X_SIGNREG_BIT(15)
 #define   CURSOR_POS_X_MASKREG_GENMASK(14, 0)
 #define   CURSOR_POS_X(x)  REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+
+#define _CURAPOS_ERLY_TPT  0x7008c
+#define CURPOS_ERLY_TPT(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), 
(pipe), _CURAPOS_ERLY_TPT)
+
 #define _CURASIZE  0x700a0 /* 845/865 */
+#define CURSIZE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CURASIZE)
 #define   CURSOR_HEIGHT_MASK   REG_GENMASK(21, 12)
 #define   CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
 #define   CURSOR_WIDTH_MASKREG_GENMASK(9, 0)
 #define   CURSOR_WIDTH(w)  REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
+
 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
+#define CUR_FBC_CTL(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CUR_FBC_CTL_A)
 #define   CUR_FBC_EN   REG_BIT(31)
 #define   CUR_FBC_HEIGHT_MASK  REG_GENMASK(7, 0)
 #define   CUR_FBC_HEIGHT(h)REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
+
 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
+#define CUR_CHICKEN(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CUR_CHICKEN_A)
+
 #define _CURASURFLIVE  0x700ac /* g4x+ */
-#define _CURBCNTR  0x700c0
-#define _CURBBASE  0x700c4
-#define _CURBPOS   0x700c8
-
-#define _CURBCNTR_IVB  0x71080
-#define _CURBBASE_IVB  0x71084
-#define _CURBPOS_IVB   0x71088
-
-#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
-#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
-#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
-#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, 
_CURAPOS_ERLY_TPT)
-#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
-#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, 
_CUR_FBC_CTL_A)
-#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, 
_CUR_CHICKEN_A)
-#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, 
_CURASURFLIVE)
+#define CURSURFLIVE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), 
_CURASURFLIVE)
 
 /* skl+ */
 #define _CUR_WM_A_00x70140
 #define _CUR_WM_B_00x71140
+#define CUR_WM(pipe, level)_MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + 
(level) * 4)
+
 #define _CUR_WM_SAGV_A 0x70158
 #define _CUR_WM_SAGV_B 0x71158
+#define CUR_WM_SAGV(pipe)  _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, 
_CUR_WM_SAGV_B)
+
 #define _CUR_WM_SAGV_TRANS_A   0x7015C
 #define _CUR_WM_SAGV_TRANS_B   0x7115C
+#define CUR_WM_SAGV_TRANS(pipe)_MMIO_PIPE((pipe), 
_CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+
 #define _CUR_WM_TRANS_A0x70168
 #define _CUR_WM_TRANS_B0x71168
-#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
-#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, 
_CUR_WM_SAGV_TRANS_B)
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, 
_CUR_WM_TRANS_B)
 
-/* skl+ */
-#define _CUR_BUF_CFG_A 

[PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id

[Ville Syrjala]

From: Ville Syrjälä 

Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_crtc.c |  6 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +++
 .../drm/i915/display/intel_display_limits.h   | 21 ---
 .../gpu/drm/i915/display/intel_sprite_uapi.c  |  2 +-
 .../drm/i915/display/skl_universal_plane.c| 19 -
 5 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 339010384b86..ca6dc1dc56c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum 
pipe pipe)
crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
 
if (DISPLAY_VER(dev_priv) >= 9)
-   primary = skl_universal_plane_create(dev_priv, pipe,
-PLANE_PRIMARY);
+   primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
else
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum 
pipe pipe)
struct intel_plane *plane;
 
if (DISPLAY_VER(dev_priv) >= 9)
-   plane = skl_universal_plane_create(dev_priv, pipe,
-  PLANE_SPRITE0 + 
sprite);
+   plane = skl_universal_plane_create(dev_priv, pipe, 
PLANE_2 + sprite);
else
plane = intel_sprite_plane_create(dev_priv, pipe, 
sprite);
if (IS_ERR(plane)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb541..ee2df655b0ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct 
intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
 
if (icl_is_hdr_plane(dev_priv, plane->id)) {
-   if (linked->id == PLANE_SPRITE5)
+   if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
-   else if (linked->id == PLANE_SPRITE4)
+   else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
-   else if (linked->id == PLANE_SPRITE3)
+   else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
-   else if (linked->id == PLANE_SPRITE2)
+   else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h 
b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 5126d0b5ae5d..c4775c99dc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -60,16 +60,23 @@ enum transcoder {
  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
  */
 enum plane_id {
-   PLANE_PRIMARY,
-   PLANE_SPRITE0,
-   PLANE_SPRITE1,
-   PLANE_SPRITE2,
-   PLANE_SPRITE3,
-   PLANE_SPRITE4,
-   PLANE_SPRITE5,
+   /* skl+ universal plane names */
+   PLANE_1,
+   PLANE_2,
+   PLANE_3,
+   PLANE_4,
+   PLANE_5,
+   PLANE_6,
+   PLANE_7,
+
PLANE_CURSOR,
 
I915_MAX_PLANES,
+
+   /* pre-skl plane names */
+   PLANE_PRIMARY = PLANE_1,
+   PLANE_SPRITE0,
+   PLANE_SPRITE1,
 };
 
 enum port {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c 
b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
index a76b48ebc2d3..4853c4806004 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, 
void *data,
 * pipe simultaneously.
 */
if (DISPLAY_VER(dev_priv) >= 9 &&
-   to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+   to_intel_plane(plane)->id >= PLANE_3 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
 
diff --git 

[PATCH 00/13] drm/i915: Plane register cleanups

[Ville Syrjala]

From: Ville Syrjälä 

Bunch of cleanup mostly around plane registers.

Ville Syrjälä (13):
  drm/i915: Add skl+ plane name aliases to enum plane_id
  drm/i915: Clean up the cursor register defines
  drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
  drm/i915: Simplify PIPESRC_ERLY_TPT definition
  drm/i915: Rename selective fetch plane registers
  drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
  drm/i915: Add separate defines for cursor WM/DDB register bits
  drm/i915: Move PIPEGCMAX to intel_color_regs.h
  drm/i915: Extract i9xx_plane_regs.h
  drm/i915: Polish pre-skl primary plane registers
  drm/i915: Document a few pre-skl primary plane platform dependencies
  drm/i915: Polish sprite plane register definitions
  drm/i915: Document which platforms use which sprite registers

 drivers/gpu/drm/i915/display/i9xx_plane.c |   1 +
 .../gpu/drm/i915/display/i9xx_plane_regs.h| 110 
 .../gpu/drm/i915/display/intel_atomic_plane.c |   1 +
 drivers/gpu/drm/i915/display/intel_color.c|   2 +-
 .../gpu/drm/i915/display/intel_color_regs.h   |   5 +
 drivers/gpu/drm/i915/display/intel_crtc.c |   6 +-
 drivers/gpu/drm/i915/display/intel_cursor.c   |  42 ++-
 .../gpu/drm/i915/display/intel_cursor_regs.h  |  66 +++--
 drivers/gpu/drm/i915/display/intel_display.c  |   9 +-
 .../drm/i915/display/intel_display_limits.h   |  21 +-
 drivers/gpu/drm/i915/display/intel_fbc.c  |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  49 +---
 .../gpu/drm/i915/display/intel_sprite_regs.h  | 242 ++
 .../gpu/drm/i915/display/intel_sprite_uapi.c  |   2 +-
 .../drm/i915/display/skl_universal_plane.c|  35 ++-
 .../drm/i915/display/skl_universal_plane.h|   3 -
 .../i915/display/skl_universal_plane_regs.h   |  68 +
 drivers/gpu/drm/i915/gvt/cmd_parser.c |   1 +
 drivers/gpu/drm/i915/gvt/display.c|   1 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   |  91 +--
 drivers/gpu/drm/i915/intel_clock_gating.c |   1 +
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
 25 files changed, 449 insertions(+), 313 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h

-- 
2.44.1

[PATCH 9/9] drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff

[Ville Syrjala]

From: Ville Syrjälä 

I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")

Bspec had the same exact thing to say about earlier hardware
as well, but we never cared and things work just fine.

The one thing mentioned in that commit that is definitely
true however is the fence alignment issue. But we don't
deal with that on earlier hardware either. We do have code
to deal with that issue for the first color plane, but not
the chroma planes. So I think if we did want to check this
more extensively we should do it in the same places where
we already check the first color plane (namely
convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb.c| 12 +---
 drivers/gpu/drm/i915/display/intel_fb.h|  1 -
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 ---
 3 files changed, 1 insertion(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index c80f866f3fb6..fc18da3106fd 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -584,12 +584,6 @@ static bool is_gen12_ccs_cc_plane(const struct 
drm_framebuffer *fb, int color_pl
return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
 }
 
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
-{
-   return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
-   color_plane == 1;
-}
-
 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
@@ -1019,11 +1013,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
struct drm_i915_private *i915 = to_i915(fb->dev);
unsigned int height, alignment, unused;
 
-   if (DISPLAY_VER(i915) >= 12 &&
-   !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
-   is_semiplanar_uv_plane(fb, color_plane))
-   alignment = intel_tile_row_size(fb, color_plane);
-   else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+   if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
alignment = intel_tile_size(i915);
else
alignment = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h 
b/drivers/gpu/drm/i915/display/intel_fb.h
index 1b1fef2dc39a..6dee0c8b7f22 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,7 +34,6 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
 bool intel_fb_is_mc_ccs_modifier(u64 modifier);
 
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int 
color_plane);
 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ca7fc9fae990..476f5b7d9497 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -514,17 +514,6 @@ static u32 tgl_plane_min_alignment(struct intel_plane 
*plane,
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return mult * 4 * 1024;
 
-   if (is_semiplanar_uv_plane(fb, color_plane)) {
-   /*
-* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
-* alignment for linear UV planes on all platforms.
-*/
-   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
-   return 256 * 1024;
-
-   return intel_tile_row_size(fb, color_plane);
-   }
-
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
-- 
2.43.2

[PATCH 8/9] drm/i915: Update plane alignment requirements for TGL+

[Ville Syrjala]

From: Ville Syrjälä 

Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.

Signed-off-by: Ville Syrjälä 
---
 .../drm/i915/display/skl_universal_plane.c| 103 ++
 1 file changed, 55 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1ecd7c691317..ca7fc9fae990 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -502,75 +502,79 @@ skl_plane_max_stride(struct intel_plane *plane,
max_pixels, max_bytes);
 }
 
-static unsigned int skl_plane_min_alignment(struct intel_plane *plane,
-   const struct drm_framebuffer *fb,
-   int color_plane)
+static u32 tgl_plane_min_alignment(struct intel_plane *plane,
+  const struct drm_framebuffer *fb,
+  int color_plane)
 {
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
-   if (intel_fb_uses_dpt(fb)) {
-   /* AUX_DIST needs only 4K alignment */
-   if (intel_fb_is_ccs_aux_plane(fb, color_plane))
-   return 512 * 4096;
-
-   /*
-* FIXME ADL sees GGTT/DMAR faults with async
-* flips unless we align to 16k at least.
-* Figure out what's going on here...
-*/
-   if (IS_ALDERLAKE_P(dev_priv) &&
-   !intel_fb_is_ccs_modifier(fb->modifier) &&
-   HAS_ASYNC_FLIPS(dev_priv))
-   return 512 * 16 * 1024;
-
-   return 512 * 4096;
-   }
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+   /* PLANE_SURF GGTT -> DPT alignment */
+   int mult = intel_fb_uses_dpt(fb) ? 512 : 1;
 
/* AUX_DIST needs only 4K alignment */
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
-   return 4096;
+   return mult * 4 * 1024;
 
if (is_semiplanar_uv_plane(fb, color_plane)) {
/*
 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
 * alignment for linear UV planes on all platforms.
 */
-   if (DISPLAY_VER(dev_priv) >= 12) {
-   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
-   return 256 * 1024;
-
-   return intel_tile_row_size(fb, color_plane);
-   }
-
-   return 4096;
-   }
-
-   drm_WARN_ON(_priv->drm, color_plane != 0);
-
-   switch (fb->modifier) {
-   case DRM_FORMAT_MOD_LINEAR:
-   return 256 * 1024;
-   case I915_FORMAT_MOD_X_TILED:
-   if (HAS_ASYNC_FLIPS(dev_priv))
+   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 256 * 1024;
-   return 0;
+
+   return intel_tile_row_size(fb, color_plane);
+   }
+
+   switch (fb->modifier) {
+   case DRM_FORMAT_MOD_LINEAR:
+   case I915_FORMAT_MOD_X_TILED:
+   case I915_FORMAT_MOD_Y_TILED:
+   case I915_FORMAT_MOD_4_TILED:
+   /*
+* FIXME ADL sees GGTT/DMAR faults with async
+* flips unless we align to 16k at least.
+* Figure out what's going on here...
+*/
+   if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915))
+   return mult * 16 * 1024;
+   return mult * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+   case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
-   return 16 * 1024;
+   /* 4x1 main surface tiles (16K) match 64B of AUX */
+   return max(mult * 4 * 1024, 16 * 1024);
+   default:
+   MISSING_CASE(fb->modifier);
+   return 0;
+   }
+}
+
+static u32 skl_plane_min_alignment(struct intel_plane *plane,
+  const struct drm_framebuffer *fb,
+  int color_plane)
+{
+   /*
+* AUX_DIST needs only 4K alignment,
+* as does ICL UV PLANE_SURF.
+*/
+   if (color_plane != 0)
+   return 4 * 1024;
+
+   switch (fb->modifier) {
+   case DRM_FORMAT_MOD_LINEAR:
+   case 

[PATCH 7/9] drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c

[Ville Syrjala]

From: Ville Syrjälä 

Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb.c   | 77 +--
 drivers/gpu/drm/i915/display/intel_fb.h   |  4 +-
 .../drm/i915/display/skl_universal_plane.c| 77 ++-
 3 files changed, 78 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index eea93d84a16e..c80f866f3fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -584,7 +584,7 @@ static bool is_gen12_ccs_cc_plane(const struct 
drm_framebuffer *fb, int color_pl
return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
 }
 
-static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int 
color_plane)
+bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
 {
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
@@ -776,81 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
-unsigned int intel_surf_alignment(struct intel_plane *plane,
- const struct drm_framebuffer *fb,
- int color_plane)
-{
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
-   if (intel_fb_uses_dpt(fb)) {
-   /* AUX_DIST needs only 4K alignment */
-   if (intel_fb_is_ccs_aux_plane(fb, color_plane))
-   return 512 * 4096;
-
-   /*
-* FIXME ADL sees GGTT/DMAR faults with async
-* flips unless we align to 16k at least.
-* Figure out what's going on here...
-*/
-   if (IS_ALDERLAKE_P(dev_priv) &&
-   !intel_fb_is_ccs_modifier(fb->modifier) &&
-   HAS_ASYNC_FLIPS(dev_priv))
-   return 512 * 16 * 1024;
-
-   return 512 * 4096;
-   }
-
-   /* AUX_DIST needs only 4K alignment */
-   if (intel_fb_is_ccs_aux_plane(fb, color_plane))
-   return 4096;
-
-   if (is_semiplanar_uv_plane(fb, color_plane)) {
-   /*
-* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
-* alignment for linear UV planes on all platforms.
-*/
-   if (DISPLAY_VER(dev_priv) >= 12) {
-   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
-   return 256 * 1024;
-
-   return intel_tile_row_size(fb, color_plane);
-   }
-
-   return 4096;
-   }
-
-   drm_WARN_ON(_priv->drm, color_plane != 0);
-
-   switch (fb->modifier) {
-   case DRM_FORMAT_MOD_LINEAR:
-   return 256 * 1024;
-   case I915_FORMAT_MOD_X_TILED:
-   if (HAS_ASYNC_FLIPS(dev_priv))
-   return 256 * 1024;
-   return 0;
-   case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
-   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
-   case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
-   case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
-   case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
-   case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
-   return 16 * 1024;
-   case I915_FORMAT_MOD_Y_TILED_CCS:
-   case I915_FORMAT_MOD_Yf_TILED_CCS:
-   case I915_FORMAT_MOD_Y_TILED:
-   case I915_FORMAT_MOD_4_TILED:
-   case I915_FORMAT_MOD_Yf_TILED:
-   return 1 * 1024 * 1024;
-   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
-   case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
-   case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
-   return 16 * 1024;
-   default:
-   MISSING_CASE(fb->modifier);
-   return 0;
-   }
-}
-
 void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
const struct drm_framebuffer *fb,
int color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h 
b/drivers/gpu/drm/i915/display/intel_fb.h
index 16ebb573643f..1b1fef2dc39a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
 bool intel_fb_is_mc_ccs_modifier(u64 modifier);
 
+bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int 
color_plane);
 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
 
@@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer 

[PATCH 6/9] drm/i915: Split pre-skl platforms out from intel_surf_alignment()

[Ville Syrjala]

From: Ville Syrjälä 

Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c   | 69 -
 drivers/gpu/drm/i915/display/intel_fb.c | 17 +
 drivers/gpu/drm/i915/display/intel_sprite.c | 28 -
 3 files changed, 96 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 85dbf5b950e2..0d64176c1e6f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -762,6 +762,66 @@ i8xx_plane_max_stride(struct intel_plane *plane,
return 8 * 1024;
 }
 
+static unsigned int vlv_primary_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+   switch (fb->modifier) {
+   case I915_FORMAT_MOD_X_TILED:
+   if (HAS_ASYNC_FLIPS(i915))
+   return 256 * 1024;
+   return 4 * 1024;
+   case DRM_FORMAT_MOD_LINEAR:
+   return 128 * 1024;
+   default:
+   MISSING_CASE(fb->modifier);
+   return 0;
+   }
+}
+
+static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+   switch (fb->modifier) {
+   case I915_FORMAT_MOD_X_TILED:
+   if (HAS_ASYNC_FLIPS(i915))
+   return 256 * 1024;
+   return 4 * 1024;
+   case DRM_FORMAT_MOD_LINEAR:
+   return 4 * 1024;
+   default:
+   MISSING_CASE(fb->modifier);
+   return 0;
+   }
+}
+
+static unsigned int i965_plane_min_alignment(struct intel_plane *plane,
+const struct drm_framebuffer *fb,
+int color_plane)
+{
+   switch (fb->modifier) {
+   case I915_FORMAT_MOD_X_TILED:
+   return 4 * 1024;
+   case DRM_FORMAT_MOD_LINEAR:
+   return 128 * 1024;
+   default:
+   MISSING_CASE(fb->modifier);
+   return 0;
+   }
+}
+
+static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane,
+const struct drm_framebuffer *fb,
+int color_plane)
+{
+   return 0;
+}
+
 static const struct drm_plane_funcs i965_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -867,7 +927,14 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
 
-   plane->min_alignment = intel_surf_alignment;
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   plane->min_alignment = vlv_primary_min_alignment;
+   else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
+   plane->min_alignment = g4x_primary_min_alignment;
+   else if (DISPLAY_VER(dev_priv) == 4)
+   plane->min_alignment = i965_plane_min_alignment;
+   else
+   plane->min_alignment = i9xx_plane_min_alignment;
 
if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
plane->update_arm = i830_plane_update_arm;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index c84ecae3a57c..eea93d84a16e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -776,19 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
-static unsigned int intel_linear_alignment(const struct drm_i915_private 
*dev_priv)
-{
-   if (DISPLAY_VER(dev_priv) >= 9)
-   return 256 * 1024;
-   else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
-IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-   return 128 * 1024;
-   else if (DISPLAY_VER(dev_priv) >= 4)
-   return 4 * 1024;
-   else
-   return 0;
-}
-
 unsigned int intel_surf_alignment(struct intel_plane *plane,
  const struct drm_framebuffer *fb,
  int color_plane)
@@ -824,7 +811,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane,
 */
if (DISPLAY_VER(dev_priv) >= 12) {
if (fb->modifier == 

[PATCH 5/9] drm/i915: Split cursor alignment to per-platform vfuncs

[Ville Syrjala]

From: Ville Syrjälä 

Split intel_cursor_alignment() into per-platform variants.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
 drivers/gpu/drm/i915/display/intel_fb.c | 16 -
 drivers/gpu/drm/i915/display/intel_fb.h |  3 --
 3 files changed, 38 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 026975f569a7..737d53c50901 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -193,6 +193,13 @@ i845_cursor_max_stride(struct intel_plane *plane,
return 2048;
 }
 
+static unsigned int i845_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   return 32;
+}
+
 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
u32 cntl = 0;
@@ -343,6 +350,28 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
return plane->base.dev->mode_config.cursor_width * 4;
 }
 
+static unsigned int i830_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." 
*/
+   return 16 * 1024; /* physical */
+}
+
+static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   return 256; /* physical */
+}
+
+static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+   return 4 * 1024; /* physical for i915/i945 */
+}
+
 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -884,20 +913,27 @@ intel_cursor_plane_create(struct drm_i915_private 
*dev_priv,
 
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
cursor->max_stride = i845_cursor_max_stride;
+   cursor->min_alignment = i845_cursor_min_alignment;
cursor->update_arm = i845_cursor_update_arm;
cursor->disable_arm = i845_cursor_disable_arm;
cursor->get_hw_state = i845_cursor_get_hw_state;
cursor->check_plane = i845_check_cursor;
} else {
cursor->max_stride = i9xx_cursor_max_stride;
+
+   if (IS_I830(dev_priv))
+   cursor->min_alignment = i830_cursor_min_alignment;
+   else if (IS_I85X(dev_priv))
+   cursor->min_alignment = i85x_cursor_min_alignment;
+   else
+   cursor->min_alignment = i9xx_cursor_min_alignment;
+
cursor->update_arm = i9xx_cursor_update_arm;
cursor->disable_arm = i9xx_cursor_disable_arm;
cursor->get_hw_state = i9xx_cursor_get_hw_state;
cursor->check_plane = i9xx_check_cursor;
}
 
-   cursor->min_alignment = intel_cursor_alignment;
-
cursor->cursor.base = ~0;
cursor->cursor.cntl = ~0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index c5bae05cbbc3..c84ecae3a57c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -776,22 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
-unsigned int intel_cursor_alignment(struct intel_plane *plane,
-   const struct drm_framebuffer *fb,
-   int color_plane)
-{
-   struct drm_i915_private *i915 = to_i915(plane->base.dev);
-
-   if (IS_I830(i915))
-   return 16 * 1024;
-   else if (IS_I85X(i915))
-   return 256;
-   else if (IS_I845G(i915) || IS_I865G(i915))
-   return 32;
-   else
-   return 4 * 1024;
-}
-
 static unsigned int intel_linear_alignment(const struct drm_i915_private 
*dev_priv)
 {
if (DISPLAY_VER(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h 
b/drivers/gpu/drm/i915/display/intel_fb.h
index 86c01a3ce81e..16ebb573643f 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -60,9 +60,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer 
*fb, int color_plane
 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int 
color_plane);
 unsigned int 

[PATCH 4/9] drm/i915: Introduce fb->min_alignment

[Ville Syrjala]

From: Ville Syrjälä 

Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment used when pinning the normal ggtt
view is satisfactory to all those planes.

When pinning per-plane views we only have to satisfy the
alignment requirements of the specific plane.

Signed-off-by: Ville Syrjälä 
---
 .../drm/i915/display/intel_display_types.h|  2 ++
 drivers/gpu/drm/i915/display/intel_fb.c   | 23 
 drivers/gpu/drm/i915/display/intel_fb_pin.c   | 27 +--
 drivers/gpu/drm/i915/display/intel_fbdev.c| 18 +
 4 files changed, 51 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40d6e5f4c350..58bb65832adf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -145,6 +145,8 @@ struct intel_framebuffer {
};
 
struct i915_address_space *dpt_vm;
+
+   unsigned int min_alignment;
 };
 
 enum intel_hotplug_state {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index 3f3a9cd534f4..c5bae05cbbc3 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -10,6 +10,7 @@
 #include 
 
 #include "i915_drv.h"
+#include "intel_atomic_plane.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
 #include "intel_dpt.h"
@@ -1616,6 +1617,26 @@ bool intel_fb_supports_90_270_rotation(const struct 
intel_framebuffer *fb)
   fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
 }
 
+static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb)
+{
+   struct drm_i915_private *i915 = to_i915(fb->dev);
+   struct intel_plane *plane;
+   unsigned int min_alignment = 0;
+
+   for_each_intel_plane(>drm, plane) {
+   if (!drm_plane_has_format(>base, fb->format->format, 
fb->modifier))
+   continue;
+
+   if (intel_plane_needs_physical(plane))
+   continue;
+
+   min_alignment = max(min_alignment,
+   plane->min_alignment(plane, fb, 0));
+   }
+
+   return min_alignment;
+}
+
 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer 
*fb)
 {
struct drm_i915_gem_object *obj = intel_fb_obj(>base);
@@ -1698,6 +1719,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915, 
struct intel_framebuffer *
return -EINVAL;
}
 
+   fb->min_alignment = intel_fb_min_alignment(>base);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c 
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 9b0f1ea41b70..1ae02de906f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -230,13 +230,36 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned 
long flags)
i915_vma_put(vma);
 }
 
+static bool gtt_view_is_per_plane(const struct intel_plane_state *plane_state)
+{
+   const struct intel_framebuffer *fb = 
to_intel_framebuffer(plane_state->hw.fb);
+
+   if (plane_state->view.gtt.type == I915_GTT_VIEW_REMAPPED &&
+   intel_fb_needs_pot_stride_remap(fb))
+   return false;
+
+   return plane_state->view.gtt.type != I915_GTT_VIEW_NORMAL;
+}
+
 static unsigned int
 intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
 {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-   const struct drm_framebuffer *fb = plane_state->hw.fb;
+   const struct intel_framebuffer *fb = 
to_intel_framebuffer(plane_state->hw.fb);
 
-   return plane->min_alignment(plane, fb, 0);
+   /*
+* Only use plane specific alignment for binding
+* a per-plane gtt view (remapped or rotated),
+* otherwise make sure the alignment is suitable
+* for all planes.
+*/
+   if (!gtt_view_is_per_plane(plane_state))
+   return fb->min_alignment;
+
+   if (intel_plane_needs_physical(plane))
+   return 0;
+
+   return plane->min_alignment(plane, >base, 0);
 }
 
 static unsigned int
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index ff685aebbd1a..124aac172acb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -46,7 +46,6 @@
 #include "gem/i915_gem_mman.h"
 
 #include "i915_drv.h"
-#include "intel_crtc.h"
 #include "intel_display_types.h"
 #include "intel_fb.h"
 #include "intel_fb_pin.h"
@@ -172,21 +171,6 @@ static const struct fb_ops intelfb_ops = {
 
 __diag_pop();
 
-static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb)
-{
-   

[PATCH 3/9] drm/i915: Introduce plane->min_alignment() vfunc

[Ville Syrjala]

From: Ville Syrjälä 

Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.

For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment() functions.

For fbdev we (temporarily) introduce intel_fbdev_min_alignment()
that simply queries the alignment from the primary plane of
the first crtc.

TODO: someone will need to fix xe's alignment handling

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c |  8 ++--
 drivers/gpu/drm/i915/display/intel_cursor.c   |  2 +
 .../drm/i915/display/intel_display_types.h|  3 ++
 drivers/gpu/drm/i915/display/intel_fb.c   | 22 +-
 drivers/gpu/drm/i915/display/intel_fb.h   |  7 +++-
 drivers/gpu/drm/i915/display/intel_fb_pin.c   | 40 ++-
 drivers/gpu/drm/i915/display/intel_fb_pin.h   |  3 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c| 21 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +
 .../drm/i915/display/skl_universal_plane.c| 11 +++--
 drivers/gpu/drm/xe/display/xe_fb_pin.c|  3 +-
 drivers/gpu/drm/xe/display/xe_plane_initial.c |  4 +-
 12 files changed, 89 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ea4d8ba55ad8..85dbf5b950e2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -224,8 +224,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 {
-   struct drm_i915_private *dev_priv =
-   to_i915(plane_state->uapi.plane->dev);
+   struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int src_x, src_y, src_w;
u32 offset;
@@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state 
*plane_state)
 * despite them not using the linear offset anymore.
 */
if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == 
I915_FORMAT_MOD_X_TILED) {
-   unsigned int alignment = intel_surf_alignment(fb, 0);
+   unsigned int alignment = plane->min_alignment(plane, fb, 0);
int cpp = fb->format->cpp[0];
 
while ((src_x + src_w) * cpp > 
plane_state->view.color_plane[0].mapping_stride) {
@@ -867,6 +867,8 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
 
+   plane->min_alignment = intel_surf_alignment;
+
if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
plane->update_arm = i830_plane_update_arm;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2118b87ccb10..026975f569a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -896,6 +896,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
cursor->check_plane = i9xx_check_cursor;
}
 
+   cursor->min_alignment = intel_cursor_alignment;
+
cursor->cursor.base = ~0;
cursor->cursor.cntl = ~0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index fec3de25ea54..40d6e5f4c350 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1550,6 +1550,9 @@ struct intel_plane {
int (*max_height)(const struct drm_framebuffer *fb,
  int color_plane,
  unsigned int rotation);
+   unsigned int (*min_alignment)(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane);
unsigned int (*max_stride)(struct intel_plane *plane,
   u32 pixel_format, u64 modifier,
   unsigned int rotation);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index b6638726949d..3f3a9cd534f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -775,8 +775,12 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
-unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
+unsigned int intel_cursor_alignment(struct intel_plane *plane,
+   const struct drm_framebuffer *fb,
+   int color_plane)
 {
+   struct 

[PATCH 1/9] drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()

[Ville Syrjala]

From: Ville Syrjälä 

Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.

Also matches drm_any_plane_has_format() better.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c|  7 ++-
 drivers/gpu/drm/drm_crtc.c  |  6 ++
 drivers/gpu/drm/drm_crtc_internal.h |  4 ++--
 drivers/gpu/drm/drm_plane.c | 22 ++
 4 files changed, 16 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index a91737adf8e7..e22560213b8e 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -608,7 +608,6 @@ static int drm_atomic_plane_check(const struct 
drm_plane_state *old_plane_state,
unsigned int fb_width, fb_height;
struct drm_mode_rect *clips;
uint32_t num_clips;
-   int ret;
 
/* either *both* CRTC and FB must be set, or neither */
if (crtc && !fb) {
@@ -635,14 +634,12 @@ static int drm_atomic_plane_check(const struct 
drm_plane_state *old_plane_state,
}
 
/* Check whether this plane supports the fb pixel format. */
-   ret = drm_plane_check_pixel_format(plane, fb->format->format,
-  fb->modifier);
-   if (ret) {
+   if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {
drm_dbg_atomic(plane->dev,
   "[PLANE:%d:%s] invalid pixel format %p4cc, 
modifier 0x%llx\n",
   plane->base.id, plane->name,
   >format->format, fb->modifier);
-   return ret;
+   return -EINVAL;
}
 
/* Give drivers some help against integer overflows */
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 483969b84a30..3488ff067c69 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -789,12 +789,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 * case.
 */
if (!plane->format_default) {
-   ret = drm_plane_check_pixel_format(plane,
-  fb->format->format,
-  fb->modifier);
-   if (ret) {
+   if (!drm_plane_has_format(plane, fb->format->format, 
fb->modifier)) {
drm_dbg_kms(dev, "Invalid pixel format %p4cc, 
modifier 0x%llx\n",
>format->format, fb->modifier);
+   ret = -EINVAL;
goto out;
}
}
diff --git a/drivers/gpu/drm/drm_crtc_internal.h 
b/drivers/gpu/drm/drm_crtc_internal.h
index 25aaae937ceb..898e0e8b51be 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -272,8 +272,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
 /* drm_plane.c */
 int drm_plane_register_all(struct drm_device *dev);
 void drm_plane_unregister_all(struct drm_device *dev);
-int drm_plane_check_pixel_format(struct drm_plane *plane,
-u32 format, u64 modifier);
+bool drm_plane_has_format(struct drm_plane *plane,
+ u32 format, u64 modifier);
 struct drm_mode_rect *
 __drm_plane_get_damage_clips(const struct drm_plane_state *state);
 
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 57662a1fd345..268aa2299df5 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -877,8 +877,8 @@ int drm_mode_getplane(struct drm_device *dev, void *data,
return 0;
 }
 
-int drm_plane_check_pixel_format(struct drm_plane *plane,
-u32 format, u64 modifier)
+bool drm_plane_has_format(struct drm_plane *plane,
+ u32 format, u64 modifier)
 {
unsigned int i;
 
@@ -887,24 +887,24 @@ int drm_plane_check_pixel_format(struct drm_plane *plane,
break;
}
if (i == plane->format_count)
-   return -EINVAL;
+   return false;
 
if (plane->funcs->format_mod_supported) {
if (!plane->funcs->format_mod_supported(plane, format, 
modifier))
-   return -EINVAL;
+   return false;
} else {
if (!plane->modifier_count)
-   return 0;
+   return true;
 
for (i = 0; i < plane->modifier_count; i++) {
if (modifier == plane->modifiers[i])
break;
}
if (i == plane->modifier_count)
-   return -EINVAL;
+   return false;
}
 
-   return 0;
+   

[PATCH 2/9] drm: Export drm_plane_has_format()

[Ville Syrjala]

From: Ville Syrjälä 

Export drm_plane_has_format() so that drivers can use it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_crtc_internal.h | 2 --
 drivers/gpu/drm/drm_plane.c | 1 +
 include/drm/drm_plane.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_internal.h 
b/drivers/gpu/drm/drm_crtc_internal.h
index 898e0e8b51be..e207759ca045 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -272,8 +272,6 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
 /* drm_plane.c */
 int drm_plane_register_all(struct drm_device *dev);
 void drm_plane_unregister_all(struct drm_device *dev);
-bool drm_plane_has_format(struct drm_plane *plane,
- u32 format, u64 modifier);
 struct drm_mode_rect *
 __drm_plane_get_damage_clips(const struct drm_plane_state *state);
 
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 268aa2299df5..a51d4dd3f7de 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -906,6 +906,7 @@ bool drm_plane_has_format(struct drm_plane *plane,
 
return true;
 }
+EXPORT_SYMBOL(drm_plane_has_format);
 
 static int __setplane_check(struct drm_plane *plane,
struct drm_crtc *crtc,
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 9507542121fa..dd718c62ac31 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -972,6 +972,8 @@ static inline struct drm_plane *drm_plane_find(struct 
drm_device *dev,
 #define drm_for_each_plane(plane, dev) \
list_for_each_entry(plane, &(dev)->mode_config.plane_list, head)
 
+bool drm_plane_has_format(struct drm_plane *plane,
+ u32 format, u64 modifier);
 bool drm_any_plane_has_format(struct drm_device *dev,
  u32 format, u64 modifier);
 
-- 
2.43.2

[PATCH 0/9] drm/i915: Polish plane surface alignment handling

[Ville Syrjala]

From: Ville Syrjälä 

intel_surf_alignment() in particular has devolved into
a complete mess. Redesign the code so that we can handle
alignment restrictions in a nicer. Also adjust alignment
for TGL+ to actually match the hardware requirements.

Ville Syrjälä (9):
  drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()
  drm: Export drm_plane_has_format()
  drm/i915: Introduce plane->min_alignment() vfunc
  drm/i915: Introduce fb->min_alignment
  drm/i915: Split cursor alignment to per-platform vfuncs
  drm/i915: Split pre-skl platforms out from intel_surf_alignment()
  drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c
  drm/i915: Update plane alignment requirements for TGL+
  drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff

 drivers/gpu/drm/drm_atomic.c  |   7 +-
 drivers/gpu/drm/drm_crtc.c|   6 +-
 drivers/gpu/drm/drm_crtc_internal.h   |   2 -
 drivers/gpu/drm/drm_plane.c   |  23 ++-
 drivers/gpu/drm/i915/display/i9xx_plane.c |  75 -
 drivers/gpu/drm/i915/display/intel_cursor.c   |  38 +
 .../drm/i915/display/intel_display_types.h|   5 +
 drivers/gpu/drm/i915/display/intel_fb.c   | 145 --
 drivers/gpu/drm/i915/display/intel_fb.h   |   3 -
 drivers/gpu/drm/i915/display/intel_fb_pin.c   |  63 ++--
 drivers/gpu/drm/i915/display/intel_fb_pin.h   |   3 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c|   5 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  26 
 .../drm/i915/display/skl_universal_plane.c|  82 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c|   3 +-
 drivers/gpu/drm/xe/display/xe_plane_initial.c |   4 +-
 include/drm/drm_plane.h   |   2 +
 17 files changed, 324 insertions(+), 168 deletions(-)

-- 
2.43.2

[PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations

[Ville Syrjala]

From: Ville Syrjälä 

Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro

v2: Rebase

Signed-off-by: Ville Syrjälä 
---
 .../i915/display/skl_universal_plane_regs.h   | 185 +-
 1 file changed, 93 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0b4f97059479..cb3bdd71b6b2 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -8,13 +8,22 @@
 
 #include "intel_display_reg_defs.h"
 
+#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), 
(reg_2_a), (reg_2_b)))
+#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), 
(reg_2_b)) + (dw) * 4)
+#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), 
(reg_2_b)))
+#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, 
reg_2_b) \
+   _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), 
(reg_2_a), (reg_2_b)))
+
 #define _PLANE_CTL_1_A 0x70180
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_1_B 0x71180
 #define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, 
_PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), 
_PLANE_CTL_2(pipe))
+#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_CTL_1_A, 
_PLANE_CTL_1_B, \
+   _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
 #define   PLANE_CTL_ENABLE REG_BIT(31)
 #define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
 #define   PLANE_CTL_ARB_SLOTS(x)   
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -83,9 +92,9 @@
 #define _PLANE_STRIDE_2_A  0x70288
 #define _PLANE_STRIDE_1_B  0x71188
 #define _PLANE_STRIDE_2_B  0x71288
-#define _PLANE_STRIDE_1(pipe)  _PIPE(pipe, _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe)  _PIPE(pipe, _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane)  _MMIO_PLANE(plane, 
_PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE(pipe, plane)  _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B, \
+   _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
 #define   PLANE_STRIDE__MASK   REG_GENMASK(11, 0)
 #define   PLANE_STRIDE_(stride)
REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
 
@@ -93,9 +102,9 @@
 #define _PLANE_POS_2_A 0x7028c
 #define _PLANE_POS_1_B 0x7118c
 #define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, 
_PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, 
_PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), 
_PLANE_POS_2(pipe))
+#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_POS_1_A, 
_PLANE_POS_1_B, \
+   _PLANE_POS_2_A, 
_PLANE_POS_2_B)
 #define   PLANE_POS_Y_MASK REG_GENMASK(31, 16)
 #define   PLANE_POS_Y(y)   
REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
 #define   PLANE_POS_X_MASK REG_GENMASK(15, 0)
@@ -105,9 +114,9 @@
 #define _PLANE_SIZE_2_A0x70290
 #define _PLANE_SIZE_1_B0x71190
 #define _PLANE_SIZE_2_B0x71290
-#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, 
_PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, 
_PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, 
_PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+#define PLANE_SIZE(pipe, plane)_MMIO_SKL_PLANE((pipe), 
(plane), \
+

[PATCH v2 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines

[Ville Syrjala]

From: Ville Syrjälä 

A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.

v2: Rebase

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index e8d399592fd3..0b4f97059479 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -205,17 +205,17 @@
 #define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, 
_PLANE_CUS_CTL_2_B)
 #define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, 
_PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
 #define   PLANE_CUS_ENABLE REG_BIT(31)
-#define   PLANE_CUS_Y_PLANE_MASK   REG_BIT(30)
+#define   PLANE_CUS_Y_PLANE_MASK   REG_BIT(30)
 #define   PLANE_CUS_Y_PLANE_4_RKL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_5_RKL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
 #define   PLANE_CUS_Y_PLANE_6_ICL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_7_ICL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE   REG_BIT(19)
+#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE   REG_BIT(19)
 #define   PLANE_CUS_HPHASE_MASKREG_GENMASK(17, 16)
 #define   PLANE_CUS_HPHASE_0   
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
 #define   PLANE_CUS_HPHASE_0_25
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
 #define   PLANE_CUS_HPHASE_0_5 
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE   REG_BIT(15)
+#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE   REG_BIT(15)
 #define   PLANE_CUS_VPHASE_MASKREG_GENMASK(13, 12)
 #define   PLANE_CUS_VPHASE_0   
REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
 #define   PLANE_CUS_VPHASE_0_25
REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
-- 
2.43.2

[PATCH v2 11/16] drm/i915: Use REG_BIT for PLANE_WM bits

[Ville Syrjala]

From: Ville Syrjälä 

A couple of PLANE_WM bits were still using the hand
rolled (1<
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 5fcd5898af4f..e8d399592fd3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -307,8 +307,8 @@
 #define _PLANE_WM_2(pipe)  _PIPE(pipe, _PLANE_WM_2_A_0, 
_PLANE_WM_2_B_0)
 #define _PLANE_WM_BASE(pipe, plane)_PLANE(plane, _PLANE_WM_1(pipe), 
_PLANE_WM_2(pipe))
 #define PLANE_WM(pipe, plane, level)   _MMIO(_PLANE_WM_BASE(pipe, plane) + 
((4) * (level)))
-#define   PLANE_WM_EN  (1 << 31)
-#define   PLANE_WM_IGNORE_LINES(1 << 30)
+#define   PLANE_WM_EN  REG_BIT(31)
+#define   PLANE_WM_IGNORE_LINESREG_BIT(30)
 #define   PLANE_WM_LINES_MASK  REG_GENMASK(26, 14)
 #define   PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
 
-- 
2.43.2

[PATCH v2 10/16] drm/i915: Shuffle the skl+ plane register definitions

[Ville Syrjala]

From: Ville Syrjälä 

Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit

v2: Define register contents after all offsets (Jani)

Cc: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 .../i915/display/skl_universal_plane_regs.h   | 481 --
 1 file changed, 200 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 49278584caa7..5fcd5898af4f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -10,6 +10,11 @@
 
 #define _PLANE_CTL_1_A 0x70180
 #define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_1_B 0x71180
+#define _PLANE_CTL_2_B 0x71280
+#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, 
_PLANE_CTL_1_B)
+#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
+#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), 
_PLANE_CTL_2(pipe))
 #define   PLANE_CTL_ENABLE REG_BIT(31)
 #define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
 #define   PLANE_CTL_ARB_SLOTS(x)   
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -73,54 +78,132 @@
 #define   PLANE_CTL_ROTATE_90  
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
 #define   PLANE_CTL_ROTATE_180 
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
 #define   PLANE_CTL_ROTATE_270 
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
+
 #define _PLANE_STRIDE_1_A  0x70188
 #define _PLANE_STRIDE_2_A  0x70288
+#define _PLANE_STRIDE_1_B  0x71188
+#define _PLANE_STRIDE_2_B  0x71288
+#define _PLANE_STRIDE_1(pipe)  _PIPE(pipe, _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B)
+#define _PLANE_STRIDE_2(pipe)  _PIPE(pipe, _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
+#define PLANE_STRIDE(pipe, plane)  _MMIO_PLANE(plane, 
_PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
 #define   PLANE_STRIDE__MASK   REG_GENMASK(11, 0)
 #define   PLANE_STRIDE_(stride)
REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
+
 #define _PLANE_POS_1_A 0x7018c
 #define _PLANE_POS_2_A 0x7028c
+#define _PLANE_POS_1_B 0x7118c
+#define _PLANE_POS_2_B 0x7128c
+#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, 
_PLANE_POS_1_B)
+#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, 
_PLANE_POS_2_B)
+#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), 
_PLANE_POS_2(pipe))
 #define   PLANE_POS_Y_MASK REG_GENMASK(31, 16)
 #define   PLANE_POS_Y(y)   
REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
 #define   PLANE_POS_X_MASK REG_GENMASK(15, 0)
 #define   PLANE_POS_X(x)   
REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
+
 #define _PLANE_SIZE_1_A0x70190
 #define _PLANE_SIZE_2_A0x70290
+#define _PLANE_SIZE_1_B0x71190
+#define _PLANE_SIZE_2_B0x71290
+#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, 
_PLANE_SIZE_1_B)
+#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, 
_PLANE_SIZE_2_B)
+#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, 
_PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
 #define   PLANE_HEIGHT_MASKREG_GENMASK(31, 16)
 #define   PLANE_HEIGHT(h)  
REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
 #define   PLANE_WIDTH_MASK REG_GENMASK(15, 0)
 #define   PLANE_WIDTH(w)   
REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
+
+#define _PLANE_KEYVAL_1_A  0x70194
+#define _PLANE_KEYVAL_2_A  0x70294
+#define _PLANE_KEYVAL_1_B  0x71194
+#define _PLANE_KEYVAL_2_B  0x71294
+#define _PLANE_KEYVAL_1(pipe)  _PIPE(pipe, _PLANE_KEYVAL_1_A, 
_PLANE_KEYVAL_1_B)
+#define _PLANE_KEYVAL_2(pipe)  _PIPE(pipe, _PLANE_KEYVAL_2_A, 
_PLANE_KEYVAL_2_B)
+#define PLANE_KEYVAL(pipe, plane)  _MMIO_PLANE(plane, 
_PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+
+#define _PLANE_KEYMSK_1_A  0x70198
+#define _PLANE_KEYMSK_2_A  0x70298
+#define _PLANE_KEYMSK_1_B  0x71198
+#define _PLANE_KEYMSK_2_B  0x71298
+#define _PLANE_KEYMSK_1(pipe)  _PIPE(pipe, _PLANE_KEYMSK_1_A, 
_PLANE_KEYMSK_1_B)
+#define _PLANE_KEYMSK_2(pipe)  

[PATCH v2 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines

[Ville Syrjala]

From: Ville Syrjälä 

We only need register defines for the first two planes
on the first two pipes. Nuke everything else.

v2: Drop a few more that snuck through

Reviewed-by: Jani Nikula  #v1
Signed-off-by: Ville Syrjälä 
---
 .../i915/display/skl_universal_plane_regs.h   | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index d0c760e8..49278584caa7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -10,7 +10,6 @@
 
 #define _PLANE_CTL_1_A 0x70180
 #define _PLANE_CTL_2_A 0x70280
-#define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE REG_BIT(31)
 #define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
 #define   PLANE_CTL_ARB_SLOTS(x)   
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -76,31 +75,26 @@
 #define   PLANE_CTL_ROTATE_270 
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
 #define _PLANE_STRIDE_1_A  0x70188
 #define _PLANE_STRIDE_2_A  0x70288
-#define _PLANE_STRIDE_3_A  0x70388
 #define   PLANE_STRIDE__MASK   REG_GENMASK(11, 0)
 #define   PLANE_STRIDE_(stride)
REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
 #define _PLANE_POS_1_A 0x7018c
 #define _PLANE_POS_2_A 0x7028c
-#define _PLANE_POS_3_A 0x7038c
 #define   PLANE_POS_Y_MASK REG_GENMASK(31, 16)
 #define   PLANE_POS_Y(y)   
REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
 #define   PLANE_POS_X_MASK REG_GENMASK(15, 0)
 #define   PLANE_POS_X(x)   
REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
 #define _PLANE_SIZE_1_A0x70190
 #define _PLANE_SIZE_2_A0x70290
-#define _PLANE_SIZE_3_A0x70390
 #define   PLANE_HEIGHT_MASKREG_GENMASK(31, 16)
 #define   PLANE_HEIGHT(h)  
REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
 #define   PLANE_WIDTH_MASK REG_GENMASK(15, 0)
 #define   PLANE_WIDTH(w)   
REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
 #define _PLANE_SURF_1_A0x7019c
 #define _PLANE_SURF_2_A0x7029c
-#define _PLANE_SURF_3_A0x7039c
 #define   PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
 #define   PLANE_SURF_DECRYPT   REG_BIT(2)
 #define _PLANE_OFFSET_1_A  0x701a4
 #define _PLANE_OFFSET_2_A  0x702a4
-#define _PLANE_OFFSET_3_A  0x703a4
 #define   PLANE_OFFSET_Y_MASK  REG_GENMASK(31, 16)
 #define   PLANE_OFFSET_Y(y)
REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
 #define   PLANE_OFFSET_X_MASK  REG_GENMASK(15, 0)
@@ -145,7 +139,6 @@
 #define   PLANE_CUS_VPHASE_0_5 
REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
 #define _PLANE_COLOR_CTL_1_A   0x701CC /* GLK+ */
 #define _PLANE_COLOR_CTL_2_A   0x702CC /* GLK+ */
-#define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLEREG_BIT(30) /* 
Pre-ICL */
 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  REG_BIT(23) /* Pre-ICL 
*/
@@ -234,49 +227,38 @@
 
 #define _PLANE_CTL_1_B 0x71180
 #define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_3_B 0x71380
 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
 #define PLANE_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
 
 #define _PLANE_STRIDE_1_B  0x71188
 #define _PLANE_STRIDE_2_B  0x71288
-#define _PLANE_STRIDE_3_B  0x71388
 #define _PLANE_STRIDE_1(pipe)  \
_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
 #define _PLANE_STRIDE_2(pipe)  \
_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define _PLANE_STRIDE_3(pipe)  \
-   _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
 #define PLANE_STRIDE(pipe, plane)  \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
 
 #define _PLANE_POS_1_B 0x7118c
 #define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_3_B 

[PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers

[Ville Syrjala]

From: Ville Syrjälä 

Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.

The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c   | 32 +++
 .../drm/i915/display/skl_universal_plane.c| 60 
 .../drm/i915/display/skl_universal_plane.h|  5 +
 drivers/gpu/drm/i915/display/skl_watermark.c  | 95 +--
 drivers/gpu/drm/i915/display/skl_watermark.h  | 13 ++-
 5 files changed, 107 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index d2b459634732..3ecab15d1431 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,6 +24,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vblank.h"
+#include "skl_universal_plane.h"
 #include "skl_watermark.h"
 
 #include "gem/i915_gem_object.h"
@@ -556,6 +557,37 @@ static void i9xx_cursor_update_sel_fetch_arm(struct 
intel_plane *plane,
}
 }
 
+static void skl_write_cursor_wm(struct intel_plane *plane,
+   const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+   enum plane_id plane_id = plane->id;
+   enum pipe pipe = plane->pipe;
+   const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
+   const struct skl_ddb_entry *ddb =
+   _state->wm.skl.plane_ddb[plane_id];
+   int level;
+
+   for (level = 0; level < i915->display.wm.num_levels; level++)
+   intel_de_write_fw(i915, CUR_WM(pipe, level),
+ 
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+   intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
+
+   if (HAS_HW_SAGV_WM(i915)) {
+   const struct skl_plane_wm *wm = _wm->planes[plane_id];
+
+   intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
+ skl_plane_wm_reg_val(>sagv.wm0));
+   intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
+ skl_plane_wm_reg_val(>sagv.trans_wm));
+   }
+
+   intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
+ skl_plane_ddb_reg_val(ddb));
+}
+
 /* TODO: split into noarm+arm pair */
 static void i9xx_cursor_update_arm(struct intel_plane *plane,
   const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ab560820bb23..a9914cb31631 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -617,6 +617,66 @@ static u32 skl_plane_stride(const struct intel_plane_state 
*plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
 }
 
+u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+   if (!entry->end)
+   return 0;
+
+   return PLANE_BUF_END(entry->end - 1) |
+   PLANE_BUF_START(entry->start);
+}
+
+u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
+{
+   u32 val = 0;
+
+   if (level->enable)
+   val |= PLANE_WM_EN;
+   if (level->ignore_lines)
+   val |= PLANE_WM_IGNORE_LINES;
+   val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
+   val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
+
+   return val;
+}
+
+static void skl_write_plane_wm(struct intel_plane *plane,
+  const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+   enum plane_id plane_id = plane->id;
+   enum pipe pipe = plane->pipe;
+   const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
+   const struct skl_ddb_entry *ddb =
+   _state->wm.skl.plane_ddb[plane_id];
+   const struct skl_ddb_entry *ddb_y =
+   _state->wm.skl.plane_ddb_y[plane_id];
+   int level;
+
+   for (level = 0; level < i915->display.wm.num_levels; level++)
+   intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+ 
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+   intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
+
+   if 

[PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()

[Ville Syrjala]

From: Ville Syrjälä 

Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.

This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.

Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))

@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 57 
 1 file changed, 22 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8a0a26ab8e6a..1daceb8ef9de 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct 
skl_ddb_entry *entry)
PLANE_BUF_START(entry->start);
 }
 
-static void skl_ddb_entry_write(struct drm_i915_private *i915,
-   i915_reg_t reg,
-   const struct skl_ddb_entry *entry)
-{
-   intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
-}
-
 static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
 {
u32 val = 0;
@@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct 
skl_wm_level *level)
return val;
 }
 
-static void skl_write_wm_level(struct drm_i915_private *i915,
-  i915_reg_t reg,
-  const struct skl_wm_level *level)
-{
-   intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
-}
-
 void skl_write_plane_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
 {
@@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
int level;
 
for (level = 0; level < i915->display.wm.num_levels; level++)
-   skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
-  skl_plane_wm_level(pipe_wm, plane_id, 
level));
+   intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+ 
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
 
-   skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
-  skl_plane_trans_wm(pipe_wm, plane_id));
+   intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
 
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
 
-   skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
-  >sagv.wm0);
-   skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
-  >sagv.trans_wm);
+   intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
+ skl_plane_wm_reg_val(>sagv.wm0));
+   intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(>sagv.trans_wm));
}
 
-   skl_ddb_entry_write(i915,
-   PLANE_BUF_CFG(pipe, plane_id), ddb);
+   intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb));
 
if (DISPLAY_VER(i915) < 11)
-   skl_ddb_entry_write(i915,
-   PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
+   intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb_y));
 }
 
 void skl_write_cursor_wm(struct intel_plane *plane,
@@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
int level;
 
for (level = 0; level < i915->display.wm.num_levels; level++)
-   skl_write_wm_level(i915, CUR_WM(pipe, level),
-  skl_plane_wm_level(pipe_wm, plane_id, 
level));
+   intel_de_write_fw(i915, CUR_WM(pipe, level),
+ 
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
 
-   skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
-  skl_plane_trans_wm(pipe_wm, plane_id));
+   intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, 
plane_id)));
 
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
 
-   skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
-  >sagv.wm0);
-   skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
-  >sagv.trans_wm);
+   intel_de_write_fw(i915, 

[PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()

[Ville Syrjala]

From: Ville Syrjälä 

Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 29 +---
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2a2073bf3aca..8a0a26ab8e6a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state 
*state,
return skl_wm_check_vblank(crtc_state);
 }
 
+static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+   if (!entry->end)
+   return 0;
+
+   return PLANE_BUF_END(entry->end - 1) |
+   PLANE_BUF_START(entry->start);
+}
+
 static void skl_ddb_entry_write(struct drm_i915_private *i915,
i915_reg_t reg,
const struct skl_ddb_entry *entry)
 {
-   if (entry->end)
-   intel_de_write_fw(i915, reg,
- PLANE_BUF_END(entry->end - 1) |
- PLANE_BUF_START(entry->start));
-   else
-   intel_de_write_fw(i915, reg, 0);
+   intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
 }
 
-static void skl_write_wm_level(struct drm_i915_private *i915,
-  i915_reg_t reg,
-  const struct skl_wm_level *level)
+static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
 {
u32 val = 0;
 
@@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private 
*i915,
val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
 
-   intel_de_write_fw(i915, reg, val);
+   return val;
+}
+
+static void skl_write_wm_level(struct drm_i915_private *i915,
+  i915_reg_t reg,
+  const struct skl_wm_level *level)
+{
+   intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
 }
 
 void skl_write_plane_wm(struct intel_plane *plane,
-- 
2.43.2

[PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations

[Ville Syrjala]

From: Ville Syrjälä 

Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro

Signed-off-by: Ville Syrjälä 
---
 .../i915/display/skl_universal_plane_regs.h   | 186 +-
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 18dbe717ea21..07bcdf4e195d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -8,6 +8,15 @@
 
 #include "intel_display_reg_defs.h"
 
+#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), 
(reg_2_a), (reg_2_b)))
+#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), 
(reg_2_b)) + (dw) * 4)
+#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+   _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), 
(reg_2_b)))
+#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, 
reg_2_b) \
+   _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), 
(reg_2_a), (reg_2_b)))
+
 #define _PLANE_CTL_1_A 0x70180
 #define   PLANE_CTL_ENABLE REG_BIT(31)
 #define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
@@ -75,9 +84,9 @@
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_1_B 0x71180
 #define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, 
_PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), 
_PLANE_CTL_2(pipe))
+#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_CTL_1_A, 
_PLANE_CTL_1_B, \
+   _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
 
 #define _PLANE_STRIDE_1_A  0x70188
 #define   PLANE_STRIDE__MASK   REG_GENMASK(11, 0)
@@ -85,10 +94,9 @@
 #define _PLANE_STRIDE_2_A  0x70288
 #define _PLANE_STRIDE_1_B  0x71188
 #define _PLANE_STRIDE_2_B  0x71288
-#define _PLANE_STRIDE_1(pipe)  _PIPE(pipe, _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe)  _PIPE(pipe, _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane)  _MMIO_PLANE(plane, 
_PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
+#define PLANE_STRIDE(pipe, plane)  _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B, \
+   _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
 #define _PLANE_POS_1_A 0x7018c
 #define   PLANE_POS_Y_MASK REG_GENMASK(31, 16)
 #define   PLANE_POS_Y(y)   
REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
@@ -97,9 +105,9 @@
 #define _PLANE_POS_2_A 0x7028c
 #define _PLANE_POS_1_B 0x7118c
 #define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, 
_PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, 
_PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), 
_PLANE_POS_2(pipe))
+#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+   _PLANE_POS_1_A, 
_PLANE_POS_1_B, \
+   _PLANE_POS_2_A, 
_PLANE_POS_2_B)
 
 #define _PLANE_SIZE_1_A0x70190
 #define   PLANE_HEIGHT_MASKREG_GENMASK(31, 16)
@@ -109,26 +117,26 @@
 #define _PLANE_SIZE_2_A0x70290
 #define _PLANE_SIZE_1_B0x71190
 #define _PLANE_SIZE_2_B0x71290
-#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, 
_PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, 
_PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, 
_PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+#define PLANE_SIZE(pipe, plane)_MMIO_SKL_PLANE((pipe), 
(plane), \
+   

[PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines

[Ville Syrjala]

From: Ville Syrjälä 

A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 8ef9bd50d021..18dbe717ea21 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -199,17 +199,17 @@
 
 #define _PLANE_CUS_CTL_1_A 0x701c8
 #define   PLANE_CUS_ENABLE REG_BIT(31)
-#define   PLANE_CUS_Y_PLANE_MASK   REG_BIT(30)
+#define   PLANE_CUS_Y_PLANE_MASK   REG_BIT(30)
 #define   PLANE_CUS_Y_PLANE_4_RKL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_5_RKL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
 #define   PLANE_CUS_Y_PLANE_6_ICL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_7_ICL  
REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE   REG_BIT(19)
+#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE   REG_BIT(19)
 #define   PLANE_CUS_HPHASE_MASKREG_GENMASK(17, 16)
 #define   PLANE_CUS_HPHASE_0   
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
 #define   PLANE_CUS_HPHASE_0_25
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
 #define   PLANE_CUS_HPHASE_0_5 
REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE   REG_BIT(15)
+#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE   REG_BIT(15)
 #define   PLANE_CUS_VPHASE_MASKREG_GENMASK(13, 12)
 #define   PLANE_CUS_VPHASE_0   
REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
 #define   PLANE_CUS_VPHASE_0_25
REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
-- 
2.43.2

[PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits

[Ville Syrjala]

From: Ville Syrjälä 

A couple of PLANE_WM bits were still using the hand
rolled (1<
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0ad14727e334..8ef9bd50d021 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -300,8 +300,8 @@
_MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, 
_PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
 
 #define _PLANE_WM_1_A_00x70240
-#define   PLANE_WM_EN  (1 << 31)
-#define   PLANE_WM_IGNORE_LINES(1 << 30)
+#define   PLANE_WM_EN  REG_BIT(31)
+#define   PLANE_WM_IGNORE_LINESREG_BIT(30)
 #define   PLANE_WM_LINES_MASK  REG_GENMASK(26, 14)
 #define   PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
 #define _PLANE_WM_1_B_00x71240
-- 
2.43.2

[PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions

[Ville Syrjala]

From: Ville Syrjälä 

Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit

Signed-off-by: Ville Syrjälä 
---
 .../i915/display/skl_universal_plane_regs.h   | 502 --
 1 file changed, 207 insertions(+), 295 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0558d97614e1..0ad14727e334 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -9,8 +9,6 @@
 #include "intel_display_reg_defs.h"
 
 #define _PLANE_CTL_1_A 0x70180
-#define _PLANE_CTL_2_A 0x70280
-#define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE REG_BIT(31)
 #define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
 #define   PLANE_CTL_ARB_SLOTS(x)   
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -74,59 +72,132 @@
 #define   PLANE_CTL_ROTATE_90  
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
 #define   PLANE_CTL_ROTATE_180 
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
 #define   PLANE_CTL_ROTATE_270 
REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
+#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_1_B 0x71180
+#define _PLANE_CTL_2_B 0x71280
+#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, 
_PLANE_CTL_1_B)
+#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, 
_PLANE_CTL_2_B)
+#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), 
_PLANE_CTL_2(pipe))
+
 #define _PLANE_STRIDE_1_A  0x70188
-#define _PLANE_STRIDE_2_A  0x70288
-#define _PLANE_STRIDE_3_A  0x70388
 #define   PLANE_STRIDE__MASK   REG_GENMASK(11, 0)
 #define   PLANE_STRIDE_(stride)
REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
+#define _PLANE_STRIDE_2_A  0x70288
+#define _PLANE_STRIDE_1_B  0x71188
+#define _PLANE_STRIDE_2_B  0x71288
+#define _PLANE_STRIDE_1(pipe)  _PIPE(pipe, _PLANE_STRIDE_1_A, 
_PLANE_STRIDE_1_B)
+#define _PLANE_STRIDE_2(pipe)  _PIPE(pipe, _PLANE_STRIDE_2_A, 
_PLANE_STRIDE_2_B)
+#define PLANE_STRIDE(pipe, plane)  _MMIO_PLANE(plane, 
_PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+
 #define _PLANE_POS_1_A 0x7018c
-#define _PLANE_POS_2_A 0x7028c
-#define _PLANE_POS_3_A 0x7038c
 #define   PLANE_POS_Y_MASK REG_GENMASK(31, 16)
 #define   PLANE_POS_Y(y)   
REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
 #define   PLANE_POS_X_MASK REG_GENMASK(15, 0)
 #define   PLANE_POS_X(x)   
REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
+#define _PLANE_POS_2_A 0x7028c
+#define _PLANE_POS_1_B 0x7118c
+#define _PLANE_POS_2_B 0x7128c
+#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, 
_PLANE_POS_1_B)
+#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, 
_PLANE_POS_2_B)
+#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), 
_PLANE_POS_2(pipe))
+
 #define _PLANE_SIZE_1_A0x70190
-#define _PLANE_SIZE_2_A0x70290
-#define _PLANE_SIZE_3_A0x70390
 #define   PLANE_HEIGHT_MASKREG_GENMASK(31, 16)
 #define   PLANE_HEIGHT(h)  
REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
 #define   PLANE_WIDTH_MASK REG_GENMASK(15, 0)
 #define   PLANE_WIDTH(w)   
REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
+#define _PLANE_SIZE_2_A0x70290
+#define _PLANE_SIZE_1_B0x71190
+#define _PLANE_SIZE_2_B0x71290
+#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, 
_PLANE_SIZE_1_B)
+#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, 
_PLANE_SIZE_2_B)
+#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, 
_PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+
+#define _PLANE_KEYVAL_1_A  0x70194
+#define _PLANE_KEYVAL_2_A  0x70294
+#define _PLANE_KEYVAL_1_B  0x71194
+#define _PLANE_KEYVAL_2_B  0x71294
+#define _PLANE_KEYVAL_1(pipe)  _PIPE(pipe, _PLANE_KEYVAL_1_A, 
_PLANE_KEYVAL_1_B)
+#define _PLANE_KEYVAL_2(pipe)  _PIPE(pipe, _PLANE_KEYVAL_2_A, 
_PLANE_KEYVAL_2_B)
+#define PLANE_KEYVAL(pipe, plane) 

[PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines

[Ville Syrjala]

From: Ville Syrjälä 

We only need register defines for the first two planes
on the first two pipes. Nuke everything else.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/skl_universal_plane_regs.h  | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index d0c760e8..0558d97614e1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -234,49 +234,38 @@
 
 #define _PLANE_CTL_1_B 0x71180
 #define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_3_B 0x71380
 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
 #define PLANE_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
 
 #define _PLANE_STRIDE_1_B  0x71188
 #define _PLANE_STRIDE_2_B  0x71288
-#define _PLANE_STRIDE_3_B  0x71388
 #define _PLANE_STRIDE_1(pipe)  \
_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
 #define _PLANE_STRIDE_2(pipe)  \
_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define _PLANE_STRIDE_3(pipe)  \
-   _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
 #define PLANE_STRIDE(pipe, plane)  \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
 
 #define _PLANE_POS_1_B 0x7118c
 #define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_3_B 0x7138c
 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
 #define PLANE_POS(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
 
 #define _PLANE_SIZE_1_B0x71190
 #define _PLANE_SIZE_2_B0x71290
-#define _PLANE_SIZE_3_B0x71390
 #define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
 #define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define _PLANE_SIZE_3(pipe)_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
 #define PLANE_SIZE(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
 
 #define _PLANE_SURF_1_B0x7119c
 #define _PLANE_SURF_2_B0x7129c
-#define _PLANE_SURF_3_B0x7139c
 #define _PLANE_SURF_1(pipe)_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
 #define _PLANE_SURF_2(pipe)_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
 #define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
 
@@ -351,7 +340,6 @@
 
 #define _PLANE_COLOR_CTL_1_B   0x711CC
 #define _PLANE_COLOR_CTL_2_B   0x712CC
-#define _PLANE_COLOR_CTL_3_B   0x713CC
 #define _PLANE_COLOR_CTL_1(pipe)   \
_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
 #define _PLANE_COLOR_CTL_2(pipe)   \
-- 
2.43.2

[PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines

[Ville Syrjala]

From: Ville Syrjälä 

Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
and just use the real thing.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index b53c98cd6d7f..843bdb46d49c 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct 
intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
-   MMIO_D(_MMIO(_PLANE_CTL_3_A));
-   MMIO_D(_MMIO(_PLANE_CTL_3_B));
-   MMIO_D(_MMIO(0x72380));
-   MMIO_D(_MMIO(0x7239c));
-   MMIO_D(_MMIO(_PLANE_SURF_3_A));
-   MMIO_D(_MMIO(_PLANE_SURF_3_B));
+   MMIO_D(PLANE_CTL(PIPE_A, 2));
+   MMIO_D(PLANE_CTL(PIPE_B, 2));
+   MMIO_D(PLANE_CTL(PIPE_C, 2));
+   MMIO_D(PLANE_SURF(PIPE_A, 2));
+   MMIO_D(PLANE_SURF(PIPE_B, 2));
+   MMIO_D(PLANE_SURF(PIPE_C, 2));
MMIO_D(DMC_SSP_BASE);
MMIO_D(DMC_HTP_SKL);
MMIO_D(DMC_LAST_WRITE);
-- 
2.43.2

[PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines

[Ville Syrjala]

From: Ville Syrjälä 

Stop hand rolling PLANE_KEY*() register defines and just
use the real thing.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index ad3bf60855bc..b53c98cd6d7f 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct 
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70034));
MMIO_D(_MMIO(0x71034));
MMIO_D(_MMIO(0x72034));
-   MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)));
-   MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)));
-   MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)));
-   MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)));
-   MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)));
-   MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)));
-   MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)));
-   MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)));
-   MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)));
+   MMIO_D(PLANE_KEYVAL(PIPE_A, 0));
+   MMIO_D(PLANE_KEYVAL(PIPE_B, 0));
+   MMIO_D(PLANE_KEYVAL(PIPE_C, 0));
+   MMIO_D(PLANE_KEYMAX(PIPE_A, 0));
+   MMIO_D(PLANE_KEYMAX(PIPE_B, 0));
+   MMIO_D(PLANE_KEYMAX(PIPE_C, 0));
+   MMIO_D(PLANE_KEYMSK(PIPE_A, 0));
+   MMIO_D(PLANE_KEYMSK(PIPE_B, 0));
+   MMIO_D(PLANE_KEYMSK(PIPE_C, 0));
MMIO_D(_MMIO(0x44500));
 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
MMIO_RING_D(CSFE_CHICKEN1_REG);
-- 
2.43.2

[PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define

[Ville Syrjala]

From: Ville Syrjälä 

Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/gvt/handlers.c | 24 ++---
 drivers/gpu/drm/i915/gvt/reg.h  |  2 --
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++---
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 6b02612ddef5..6f633035618e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
 
MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index e8a56faafe95..90d8eb1761a3 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -57,8 +57,6 @@
 
 #define VGT_SPRSTRIDE(pipe)_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
 
-#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
-
 #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + 
(pipe))
 
 #define REG50080_FLIP_TYPE_MASK0x3
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index cf45342a6db0..ad3bf60855bc 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct 
intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
-   MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
+   MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
MMIO_D(_MMIO(_PLANE_CTL_3_A));
MMIO_D(_MMIO(_PLANE_CTL_3_B));
MMIO_D(_MMIO(0x72380));
-- 
2.43.2

[PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define

[Ville Syrjala]

From: Ville Syrjälä 

Stop hand rolling PLANE_AUX_DIST() and just use the real thing.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/gvt/handlers.c | 24 ++---
 drivers/gpu/drm/i915/gvt/reg.h  |  1 -
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++---
 3 files changed, 24 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 6c857beb5083..6b02612ddef5 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
 
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
-   MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+   MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
 
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index d8216c63c39a..e8a56faafe95 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -57,7 +57,6 @@
 
 #define VGT_SPRSTRIDE(pipe)_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
 
-#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
 #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
 
 #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + 
(pipe))
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 3b79c1c84b79..cf45342a6db0 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct 
intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1));
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2));
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3)));
-   MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4)));
+   MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));
+   MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));
+   MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));
+   MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));
+   MMIO_D(PLANE_AUX_DIST(PIPE_B, 0));
+   MMIO_D(PLANE_AUX_DIST(PIPE_B, 1));
+   MMIO_D(PLANE_AUX_DIST(PIPE_B, 2));
+   MMIO_D(PLANE_AUX_DIST(PIPE_B, 3));
+   MMIO_D(PLANE_AUX_DIST(PIPE_C, 0));
+   MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
+   MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
+   MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
-- 
2.43.2

[PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers

[Ville Syrjala]

From: Ville Syrjälä 

On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_cursor_regs.h  | 20 +
 .../i915/display/skl_universal_plane_regs.h   | 64 ++
 drivers/gpu/drm/i915/display/skl_watermark.c  |  1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h | 83 ---
 drivers/gpu/drm/i915/gvt/handlers.c   |  1 +
 5 files changed, 86 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 62f7fb5c3f10..a478ef5787c5 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -75,4 +75,24 @@
 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
 
+/* skl+ */
+#define _CUR_WM_A_00x70140
+#define _CUR_WM_B_00x71140
+#define _CUR_WM_SAGV_A 0x70158
+#define _CUR_WM_SAGV_B 0x71158
+#define _CUR_WM_SAGV_TRANS_A   0x7015C
+#define _CUR_WM_SAGV_TRANS_B   0x7115C
+#define _CUR_WM_TRANS_A0x70168
+#define _CUR_WM_TRANS_B0x71168
+#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
+#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, 
_CUR_WM_SAGV_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
+
+/* skl+ */
+#define _CUR_BUF_CFG_A 0x7017c
+#define _CUR_BUF_CFG_B 0x7117c
+#define CUR_BUF_CFG(pipe)  _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+
 #endif /* __INTEL_CURSOR_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7e34470beb74..d0c760e8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -402,4 +402,68 @@
(index) * 4, 
_PLANE_CSC_POSTOFF_HI_2(pipe) + \
(index) * 4)
 
+#define _PLANE_WM_1_A_00x70240
+#define _PLANE_WM_1_B_00x71240
+#define _PLANE_WM_2_A_00x70340
+#define _PLANE_WM_2_B_00x71340
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A   0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B   0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A   0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B   0x7135C
+#define _PLANE_WM_TRANS_1_A0x70268
+#define _PLANE_WM_TRANS_1_B0x71268
+#define _PLANE_WM_TRANS_2_A0x70368
+#define _PLANE_WM_TRANS_2_B0x71368
+#define   PLANE_WM_EN  (1 << 31)
+#define   PLANE_WM_IGNORE_LINES(1 << 30)
+#define   PLANE_WM_LINES_MASK  REG_GENMASK(26, 14)
+#define   PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
+#define _PLANE_WM_BASE(pipe, plane) \
+   _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) \
+   _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define _PLANE_WM_SAGV_1(pipe) \
+   _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) \
+   _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) \
+   _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1(pipe) \
+   _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) \
+   _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+   _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), 
_PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1(pipe) \
+   _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) \
+   _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) \
+   _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+
+#define _PLANE_BUF_CFG_1_B 0x7127c
+#define _PLANE_BUF_CFG_2_B 0x7137c
+#define _PLANE_BUF_CFG_1(pipe) \
+   _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
+#define _PLANE_BUF_CFG_2(pipe) \
+   _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
+#define 

[PATCH 03/16] drm/i915: Extract intel_cursor_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

Move most cursor register definitions into their own file.
Declutters i915_reg.h a bit more.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cursor.c   |  1 +
 .../gpu/drm/i915/display/intel_cursor_regs.h  | 78 +++
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c  |  1 +
 drivers/gpu/drm/i915/gvt/display.c|  1 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c |  1 +
 drivers/gpu/drm/i915/i915_reg.h   | 70 -
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  1 +
 8 files changed, 84 insertions(+), 70 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2118b87ccb10..d2b459634732 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -14,6 +14,7 @@
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
 #include "intel_cursor.h"
+#include "intel_cursor_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h 
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
new file mode 100644
index ..62f7fb5c3f10
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_CURSOR_REGS_H__
+#define __INTEL_CURSOR_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _CURACNTR  0x70080
+/* Old style CUR*CNTR flags (desktop 8xx) */
+#define   CURSOR_ENABLEREG_BIT(31)
+#define   CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define   CURSOR_STRIDE_MASK   REG_GENMASK(29, 28)
+#define   CURSOR_STRIDE(stride)REG_FIELD_PREP(CURSOR_STRIDE_MASK, 
ffs(stride) - 9) /* 256,512,1k,2k */
+#define   CURSOR_FORMAT_MASK   REG_GENMASK(26, 24)
+#define   CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
+#define   CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
+#define   CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
+#define   CURSOR_FORMAT_ARGB   REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
+#define   CURSOR_FORMAT_XRGB   REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
+/* New style CUR*CNTR flags */
+#define   MCURSOR_ARB_SLOTS_MASK   REG_GENMASK(30, 28) /* icl+ */
+#define   MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, 
(x)) /* icl+ */
+#define   MCURSOR_PIPE_SEL_MASKREG_GENMASK(29, 28)
+#define   MCURSOR_PIPE_SEL(pipe)   REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, 
(pipe))
+#define   MCURSOR_PIPE_GAMMA_ENABLEREG_BIT(26)
+#define   MCURSOR_PIPE_CSC_ENABLE  REG_BIT(24) /* ilk+ */
+#define   MCURSOR_ROTATE_180   REG_BIT(15)
+#define   MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define   MCURSOR_MODE_MASK0x27
+#define   MCURSOR_MODE_DISABLE 0x00
+#define   MCURSOR_MODE_128_32B_AX  0x02
+#define   MCURSOR_MODE_256_32B_AX  0x03
+#define   MCURSOR_MODE_64_2B   0x04
+#define   MCURSOR_MODE_64_32B_AX   0x07
+#define   MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
+#define   MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
+#define   MCURSOR_MODE_64_ARGB_AX  (0x20 | MCURSOR_MODE_64_32B_AX)
+#define _CURABASE  0x70084
+#define _CURAPOS   0x70088
+#define _CURAPOS_ERLY_TPT  0x7008c
+#define   CURSOR_POS_Y_SIGNREG_BIT(31)
+#define   CURSOR_POS_Y_MASKREG_GENMASK(30, 16)
+#define   CURSOR_POS_Y(y)  REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
+#define   CURSOR_POS_X_SIGNREG_BIT(15)
+#define   CURSOR_POS_X_MASKREG_GENMASK(14, 0)
+#define   CURSOR_POS_X(x)  REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+#define _CURASIZE  0x700a0 /* 845/865 */
+#define   CURSOR_HEIGHT_MASK   REG_GENMASK(21, 12)
+#define   CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
+#define   CURSOR_WIDTH_MASKREG_GENMASK(9, 0)
+#define   CURSOR_WIDTH(w)  REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
+#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
+#define   CUR_FBC_EN   REG_BIT(31)
+#define   CUR_FBC_HEIGHT_MASK  REG_GENMASK(7, 0)
+#define   CUR_FBC_HEIGHT(h)REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
+#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
+#define _CURASURFLIVE  0x700ac /* g4x+ */
+#define _CURBCNTR  0x700c0
+#define _CURBBASE  0x700c4
+#define _CURBPOS   0x700c8
+
+#define _CURBCNTR_IVB  0x71080
+#define _CURBBASE_IVB  0x71084
+#define _CURBPOS_IVB   0x71088
+
+#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)

[PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.

Cc: Zhenyu Wang 
CC: Zhi Wang 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../gpu/drm/i915/display/intel_dpt_common.c   |   1 +
 .../drm/i915/display/skl_universal_plane.c|   1 +
 .../i915/display/skl_universal_plane_regs.h   | 405 ++
 drivers/gpu/drm/i915/display/skl_watermark.c  |   1 +
 drivers/gpu/drm/i915/gvt/dmabuf.c |   3 +-
 drivers/gpu/drm/i915/gvt/fb_decoder.c |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 395 -
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
 10 files changed, 414 insertions(+), 396 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b508431..a2c331c696fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -119,6 +119,7 @@
 #include "intel_wm.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
 #include "vlv_dpio_phy_regs.h"
 #include "vlv_dsi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c 
b/drivers/gpu/drm/i915/display/intel_dpt_common.c
index cdba47165c04..573f72068899 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
@@ -7,6 +7,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dpt_common.h"
+#include "skl_universal_plane_regs.h"
 
 void intel_dpt_configure(struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0a8e781a3648..ab560820bb23 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -21,6 +21,7 @@
 #include "intel_psr_regs.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
 #include "pxp/intel_pxp.h"
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
new file mode 100644
index ..7e34470beb74
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
+#define __SKL_UNIVERSAL_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _PLANE_CTL_1_A 0x70180
+#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_3_A 0x70380
+#define   PLANE_CTL_ENABLE REG_BIT(31)
+#define   PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
+#define   PLANE_CTL_ARB_SLOTS(x)   
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  REG_BIT(30) /* Pre-GLK */
+#define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE   REG_BIT(28)
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
+#define   PLANE_CTL_FORMAT_MASK_SKLREG_GENMASK(27, 24) /* pre-icl 
*/
+#define   PLANE_CTL_FORMAT_MASK_ICLREG_GENMASK(27, 23) /* icl+ */
+#define   PLANE_CTL_FORMAT_YUV422  
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+#define   PLANE_CTL_FORMAT_NV12
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+#define   PLANE_CTL_FORMAT_XRGB_2101010
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+#define   PLANE_CTL_FORMAT_P010
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+#define   PLANE_CTL_FORMAT_XRGB_   
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+#define   PLANE_CTL_FORMAT_P012
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+#define   PLANE_CTL_FORMAT_XRGB_16161616F  
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+#define   PLANE_CTL_FORMAT_P016
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+#define   PLANE_CTL_FORMAT_XYUV
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+#define   PLANE_CTL_FORMAT_INDEXED 
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+#define   PLANE_CTL_FORMAT_RGB_565 
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+#define   PLANE_CTL_FORMAT_Y210
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+#define   PLANE_CTL_FORMAT_Y212

[PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC()

[Ville Syrjala]

From: Ville Syrjälä 

_MMIO_PLANE_GAMC() is some leftover macro that is never used.
Get rid of it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 256d73c25701..0f4a2d542d81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5151,8 +5151,6 @@ enum skl_power_gate {
 #define  WM_DBG_DISALLOW_MAXFIFO   (1 << 1)
 #define  WM_DBG_DISALLOW_SPRITE(1 << 2)
 
-#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
-
 /* Plane CSC Registers */
 #define _PLANE_CSC_RY_GY_1_A   0x70210
 #define _PLANE_CSC_RY_GY_2_A   0x70310
-- 
2.43.2

[PATCH 00/16] drm/i915: skl+ plane register stuff

[Ville Syrjala]

From: Ville Syrjälä 

Bunch of refactoring around skl+ plane registers.

Ville Syrjälä (16):
  drm/i915: Nuke _MMIO_PLANE_GAMC()
  drm/i915: Extract skl_universal_plane_regs.h
  drm/i915: Extract intel_cursor_regs.h
  drm/i915: Move skl+ wm/ddb registers to proper headers
  drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
  drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
  drm/i915/gvt: Use the full PLANE_KEY*() defines
  drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
  drm/i915: Drop useless PLANE_FOO_3 register defines
  drm/i915: Shuffle the skl+ plane register definitions
  drm/i915: Use REG_BIT for PLANE_WM bits
  drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
  drm/i915: Refactor skl+ plane register offset calculations
  drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
  drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
  drm/i915: Handle SKL+ WM/DDB registers next to all other plane
registers

 drivers/gpu/drm/i915/display/intel_cursor.c   |  33 ++
 .../gpu/drm/i915/display/intel_cursor_regs.h  |  98 
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +
 .../gpu/drm/i915/display/intel_dpt_common.c   |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c  |   1 +
 .../drm/i915/display/skl_universal_plane.c|  61 +++
 .../drm/i915/display/skl_universal_plane.h|   5 +
 .../i915/display/skl_universal_plane_regs.h   | 369 ++
 drivers/gpu/drm/i915/display/skl_watermark.c  | 101 +---
 drivers/gpu/drm/i915/display/skl_watermark.h  |  13 +-
 .../gpu/drm/i915/display/skl_watermark_regs.h |  83 
 drivers/gpu/drm/i915/gvt/display.c|   1 +
 drivers/gpu/drm/i915/gvt/dmabuf.c |   3 +-
 drivers/gpu/drm/i915/gvt/fb_decoder.c |   2 +
 drivers/gpu/drm/i915/gvt/handlers.c   |  50 +-
 drivers/gpu/drm/i915/gvt/reg.h|   3 -
 drivers/gpu/drm/i915/i915_reg.h   | 467 --
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  80 +--
 18 files changed, 654 insertions(+), 719 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h
 create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h

-- 
2.43.2

[PATCH v2 8/9] drm/i915: Cleanup fbdev fb setup

[Ville Syrjala]

From: Ville Syrjälä 

We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' (renamed from the
'intel_fb') until the very end.

v2: rebase

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbdev.c | 38 --
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 4bbbf481bb3a..e898018ab76a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -175,7 +175,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
  struct drm_fb_helper_surface_size *sizes)
 {
struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
-   struct intel_framebuffer *intel_fb = ifbdev->fb;
+   struct intel_framebuffer *fb = ifbdev->fb;
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
const struct i915_gtt_view view = {
@@ -195,29 +195,30 @@ static int intelfb_create(struct drm_fb_helper *helper,
if (ret)
return ret;
 
-   if (intel_fb &&
-   (sizes->fb_width > intel_fb->base.width ||
-sizes->fb_height > intel_fb->base.height)) {
+   ifbdev->fb = NULL;
+
+   if (fb &&
+   (sizes->fb_width > fb->base.width ||
+sizes->fb_height > fb->base.height)) {
drm_dbg_kms(_priv->drm,
"BIOS fb too small (%dx%d), we require (%dx%d),"
" releasing it\n",
-   intel_fb->base.width, intel_fb->base.height,
+   fb->base.width, fb->base.height,
sizes->fb_width, sizes->fb_height);
-   drm_framebuffer_put(_fb->base);
-   intel_fb = ifbdev->fb = NULL;
+   drm_framebuffer_put(>base);
+   fb = NULL;
}
-   if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
+   if (!fb || drm_WARN_ON(dev, !intel_fb_obj(>base))) {
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
-   intel_fb = intel_fbdev_fb_alloc(helper, sizes);
-   if (IS_ERR(intel_fb))
-   return PTR_ERR(intel_fb);
-   ifbdev->fb = intel_fb;
+   fb = intel_fbdev_fb_alloc(helper, sizes);
+   if (IS_ERR(fb))
+   return PTR_ERR(fb);
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
-   sizes->fb_width = intel_fb->base.width;
-   sizes->fb_height = intel_fb->base.height;
+   sizes->fb_width = fb->base.width;
+   sizes->fb_height = fb->base.height;
}
 
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
@@ -226,7 +227,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 * This also validates that any existing fb inherited from the
 * BIOS is suitable for own access.
 */
-   vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+   vma = intel_pin_and_fence_fb_obj(>base, false,
 , false, );
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
@@ -240,11 +241,11 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
 
-   ifbdev->helper.fb = >fb->base;
+   ifbdev->helper.fb = >base;
 
info->fbops = _ops;
 
-   obj = intel_fb_obj(_fb->base);
+   obj = intel_fb_obj(>base);
 
ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);
if (ret)
@@ -262,8 +263,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
 
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
-   ifbdev->fb->base.width, ifbdev->fb->base.height,
+   fb->base.width, fb->base.height,
i915_ggtt_offset(vma));
+   ifbdev->fb = fb;
ifbdev->vma = vma;
ifbdev->vma_flags = flags;
 
-- 
2.43.2

[PATCH v2 7/9] drm/i915: Change intel_fbdev_fb_alloc() return type

[Ville Syrjala]

From: Ville Syrjälä 

Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.

v2: Assing the results to the correct variable (Jani)
Fix xe's copy

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbdev.c| 9 -
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_fbdev_fb.h | 4 ++--
 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   | 9 +
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index bda702c2cab8..4bbbf481bb3a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -207,13 +207,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
intel_fb = ifbdev->fb = NULL;
}
if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
-   struct drm_framebuffer *fb;
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
-   fb = intel_fbdev_fb_alloc(helper, sizes);
-   if (IS_ERR(fb))
-   return PTR_ERR(fb);
-   intel_fb = ifbdev->fb = to_intel_framebuffer(fb);
+   intel_fb = intel_fbdev_fb_alloc(helper, sizes);
+   if (IS_ERR(intel_fb))
+   return PTR_ERR(intel_fb);
+   ifbdev->fb = intel_fb;
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c 
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
index 0665f943f65f..497525ef9668 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
@@ -11,8 +11,8 @@
 #include "intel_display_types.h"
 #include "intel_fbdev_fb.h"
 
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size 
*sizes)
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+  struct 
drm_fb_helper_surface_size *sizes)
 {
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
@@ -63,7 +63,7 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct 
drm_fb_helper *helper,
fb = intel_framebuffer_create(obj, _cmd);
i915_gem_object_put(obj);
 
-   return fb;
+   return to_intel_framebuffer(fb);
 }
 
 int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h 
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
index a395b2c65d33..4832fe688fbf 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
@@ -13,8 +13,8 @@ struct drm_i915_private;
 struct fb_info;
 struct i915_vma;
 
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size 
*sizes);
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+  struct 
drm_fb_helper_surface_size *sizes);
 int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
 struct drm_i915_gem_object *obj, struct i915_vma 
*vma);
 
diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c 
b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
index 9e4bcfdbc7e5..f6bf5896ff1b 100644
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
@@ -13,8 +13,8 @@
 #include "i915_drv.h"
 #include "intel_display_types.h"
 
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size *sizes)
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+  struct 
drm_fb_helper_surface_size *sizes)
 {
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
@@ -70,10 +70,11 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct 
drm_fb_helper *helper,
}
 
drm_gem_object_put(intel_bo_to_drm_bo(obj));
-   return fb;
+
+   return to_intel_framebuffer(fb);
 
 err:
-   return fb;
+   return ERR_CAST(fb);
 }
 
 int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
-- 
2.43.2

[PATCH] drm/xe: Nuke xe's copy of intel_fbdev_fb.h

[Ville Syrjala]

From: Ville Syrjälä 

For some reason xe and i915 each have an identical (fortunately)
copy of intel_fbdev_fb.h. The xe copy actually only gets included
by xe's intel_fbdev_fb.c, and the i915 copy by everyone else,
include intel_fbdev.c which is the actual caller of the
functions declared in the header.

This means the xe and i915 headers are free to define/declare
completely incompatible things and the build would still succeed
as long as the symbol names match.

That is not a good thing, so let's nuke xe's copy of the header
so that everyone will use the same header, and be forced to
agree on the same API/ABI.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/xe/display/intel_fbdev_fb.h | 21 -
 1 file changed, 21 deletions(-)
 delete mode 100644 drivers/gpu/drm/xe/display/intel_fbdev_fb.h

diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h 
b/drivers/gpu/drm/xe/display/intel_fbdev_fb.h
deleted file mode 100644
index ea186772e0bb..
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef __INTEL_FBDEV_FB_H__
-#define __INTEL_FBDEV_FB_H__
-
-struct drm_fb_helper;
-struct drm_fb_helper_surface_size;
-struct drm_i915_gem_object;
-struct drm_i915_private;
-struct fb_info;
-struct i915_vma;
-
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size *sizes);
-int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
- struct drm_i915_gem_object *obj, struct i915_vma 
*vma);
-
-#endif
-- 
2.43.2

[PATCH 9/9] drm/i915: Rename the fb pinning functions to indicate the address space

[Ville Syrjala]

From: Ville Syrjälä 

Rename the fb pinning functions such that their name directly
informs us what gets pinned into which address space.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpt.c  |  6 +--
 drivers/gpu/drm/i915/display/intel_dpt.h  |  6 +--
 drivers/gpu/drm/i915/display/intel_fb_pin.c   | 46 +--
 drivers/gpu/drm/i915/display/intel_fb_pin.h   | 12 ++---
 drivers/gpu/drm/i915/display/intel_fbdev.c|  8 ++--
 drivers/gpu/drm/xe/display/xe_fb_pin.c| 12 ++---
 drivers/gpu/drm/xe/display/xe_plane_initial.c |  4 +-
 7 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 786d3f2e94c7..73a1918e2537 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -121,8 +121,8 @@ static void dpt_cleanup(struct i915_address_space *vm)
i915_gem_object_put(dpt->obj);
 }
 
-struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
-  unsigned int alignment)
+struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm,
+  unsigned int alignment)
 {
struct drm_i915_private *i915 = vm->i915;
struct i915_dpt *dpt = i915_vm_to_dpt(vm);
@@ -173,7 +173,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space 
*vm,
return err ? ERR_PTR(err) : vma;
 }
 
-void intel_dpt_unpin(struct i915_address_space *vm)
+void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm)
 {
struct i915_dpt *dpt = i915_vm_to_dpt(vm);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h 
b/drivers/gpu/drm/i915/display/intel_dpt.h
index f467578a4950..ff18a525bfbe 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.h
+++ b/drivers/gpu/drm/i915/display/intel_dpt.h
@@ -13,9 +13,9 @@ struct i915_vma;
 struct intel_framebuffer;
 
 void intel_dpt_destroy(struct i915_address_space *vm);
-struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
-  unsigned int alignment);
-void intel_dpt_unpin(struct i915_address_space *vm);
+struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm,
+  unsigned int alignment);
+void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm);
 void intel_dpt_suspend(struct drm_i915_private *i915);
 void intel_dpt_resume(struct drm_i915_private *i915);
 struct i915_address_space *
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c 
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 7971656982a6..1acc11fa19f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,11 +18,11 @@
 #include "intel_fb_pin.h"
 
 static struct i915_vma *
-intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb,
-const struct i915_gtt_view *view,
-unsigned int alignment,
-unsigned long *out_flags,
-struct i915_address_space *vm)
+intel_fb_pin_to_dpt(const struct drm_framebuffer *fb,
+   const struct i915_gtt_view *view,
+   unsigned int alignment,
+   unsigned long *out_flags,
+   struct i915_address_space *vm)
 {
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -102,11 +102,11 @@ intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb,
 }
 
 struct i915_vma *
-intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb,
-  bool phys_cursor,
-  const struct i915_gtt_view *view,
-  bool uses_fence,
-  unsigned long *out_flags)
+intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
+bool phys_cursor,
+const struct i915_gtt_view *view,
+bool uses_fence,
+unsigned long *out_flags)
 {
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -226,7 +226,7 @@ intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb,
return vma;
 }
 
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
+void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
 {
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
@@ -242,10 +242,10 @@ int intel_plane_pin_fb(struct intel_plane_state 
*plane_state)
struct i915_vma *vma;
 
if (!intel_fb_uses_dpt(>base)) {
-   vma = intel_pin_and_fence_fb_obj(>base, 
intel_plane_needs_physical(plane),
-_state->view.gtt,
-
intel_plane_uses_fence(plane_state),
-_state->flags);
+   vma = intel_fb_pin_to_ggtt(>base, 

[PATCH 8/9] drm/i915: Cleanup fbdev fb setup

[Ville Syrjala]

From: Ville Syrjälä 

We use a mix of 'fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' until the very end.

And we'll also change intel_fbdev_fb_alloc() to return
struct intel_fb instead of struct drm_framebuffer so that
we don't have to have yet another alias for the same thing.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbdev.c | 39 +++---
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 0d79ec1a6427..e898018ab76a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -175,7 +175,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
  struct drm_fb_helper_surface_size *sizes)
 {
struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
-   struct intel_framebuffer *intel_fb = ifbdev->fb;
+   struct intel_framebuffer *fb = ifbdev->fb;
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
const struct i915_gtt_view view = {
@@ -195,30 +195,30 @@ static int intelfb_create(struct drm_fb_helper *helper,
if (ret)
return ret;
 
-   if (intel_fb &&
-   (sizes->fb_width > intel_fb->base.width ||
-sizes->fb_height > intel_fb->base.height)) {
+   ifbdev->fb = NULL;
+
+   if (fb &&
+   (sizes->fb_width > fb->base.width ||
+sizes->fb_height > fb->base.height)) {
drm_dbg_kms(_priv->drm,
"BIOS fb too small (%dx%d), we require (%dx%d),"
" releasing it\n",
-   intel_fb->base.width, intel_fb->base.height,
+   fb->base.width, fb->base.height,
sizes->fb_width, sizes->fb_height);
-   drm_framebuffer_put(_fb->base);
-   intel_fb = ifbdev->fb = NULL;
+   drm_framebuffer_put(>base);
+   fb = NULL;
}
-   if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
-   struct intel_framebuffer *fb;
+   if (!fb || drm_WARN_ON(dev, !intel_fb_obj(>base))) {
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
-   intel_fb = intel_fbdev_fb_alloc(helper, sizes);
-   if (IS_ERR(intel_fb))
-   return PTR_ERR(intel_fb);
-   ifbdev->fb = fb;
+   fb = intel_fbdev_fb_alloc(helper, sizes);
+   if (IS_ERR(fb))
+   return PTR_ERR(fb);
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
-   sizes->fb_width = intel_fb->base.width;
-   sizes->fb_height = intel_fb->base.height;
+   sizes->fb_width = fb->base.width;
+   sizes->fb_height = fb->base.height;
}
 
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
@@ -227,7 +227,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 * This also validates that any existing fb inherited from the
 * BIOS is suitable for own access.
 */
-   vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+   vma = intel_pin_and_fence_fb_obj(>base, false,
 , false, );
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
@@ -241,11 +241,11 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
 
-   ifbdev->helper.fb = >fb->base;
+   ifbdev->helper.fb = >base;
 
info->fbops = _ops;
 
-   obj = intel_fb_obj(_fb->base);
+   obj = intel_fb_obj(>base);
 
ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);
if (ret)
@@ -263,8 +263,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
 
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
-   ifbdev->fb->base.width, ifbdev->fb->base.height,
+   fb->base.width, fb->base.height,
i915_ggtt_offset(vma));
+   ifbdev->fb = fb;
ifbdev->vma = vma;
ifbdev->vma_flags = flags;
 
-- 
2.43.2

[PATCH 7/9] drm/i915: Change intel_fbdev_fb_alloc() reuturn type

[Ville Syrjala]

From: Ville Syrjälä 

Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbdev.c| 10 +-
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_fbdev_fb.h |  5 +++--
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index bda702c2cab8..0d79ec1a6427 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -207,13 +207,13 @@ static int intelfb_create(struct drm_fb_helper *helper,
intel_fb = ifbdev->fb = NULL;
}
if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
-   struct drm_framebuffer *fb;
+   struct intel_framebuffer *fb;
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
-   fb = intel_fbdev_fb_alloc(helper, sizes);
-   if (IS_ERR(fb))
-   return PTR_ERR(fb);
-   intel_fb = ifbdev->fb = to_intel_framebuffer(fb);
+   intel_fb = intel_fbdev_fb_alloc(helper, sizes);
+   if (IS_ERR(intel_fb))
+   return PTR_ERR(intel_fb);
+   ifbdev->fb = fb;
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c 
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
index 0665f943f65f..497525ef9668 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
@@ -11,8 +11,8 @@
 #include "intel_display_types.h"
 #include "intel_fbdev_fb.h"
 
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size 
*sizes)
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+  struct 
drm_fb_helper_surface_size *sizes)
 {
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
@@ -63,7 +63,7 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct 
drm_fb_helper *helper,
fb = intel_framebuffer_create(obj, _cmd);
i915_gem_object_put(obj);
 
-   return fb;
+   return to_intel_framebuffer(fb);
 }
 
 int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h 
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
index a395b2c65d33..82e8e7cc007b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
@@ -12,9 +12,10 @@ struct drm_i915_gem_object;
 struct drm_i915_private;
 struct fb_info;
 struct i915_vma;
+struct intel_framebuffer;
 
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size 
*sizes);
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+  struct 
drm_fb_helper_surface_size *sizes);
 int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info 
*info,
 struct drm_i915_gem_object *obj, struct i915_vma 
*vma);
 
-- 
2.43.2

[PATCH 6/9] drm/i915: Constify 'fb' in during pinning

[Ville Syrjala]

From: Ville Syrjälä 

Make the 'fb' pointers const in the pinning code. We never
want to mutate these. Also nuke a few aliasing fb vs. intel_fb
cases by just using the more specific type everywhere in the
same function.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb_pin.c | 33 ++---
 drivers/gpu/drm/i915/display/intel_fb_pin.h |  2 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c  |  8 ++---
 3 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c 
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 041f09f76628..7971656982a6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,7 +18,7 @@
 #include "intel_fb_pin.h"
 
 static struct i915_vma *
-intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
+intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb,
 const struct i915_gtt_view *view,
 unsigned int alignment,
 unsigned long *out_flags,
@@ -102,7 +102,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
 }
 
 struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb,
   bool phys_cursor,
   const struct i915_gtt_view *view,
   bool uses_fence,
@@ -237,11 +237,12 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned 
long flags)
 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-   struct drm_framebuffer *fb = plane_state->hw.fb;
+   const struct intel_framebuffer *fb =
+   to_intel_framebuffer(plane_state->hw.fb);
struct i915_vma *vma;
 
-   if (!intel_fb_uses_dpt(fb)) {
-   vma = intel_pin_and_fence_fb_obj(fb, 
intel_plane_needs_physical(plane),
+   if (!intel_fb_uses_dpt(>base)) {
+   vma = intel_pin_and_fence_fb_obj(>base, 
intel_plane_needs_physical(plane),
 _state->view.gtt,
 
intel_plane_uses_fence(plane_state),
 _state->flags);
@@ -258,22 +259,21 @@ int intel_plane_pin_fb(struct intel_plane_state 
*plane_state)
 */
if (intel_plane_needs_physical(plane))
plane_state->phys_dma_addr =
-   
i915_gem_object_get_dma_address(intel_fb_obj(fb), 0);
+   
i915_gem_object_get_dma_address(intel_fb_obj(>base), 0);
} else {
-   struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-   unsigned int alignment = intel_surf_alignment(fb, 0);
+   unsigned int alignment = intel_surf_alignment(>base, 0);
 
-   vma = intel_dpt_pin(intel_fb->dpt_vm, alignment / 512);
+   vma = intel_dpt_pin(fb->dpt_vm, alignment / 512);
if (IS_ERR(vma))
return PTR_ERR(vma);
 
plane_state->ggtt_vma = vma;
 
-   vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
+   vma = intel_pin_fb_obj_dpt(>base, _state->view.gtt,
   alignment, _state->flags,
-  intel_fb->dpt_vm);
+  fb->dpt_vm);
if (IS_ERR(vma)) {
-   intel_dpt_unpin(intel_fb->dpt_vm);
+   intel_dpt_unpin(fb->dpt_vm);
plane_state->ggtt_vma = NULL;
return PTR_ERR(vma);
}
@@ -288,22 +288,21 @@ int intel_plane_pin_fb(struct intel_plane_state 
*plane_state)
 
 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
 {
-   struct drm_framebuffer *fb = old_plane_state->hw.fb;
+   const struct intel_framebuffer *fb =
+   to_intel_framebuffer(old_plane_state->hw.fb);
struct i915_vma *vma;
 
-   if (!intel_fb_uses_dpt(fb)) {
+   if (!intel_fb_uses_dpt(>base)) {
vma = fetch_and_zero(_plane_state->ggtt_vma);
if (vma)
intel_unpin_fb_vma(vma, old_plane_state->flags);
} else {
-   struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-
vma = fetch_and_zero(_plane_state->dpt_vma);
if (vma)
intel_unpin_fb_vma(vma, old_plane_state->flags);
 
vma = fetch_and_zero(_plane_state->ggtt_vma);
if (vma)
-   intel_dpt_unpin(intel_fb->dpt_vm);
+   intel_dpt_unpin(fb->dpt_vm);
}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h 
b/drivers/gpu/drm/i915/display/intel_fb_pin.h
index 

[PATCH 5/9] drm/i915: Polish types in fb calculations

[Ville Syrjala]

From: Ville Syrjälä 

Be a bit more consistent in our use of integer types in
the fb related calculatiosn. u32 we generally only use
for ggtt offsets and such, and everything else can be regular
(unsigned) ints.

There's also an overabundance of consts for local variables
in skl_check_main_surface() which is not something we generally
do. So get rid of those while at it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c |  2 +-
 drivers/gpu/drm/i915/display/intel_fb.c   | 27 +
 drivers/gpu/drm/i915/display/intel_fb_pin.c   |  2 +-
 .../drm/i915/display/skl_universal_plane.c| 29 +--
 4 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 21303fa4f08f..ea4d8ba55ad8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state 
*plane_state)
 * despite them not using the linear offset anymore.
 */
if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == 
I915_FORMAT_MOD_X_TILED) {
-   u32 alignment = intel_surf_alignment(fb, 0);
+   unsigned int alignment = intel_surf_alignment(fb, 0);
int cpp = fb->format->cpp[0];
 
while ((src_x + src_w) * cpp > 
plane_state->view.color_plane[0].mapping_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index bf24f48a1e76..b6638726949d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1045,7 +1045,7 @@ static u32 intel_compute_aligned_offset(struct 
drm_i915_private *i915,
int color_plane,
unsigned int pitch,
unsigned int rotation,
-   u32 alignment)
+   unsigned int alignment)
 {
unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
@@ -1102,8 +1102,8 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
struct drm_i915_private *i915 = to_i915(intel_plane->base.dev);
const struct drm_framebuffer *fb = state->hw.fb;
unsigned int rotation = state->hw.rotation;
-   int pitch = state->view.color_plane[color_plane].mapping_stride;
-   u32 alignment;
+   unsigned int pitch = 
state->view.color_plane[color_plane].mapping_stride;
+   unsigned int alignment;
 
if (intel_plane->id == PLANE_CURSOR)
alignment = intel_cursor_alignment(i915);
@@ -1120,8 +1120,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
 int color_plane)
 {
struct drm_i915_private *i915 = to_i915(fb->dev);
-   unsigned int height;
-   u32 alignment, unused;
+   unsigned int height, alignment, unused;
 
if (DISPLAY_VER(i915) >= 12 &&
!intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
@@ -1508,8 +1507,8 @@ static u32 calc_plane_remap_info(const struct 
intel_framebuffer *fb, int color_p
check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
 
if (view->gtt.remapped.plane_alignment) {
-   unsigned int aligned_offset = ALIGN(gtt_offset,
-   
view->gtt.remapped.plane_alignment);
+   u32 aligned_offset = ALIGN(gtt_offset,
+  
view->gtt.remapped.plane_alignment);
 
size += aligned_offset - gtt_offset;
gtt_offset = aligned_offset;
@@ -1795,16 +1794,16 @@ u32 intel_fb_max_stride(struct drm_i915_private 
*dev_priv,
return 128 * 1024;
 }
 
-static u32
+static unsigned int
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
struct drm_i915_private *dev_priv = to_i915(fb->dev);
-   u32 tile_width;
+   unsigned int tile_width;
 
if (is_surface_linear(fb, color_plane)) {
-   u32 max_stride = intel_plane_fb_max_stride(dev_priv,
-  fb->format->format,
-  fb->modifier);
+   unsigned int max_stride = intel_plane_fb_max_stride(dev_priv,
+   
fb->format->format,
+   
fb->modifier);
 
/*
 * To make remapping with linear generally feasible
@@ -2061,7 +2060,7 @@ int intel_framebuffer_init(struct intel_framebuffer 
*intel_fb,
drm_helper_mode_fill_fb_struct(_priv->drm, fb, mode_cmd);
 
for (i = 

[PATCH 4/9] drm/i915: Extract intel_plane_needs_physical()

[Ville Syrjala]

From: Ville Syrjälä 

Pull the "does this plane need a physical address?" check into
a small helper.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 
 drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
 drivers/gpu/drm/i915/display/intel_fb_pin.c   | 9 +++--
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b083b985d170..27224ecdc94c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -144,6 +144,14 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
 }
 
+bool intel_plane_needs_physical(struct intel_plane *plane)
+{
+   struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+   return plane->id == PLANE_CURSOR &&
+   DISPLAY_INFO(i915)->cursor_needs_physical;
+}
+
 unsigned int intel_adjusted_rate(const struct drm_rect *src,
 const struct drm_rect *dst,
 unsigned int rate)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 191dad0efc8e..e7a0699f17c8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -66,5 +66,6 @@ int intel_plane_check_src_coordinates(struct 
intel_plane_state *plane_state);
 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
   struct intel_plane_state *plane_state);
 void intel_plane_helper_add(struct intel_plane *plane);
+bool intel_plane_needs_physical(struct intel_plane *plane);
 
 #endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c 
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 2b50c1946c63..5b71d9488184 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -11,6 +11,7 @@
 #include "gem/i915_gem_object.h"
 
 #include "i915_drv.h"
+#include "intel_atomic_plane.h"
 #include "intel_display_types.h"
 #include "intel_dpt.h"
 #include "intel_fb.h"
@@ -236,15 +237,11 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned 
long flags)
 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct drm_framebuffer *fb = plane_state->hw.fb;
struct i915_vma *vma;
-   bool phys_cursor =
-   plane->id == PLANE_CURSOR &&
-   DISPLAY_INFO(dev_priv)->cursor_needs_physical;
 
if (!intel_fb_uses_dpt(fb)) {
-   vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
+   vma = intel_pin_and_fence_fb_obj(fb, 
intel_plane_needs_physical(plane),
 _state->view.gtt,
 
intel_plane_uses_fence(plane_state),
 _state->flags);
@@ -259,7 +256,7 @@ int intel_plane_pin_fb(struct intel_plane_state 
*plane_state)
 * will trigger might_sleep() even if it won't actually sleep,
 * which is the case when the fb has already been pinned.
 */
-   if (phys_cursor)
+   if (intel_plane_needs_physical(plane))
plane_state->phys_dma_addr =

i915_gem_object_get_dma_address(intel_fb_obj(fb), 0);
} else {
-- 
2.43.2

[PATCH 3/9] drm/i915: Drop 'uses_fence' parameter from intel_pin_fb_obj_dpt()

[Ville Syrjala]

From: Ville Syrjälä 

Fence regions are only relevant for GGTT, not DPT. Drop the
pointless 'uses_fence' argument from intel_pin_fb_obj_dpt().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c 
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index be095cc696ba..2b50c1946c63 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -20,7 +20,6 @@ static struct i915_vma *
 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
 const struct i915_gtt_view *view,
 unsigned int alignment,
-bool uses_fence,
 unsigned long *out_flags,
 struct i915_address_space *vm)
 {
@@ -274,8 +273,8 @@ int intel_plane_pin_fb(struct intel_plane_state 
*plane_state)
plane_state->ggtt_vma = vma;
 
vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
-  alignment, false,
-  _state->flags, 
intel_fb->dpt_vm);
+  alignment, _state->flags,
+  intel_fb->dpt_vm);
if (IS_ERR(vma)) {
intel_dpt_unpin(intel_fb->dpt_vm);
plane_state->ggtt_vma = NULL;
-- 
2.43.2

[PATCH 2/9] drm/i915: Clean up skl+ plane stride limits

[Ville Syrjala]

From: Ville Syrjälä 

skl_plane_max_stride() is pretty messy. Streamline it and
split it into clear skl+ vs. adl+ variants.

TODO: Deal with icl and tgl strude limits properly

Signed-off-by: Ville Syrjälä 
---
 .../drm/i915/display/skl_universal_plane.c| 65 +++
 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0a8e781a3648..b8103d6ebc1f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -461,41 +461,46 @@ static int icl_plane_max_height(const struct 
drm_framebuffer *fb,
 }
 
 static unsigned int
-skl_plane_max_stride(struct intel_plane *plane,
-u32 pixel_format, u64 modifier,
-unsigned int rotation)
+plane_max_stride(struct intel_plane *plane,
+u32 pixel_format, u64 modifier,
+unsigned int rotation,
+unsigned int max_pixels,
+unsigned int max_bytes)
 {
-   struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
-   int max_horizontal_pixels = 8192;
-   int max_stride_bytes;
-
-   if (DISPLAY_VER(i915) >= 13) {
-   /*
-* The stride in bytes must not exceed of the size
-* of 128K bytes. For pixel formats of 64bpp will allow
-* for a 16K pixel surface.
-*/
-   max_stride_bytes = 131072;
-   if (cpp == 8)
-   max_horizontal_pixels = 16384;
-   else
-   max_horizontal_pixels = 65536;
-   } else {
-   /*
-* "The stride in bytes must not exceed the
-* of the size of 8K pixels and 32K bytes."
-*/
-   max_stride_bytes = 32768;
-   }
 
if (drm_rotation_90_or_270(rotation))
-   return min(max_horizontal_pixels, max_stride_bytes / cpp);
+   return min(max_pixels, max_bytes / cpp);
else
-   return min(max_horizontal_pixels * cpp, max_stride_bytes);
+   return min(max_pixels * cpp, max_bytes);
 }
 
+static unsigned int
+adl_plane_max_stride(struct intel_plane *plane,
+u32 pixel_format, u64 modifier,
+unsigned int rotation)
+{
+   unsigned int max_pixels = 65536; /* PLANE_OFFSET limit */
+   unsigned int max_bytes = 128 * 1024;
+
+   return plane_max_stride(plane, pixel_format,
+   modifier, rotation,
+   max_pixels, max_bytes);
+}
+
+static unsigned int
+skl_plane_max_stride(struct intel_plane *plane,
+u32 pixel_format, u64 modifier,
+unsigned int rotation)
+{
+   unsigned int max_pixels = 8192; /* PLANE_OFFSET limit */
+   unsigned int max_bytes = 32 * 1024;
+
+   return plane_max_stride(plane, pixel_format,
+   modifier, rotation,
+   max_pixels, max_bytes);
+}
 
 /* Preoffset values for YUV to RGB Conversion */
 #define PREOFF_YUV_TO_RGB_HI   0x1800
@@ -2357,7 +2362,11 @@ skl_universal_plane_create(struct drm_i915_private 
*dev_priv,
plane->min_cdclk = skl_plane_min_cdclk;
}
 
-   plane->max_stride = skl_plane_max_stride;
+   if (DISPLAY_VER(dev_priv) >= 13)
+   plane->max_stride = adl_plane_max_stride;
+   else
+   plane->max_stride = skl_plane_max_stride;
+
if (DISPLAY_VER(dev_priv) >= 11) {
plane->update_noarm = icl_plane_update_noarm;
plane->update_arm = icl_plane_update_arm;
-- 
2.43.2

[PATCH 1/9] drm/i915: Split gen2 vs. gen3 .max_stride()

[Ville Syrjala]

From: Ville Syrjälä 

Plane .max_stride() is alreayd a vfunc so having one made
up of two branches based on the display version is silly.
Split i9xx_plane_max_stride() into gen2 vs. gen3 variants
so  that we get rid of said check.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/i9xx_plane.c | 32 +--
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 3442264443e5..21303fa4f08f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -741,23 +741,25 @@ i965_plane_max_stride(struct intel_plane *plane,
 }
 
 static unsigned int
-i9xx_plane_max_stride(struct intel_plane *plane,
+i915_plane_max_stride(struct intel_plane *plane,
  u32 pixel_format, u64 modifier,
  unsigned int rotation)
 {
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+   if (modifier == I915_FORMAT_MOD_X_TILED)
+   return 8 * 1024;
+   else
+   return 16 * 1024;
+}
 
-   if (DISPLAY_VER(dev_priv) >= 3) {
-   if (modifier == I915_FORMAT_MOD_X_TILED)
-   return 8*1024;
-   else
-   return 16*1024;
-   } else {
-   if (plane->i9xx_plane == PLANE_C)
-   return 4*1024;
-   else
-   return 8*1024;
-   }
+static unsigned int
+i8xx_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+   if (plane->i9xx_plane == PLANE_C)
+   return 4 * 1024;
+   else
+   return 8 * 1024;
 }
 
 static const struct drm_plane_funcs i965_plane_funcs = {
@@ -854,8 +856,10 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
if (HAS_GMCH(dev_priv)) {
if (DISPLAY_VER(dev_priv) >= 4)
plane->max_stride = i965_plane_max_stride;
+   else if (DISPLAY_VER(dev_priv) == 3)
+   plane->max_stride = i915_plane_max_stride;
else
-   plane->max_stride = i9xx_plane_max_stride;
+   plane->max_stride = i8xx_plane_max_stride;
} else {
if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
plane->max_stride = hsw_primary_max_stride;
-- 
2.43.2

[PATCH 0/9] drm/i915: Plane fb refactoring

[Ville Syrjala]

From: Ville Syrjälä 

A bit of cleanup/refactoring around plane fb stuff.
This is mainly prep work for a slightly bigger rework
of alignment handling.

Ville Syrjälä (9):
  drm/i915: Split gen2 vs. gen3 .max_stride()
  drm/i915: Clean up skl+ plane stride limits
  drm/i915: Drop 'uses_fence' parameter from intel_pin_fb_obj_dpt()
  drm/i915: Extract intel_plane_needs_physical()
  drm/i915: Polish types in fb calculations
  drm/i915: Constify 'fb' in during pinning
  drm/i915: Change intel_fbdev_fb_alloc() reuturn type
  drm/i915: Cleanup fbdev fb setup
  drm/i915: Rename the fb pinning functions to indicate the address
space

 drivers/gpu/drm/i915/display/i9xx_plane.c | 34 ---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  8 ++
 .../gpu/drm/i915/display/intel_atomic_plane.h |  1 +
 drivers/gpu/drm/i915/display/intel_dpt.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_dpt.h  |  6 +-
 drivers/gpu/drm/i915/display/intel_fb.c   | 27 +++---
 drivers/gpu/drm/i915/display/intel_fb_pin.c   | 73 +++---
 drivers/gpu/drm/i915/display/intel_fb_pin.h   | 12 +--
 drivers/gpu/drm/i915/display/intel_fbdev.c| 39 
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c |  6 +-
 drivers/gpu/drm/i915/display/intel_fbdev_fb.h |  5 +-
 .../drm/i915/display/skl_universal_plane.c| 94 ++-
 drivers/gpu/drm/xe/display/xe_fb_pin.c| 18 ++--
 drivers/gpu/drm/xe/display/xe_plane_initial.c |  4 +-
 14 files changed, 175 insertions(+), 158 deletions(-)

-- 
2.43.2

[PATCH 35/35] drm/i915/bios: Define VBT block 253 (PRD Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 253 (PRD Table).

Unfortunately the block has two definitions, with the cutoff
supposedly happening on ICL vs. TGL. Also according to some
notes it might be that the VBIOS (if that's still a thing)
still uses the old definition even on TGL+. Quite the mess.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 26 +++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 338f6133bb1e..9d5b87ff1728 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -189,6 +189,7 @@ enum bdb_block_id {
BDB_VSWING_PREEMPH  = 57, /* 218+ */
BDB_GENERIC_DTD = 58, /* 229+ */
BDB_INT15_HOOK  = 252, /* VBIOS only */
+   BDB_PRD_TABLE   = 253,
BDB_SKIP= 254, /* VBIOS only */
 };
 
@@ -1576,4 +1577,29 @@ struct bdb_generic_dtd {
struct generic_dtd_entry dtd[]; /* up to 24 DTD's */
 } __packed;
 
+/*
+ * Block 253 - PRD Table
+ */
+
+struct prd_entry_old {
+   u8 displays_attached;
+   u8 display_in_pipe_a;
+   u8 display_in_pipe_b;
+} __packed;
+
+struct bdb_prd_table_old {
+   struct prd_entry_old list[0];   /* ???-216 */
+   u16 num_entries;/* ???-216 */
+} __packed;
+
+struct prd_entry_new {
+   u16 primary_display;
+   u16 secondary_display;
+} __packed;
+
+struct bdb_prd_table_new {
+   u16 num_entries;/* 217+ */
+   struct prd_entry_new list[];/* 217+ */
+} __packed;
+
 #endif /* _INTEL_VBT_DEFS_H_ */
-- 
2.43.2

[PATCH 34/35] drm/i915/bios: Define VBT block 252 (int15 Hook)

[Ville Syrjala]

From: Ville Syrjälä 

Declare that VBT block 252 is the "int15 hook". This is some
VBIOS only juju so don't bother with a full definition.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index ea2edac842b0..338f6133bb1e 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -188,6 +188,7 @@ enum bdb_block_id {
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
BDB_VSWING_PREEMPH  = 57, /* 218+ */
BDB_GENERIC_DTD = 58, /* 229+ */
+   BDB_INT15_HOOK  = 252, /* VBIOS only */
BDB_SKIP= 254, /* VBIOS only */
 };
 
-- 
2.43.2

[PATCH 33/35] drm/i915/bios: Define VBT block 55 (Compression Parameters)

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of the obsolete VBT block 55 (Compression
Parameters).

This was some early attempt at defining the compression
parameters. However the spec says:
"This block is obsolete and should not be consumed for any
 compression programming."

Block 56 is the replacement that should actually be used.

So let's just name the obsolete old block but not even
bother defining the contents.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 3bcb9fb5b706..ea2edac842b0 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -184,6 +184,7 @@ enum bdb_block_id {
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
BDB_RGB_PALETTE = 54, /* 180+ */
+   BDB_COMPRESSION_PARAMETERS_OLD  = 55, /* 198-212 */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
BDB_VSWING_PREEMPH  = 57, /* 218+ */
BDB_GENERIC_DTD = 58, /* 229+ */
-- 
2.43.2

[PATCH 32/35] drm/i915/bios: Define VBT block 50 (MIPI) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 50 (MIPI).

This was some easly attempt at a MIPI DSI stuff. I'm not sure
this was ever actually used (I certainly don't have any VBTs
with this block), but here's some kind of definition for it
anyway.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 47 +++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 0e5a2bf429f4..3bcb9fb5b706 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -179,6 +179,7 @@ enum bdb_block_id {
BDB_LFP_POWER   = 44,
BDB_EDP_BFI = 45, /* 160+ */
BDB_CHROMATICITY= 46, /* 169+ */
+   BDB_MIPI= 50, /* 170-172 */
BDB_FIXED_SET_MODE  = 51, /* 172+ */
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
@@ -1393,6 +1394,52 @@ struct bdb_chromaticity {
struct chromaticity chromaticity[16];
 } __packed;
 
+/*
+ * Block 50 - MIPI Block
+ */
+
+struct mipi_data {
+   u16 panel_identifier;
+   u16 bridge_revision;
+
+   u32 dithering:1;
+   u32 pixel_format_18bpp:1;
+   u32 reserved1:1;
+   u32 dphy_params_valid:1;
+   u32 reserved2:28;
+
+   u16 port_info;
+
+   u16 reserved3:2;
+   u16 num_lanes:2;
+   u16 reserved4:12;
+
+   u16 virtual_channel_num:2;
+   u16 video_transfer_mode:2;
+   u16 reserved5:12;
+
+   u32 dsi_ddr_clock;
+   u32 renesas_bridge_ref_clock;
+   u16 power_conservation;
+
+   u32 prepare_count:5;
+   u32 reserved6:3;
+   u32 clk_zero_count:8;
+   u32 trail_count:5;
+   u32 reserved7:3;
+   u32 exit_zero_count:6;
+   u32 reserved8:2;
+
+   u32 high_low_switch_count;
+   u32 lp_byte_clock;
+   u32 clock_lane_switch_time_counter;
+   u32 panel_color_depth;
+} __packed;
+
+struct bdb_mipi {
+   struct mipi_data mipi[16];
+} __packed;
+
 /*
  * Block 51 - Fixed Set Mode Table
  */
-- 
2.43.2

[PATCH 31/35] drm/i915/bios: Define VBT block 57 (Vswing PreEmphasis Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 57 (Vswing PreEmphasis Table).

The contents is highly platform specific. The columns of the
table corresponding to some set of PHY/etc registers. The rows
corresponding to all legal vswing+pre-emphasis combinations
(ie. should be 10 rows in each table). And each table
corresponds to a platform specific (mostly undocumented)
mapping based on link rate/eDP low-vswing/etc. parameters.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 50d0d96fca67..0e5a2bf429f4 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -184,6 +184,7 @@ enum bdb_block_id {
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
BDB_RGB_PALETTE = 54, /* 180+ */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
+   BDB_VSWING_PREEMPH  = 57, /* 218+ */
BDB_GENERIC_DTD = 58, /* 229+ */
BDB_SKIP= 254, /* VBIOS only */
 };
@@ -1486,6 +1487,16 @@ struct bdb_compression_parameters {
struct dsc_compression_parameters_entry data[16];
 } __packed;
 
+/*
+ * Block 57 -  Vswing PreEmphasis Table
+ */
+
+struct bdb_vswing_preemph {
+   u8 num_tables;
+   u8 num_columns;
+   u32 tables[];
+} __packed;
+
 /*
  * Block 58 - Generic DTD Block
  */
-- 
2.43.2

[PATCH 30/35] drm/i915/bios: Define VBT block 55 (RGB Palette Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 55 (RGB Palette Table).

Note that I've not actually seen any real world VBTs with this
block.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 8b4f76c54829..50d0d96fca67 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -182,6 +182,7 @@ enum bdb_block_id {
BDB_FIXED_SET_MODE  = 51, /* 172+ */
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
+   BDB_RGB_PALETTE = 54, /* 180+ */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
BDB_GENERIC_DTD = 58, /* 229+ */
BDB_SKIP= 254, /* VBIOS only */
@@ -1423,6 +1424,17 @@ struct bdb_mipi_sequence {
u8 data[]; /* up to 6 variable length blocks */
 } __packed;
 
+/*
+ * Block 55 - RGB Palette Table
+ */
+
+struct bdb_rgb_palette {
+   u8 is_enabled;
+   u8 red[256];
+   u8 blue[256];
+   u8 green[256];
+} __packed;
+
 /*
  * Block 56 - Compression Parameters
  */
-- 
2.43.2

[PATCH 29/35] drm/i915/bios: Define VBT block 51 (Fixed Set Mode Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 51 (Fixed Set Mode Table).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 5f1f485f8bf7..8b4f76c54829 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -179,6 +179,7 @@ enum bdb_block_id {
BDB_LFP_POWER   = 44,
BDB_EDP_BFI = 45, /* 160+ */
BDB_CHROMATICITY= 46, /* 169+ */
+   BDB_FIXED_SET_MODE  = 51, /* 172+ */
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
@@ -1390,6 +1391,16 @@ struct bdb_chromaticity {
struct chromaticity chromaticity[16];
 } __packed;
 
+/*
+ * Block 51 - Fixed Set Mode Table
+ */
+
+struct bdb_fixed_set_mode {
+   u8 enable;
+   u32 x_res;
+   u32 y_res;
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.43.2

[PATCH 28/35] drm/i915/bios: Define VBT block 46 (Chromaticity For Narrow Gamut Panel) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 46 (Chromaticity For Narrow Gamut
Panel). One entry per panel.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 26 +++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 87d073154d49..5f1f485f8bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -178,6 +178,7 @@ enum bdb_block_id {
BDB_LFP_BACKLIGHT   = 43,
BDB_LFP_POWER   = 44,
BDB_EDP_BFI = 45, /* 160+ */
+   BDB_CHROMATICITY= 46, /* 169+ */
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
@@ -1364,6 +1365,31 @@ struct bdb_edp_bfi {
struct edp_bfi bfi[16];
 } __packed;
 
+/*
+ * Block 46 - Chromaticity For Narrow Gamut Panel Configuration Block
+ */
+
+struct chromaticity {
+   u8 chromaticity_enable:1;
+   u8 chromaticity_from_edid_base_block:1;
+   u8 rsvd:6;
+
+   u8 red_green;
+   u8 blue_white;
+   u8 red_x;
+   u8 red_y;
+   u8 green_x;
+   u8 green_y;
+   u8 blue_x;
+   u8 blue_y;
+   u8 white_x;
+   u8 white_y;
+} __packed;
+
+struct bdb_chromaticity {
+   struct chromaticity chromaticity[16];
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.43.2

[PATCH 27/35] drm/i915/bios: Define VBT block 45 (eDP BFI) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 45 (eDP BFI).

Note that I've not actually seen any real world VBTs with this
block.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 716a339f6e2a..87d073154d49 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -177,6 +177,7 @@ enum bdb_block_id {
BDB_LFP_DATA= 42,
BDB_LFP_BACKLIGHT   = 43,
BDB_LFP_POWER   = 44,
+   BDB_EDP_BFI = 45, /* 160+ */
BDB_MIPI_CONFIG = 52, /* 175+ */
BDB_MIPI_SEQUENCE   = 53, /* 177+ */
BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
@@ -1347,6 +1348,22 @@ struct bdb_lfp_power {
struct aggressiveness_profile2_entry aggressiveness2[16];   /* 247+ 
*/
 } __packed;
 
+/*
+ * Block 45 - eDP BFI Block
+ */
+
+struct edp_bfi {
+   u8 enable_bfi_in_driver:1;
+   u8 enable_brightness_control_in_cui:1;
+   u8 reserved:6;
+   u8 brightness_percentage_when_bfi_disabled;
+} __packed;
+
+struct bdb_edp_bfi {
+   u8 bfi_structure_size;
+   struct edp_bfi bfi[16];
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.43.2

[PATCH 26/35] drm/i915/bios: Define VBT block 28 (EFP DTD) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 28 (EFP DTD).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 1b94d4aba00a..716a339f6e2a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -167,6 +167,7 @@ enum bdb_block_id {
BDB_SDVO_LVDS_PPS   = 25,
BDB_TV_OPTIONS  = 26,
BDB_EDP = 27,
+   BDB_EFP_DTD = 28, /* 161+ */
BDB_DISPLAY_SELECT_IVB  = 29, /* 164+ */
BDB_DISPLAY_REMOVE_IVB  = 30, /* 164+ */
BDB_DISPLAY_SELECT_HSW  = 31, /* 166+ */
@@ -1072,6 +1073,14 @@ struct bdb_edp {
u16 edp_dsc_disable;/* 251+ */
 } __packed;
 
+/*
+ * Block 28 - EFP DTD Block
+ */
+
+struct bdb_efp_dtd {
+   struct bdb_edid_dtd dtd[3];
+} __packed;
+
 /*
  * Block 29 - Toggle List Block (IVB)
  */
-- 
2.43.2

[PATCH 25/35] drm/i915/bios: Define VBT block 26 (TV Options) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 26 (TV Options).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index c6d03905593d..1b94d4aba00a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -988,6 +988,18 @@ struct bdb_sdvo_lvds_pps {
struct sdvo_lvds_pps pps[4];
 } __packed;
 
+/*
+ * Block 26 - TV Options Block
+ */
+
+struct bdb_tv_options {
+   u16 underscan_overscan_hdtv_component:2;
+   u16 rsvd1:10;
+   u16 underscan_overscan_hdtv_dvi:2;
+   u16 add_modes_to_avoid_overscan_issue:1;
+   u16 d_connector_support:1;
+} __packed;
+
 /*
  * Block 27 - eDP VBT Block
  */
-- 
2.43.2

[PATCH 24/35] drm/i915/bios: Define VBT block 25 (SDVO LVDS PPS) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 25 (SDVO LVDS PPS).

Not 100% sure about the order of the fields as this is not
documented in the VBT spec anymore, but this order matches
what is included as part of the power sequencing SDVO commands
(struct sdvo_panel_power_sequencing). Also the real world
VBT data I have looks OK with this definition.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 8fe2ded884e3..c6d03905593d 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -972,6 +972,22 @@ struct bdb_sdvo_lvds_pnp_id {
struct bdb_edid_pnp_id pnp_id[4];
 } __packed;
 
+/*
+ * Block 25 - SDVO LVDS PPS
+ */
+
+struct sdvo_lvds_pps {
+   u16 t0; /* power on */
+   u16 t1; /* backlight on */
+   u16 t2; /* backlight off */
+   u16 t3; /* power off */
+   u16 t4; /* power cycle */
+} __packed;
+
+struct bdb_sdvo_lvds_pps {
+   struct sdvo_lvds_pps pps[4];
+} __packed;
+
 /*
  * Block 27 - eDP VBT Block
  */
-- 
2.43.2

[PATCH 23/35] drm/i915/bios: Define VBT block 24 (SDVO LVDS PnP ID) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 24 (SDVO LVDS PnP ID).

The descriotion is not part of the VBT spec anymore, but the layout
is rather obsvious.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 6216c1689901..8fe2ded884e3 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -964,6 +964,14 @@ struct bdb_sdvo_lvds_dtd {
struct bdb_edid_dtd dtd[4];
 } __packed;
 
+/*
+ * Block 24 - SDVO LVDS PnP ID
+ */
+
+struct bdb_sdvo_lvds_pnp_id {
+   struct bdb_edid_pnp_id pnp_id[4];
+} __packed;
+
 /*
  * Block 27 - eDP VBT Block
  */
-- 
2.43.2

[PATCH 22/35] drm/i915/bios: Define VBT block 21 (EFP List) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 21 (EFP List). Specs are nowhere
to be found, but real world data suggests that each entry is just
the first four bytes of the EDID PnP ID structure.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index a61ae39196b1..6216c1689901 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -921,6 +921,21 @@ struct bdb_oem_custom {
struct oem_mode modes[];
 } __packed;
 
+/*
+ * Block 21 - EFP List
+ */
+
+struct efp_entry {
+   u16 mfg_name;
+   u16 product_code;
+} __packed;
+
+struct bdb_efp_list {
+   u8 num_entries;
+   u8 entry_size;
+   struct efp_entry efp[];
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 21/35] drm/i915/bios: Define VBT block 20 (OEM Customizable Modes) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 20 (OEM Customizable Modes).
Each entry is either 26 or 28 bytes, depending on the BDB version.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 24 +++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 30d60835e4d0..a61ae39196b1 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -897,6 +897,30 @@ struct bdb_display_remove_old {
struct display_remove_entry_old table[];
 } __packed;
 
+/*
+ * Block 20 - OEM Customizable Modes
+ */
+
+struct oem_mode {
+   u8 enable_in_vbios:1;
+   u8 enable_in_os:1;
+   u8 enable_in_gop:1; /* 207+ */
+   u8 reserved:5;
+   u8 display_flags;   /* ???-216 */
+   u16 x_res;
+   u16 y_res;
+   u8 color_depth;
+   u8 refresh_rate;
+   struct bdb_edid_dtd dtd;
+   u16 display_flags_2;/* 217+ */
+} __packed;
+
+struct bdb_oem_custom {
+   u8 num_entries;
+   u8 entry_size;
+   struct oem_mode modes[];
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 20/35] drm/i915/bios: Define VBT blocks 19, 30, 32 (Display Configuration Removal Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contenst is VBT blocks 19,30,32 (Display Configuration
Removal Table) contents. There are three variants of this block:
pre-IVB, IVB, HSW+, with each having slightly different entries.

Curiously many HSW/BDW machines seem to have both the IVB and HSW+
variants in their VBTs simultanously. No idea why.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 47 ++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index cfa17a848105..30d60835e4d0 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -158,7 +158,7 @@ enum bdb_block_id {
BDB_DISPLAY_SELECT_OLD  = 16,
BDB_SV_TEST_FUNCTIONS   = 17,
BDB_DRIVER_ROTATION = 18,
-   BDB_DISPLAY_REMOVE  = 19,
+   BDB_DISPLAY_REMOVE_OLD  = 19,
BDB_OEM_CUSTOM  = 20,
BDB_EFP_LIST= 21, /* workarounds for VGA 
hsync/vsync */
BDB_SDVO_LVDS_OPTIONS   = 22,
@@ -168,7 +168,9 @@ enum bdb_block_id {
BDB_TV_OPTIONS  = 26,
BDB_EDP = 27,
BDB_DISPLAY_SELECT_IVB  = 29, /* 164+ */
+   BDB_DISPLAY_REMOVE_IVB  = 30, /* 164+ */
BDB_DISPLAY_SELECT_HSW  = 31, /* 166+ */
+   BDB_DISPLAY_REMOVE_HSW  = 32, /* 166+ */
BDB_LFP_OPTIONS = 40,
BDB_LFP_DATA_PTRS   = 41,
BDB_LFP_DATA= 42,
@@ -880,6 +882,21 @@ struct bdb_driver_rotation {
u32 rotation_flags_4;
 } __packed;
 
+/*
+ * Block 19 - Display Configuration Removal Table (pre-IVB)
+ */
+
+struct display_remove_entry_old {
+   u8 display_select_pipe_a;
+   u8 display_select_pipe_b;
+} __packed;
+
+struct bdb_display_remove_old {
+   u8 num_entries;
+   u8 entry_size;
+   struct display_remove_entry_old table[];
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
@@ -999,6 +1016,20 @@ struct bdb_display_select_ivb {
struct toggle_list_table_ivb tables[4];
 } __packed;
 
+/*
+ * Block 30 - Display Configuration Removal Table (IVB)
+ */
+
+struct display_remove_entry_ivb {
+   u8 display_select;
+} __packed;
+
+struct bdb_display_remove_ivb {
+   u8 num_entries;
+   u8 entry_size;
+   struct display_remove_entry_ivb table[];
+} __packed;
+
 /*
  * Block 31 - Toggle List Block (HSW+)
  */
@@ -1018,6 +1049,20 @@ struct bdb_display_select_hsw {
struct toggle_list_table_hsw tables[4];
 } __packed;
 
+/*
+ * Block 32 - Display Configuration Removal Table (HSW+)
+ */
+
+struct display_remove_entry_hsw {
+   u16 display_select;
+} __packed;
+
+struct bdb_display_remove_hsw {
+   u8 num_entries;
+   u8 entry_size;
+   struct display_remove_entry_hsw table[];
+} __packed;
+
 /*
  * Block 40 - LFP Data Block
  */
-- 
2.43.2

[PATCH 19/35] drm/i915/bios: Define VBT blocks 16, 29, 31 (Toggle List) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contenst is VBT blocks 16,19,31 (Toggle List).
There are three variants of this block: pre-IVB, IVB, HSW+,
with each having slightly different entries.

Curiously many HSW/BDW machines seem to have both the IVB and
HSW+ variants in their VBTs simultanously. No idea why.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 63 ++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2792da3c916e..cfa17a848105 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -155,7 +155,7 @@ enum bdb_block_id {
BDB_DRIVER_PERSISTENCE  = 13,
BDB_EXT_TABLE_PTRS  = 14, /* VBIOS only */
BDB_DOT_CLOCK_OVERRIDE  = 15,
-   BDB_DISPLAY_SELECT  = 16,
+   BDB_DISPLAY_SELECT_OLD  = 16,
BDB_SV_TEST_FUNCTIONS   = 17,
BDB_DRIVER_ROTATION = 18,
BDB_DISPLAY_REMOVE  = 19,
@@ -167,6 +167,8 @@ enum bdb_block_id {
BDB_SDVO_LVDS_PPS   = 25,
BDB_TV_OPTIONS  = 26,
BDB_EDP = 27,
+   BDB_DISPLAY_SELECT_IVB  = 29, /* 164+ */
+   BDB_DISPLAY_SELECT_HSW  = 31, /* 166+ */
BDB_LFP_OPTIONS = 40,
BDB_LFP_DATA_PTRS   = 41,
BDB_LFP_DATA= 42,
@@ -837,6 +839,27 @@ struct bdb_dot_clock_override {
struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */
 } __packed;
 
+/*
+ * Block 16 - Toggle List Block (pre-HSW)
+ */
+
+struct toggle_list_entry_old {
+   u8 display_select_pipe_a;
+   u8 display_select_pipe_b;
+   u8 caps;
+} __packed;
+
+struct toggle_list_table_old {
+   u16 num_entries;
+   u8 entry_size;
+   struct toggle_list_entry_old list[];
+} __packed;
+
+struct bdb_display_select_old {
+   /* each table has variable size! */
+   struct toggle_list_table_old tables[4];
+} __packed;
+
 /*
  * Block 17 - SV Test Functions
  */
@@ -957,6 +980,44 @@ struct bdb_edp {
u16 edp_dsc_disable;/* 251+ */
 } __packed;
 
+/*
+ * Block 29 - Toggle List Block (IVB)
+ */
+
+struct toggle_list_entry_ivb {
+   u8 display_select;
+} __packed;
+
+struct toggle_list_table_ivb {
+   u16 num_entries;
+   u8 entry_size;
+   struct toggle_list_entry_ivb list[];
+} __packed;
+
+struct bdb_display_select_ivb {
+   /* each table has variable size! */
+   struct toggle_list_table_ivb tables[4];
+} __packed;
+
+/*
+ * Block 31 - Toggle List Block (HSW+)
+ */
+
+struct toggle_list_entry_hsw {
+   u16 display_select;
+} __packed;
+
+struct toggle_list_table_hsw {
+   u16 num_entries;
+   u8 entry_size;
+   struct toggle_list_entry_hsw list[];
+} __packed;
+
+struct bdb_display_select_hsw {
+   /* each table has variable size! */
+   struct toggle_list_table_hsw tables[4];
+} __packed;
+
 /*
  * Block 40 - LFP Data Block
  */
-- 
2.43.2

[PATCH 16/35] drm/i915/bios: Define ALM only VBT block 9 contents

[Ville Syrjala]

From: Ville Syrjälä 

For some reason ALM VBT has two dot clock override tables.
One as the normal block 15 and a second one as block 9.
The table in block 9 has no row_size/num_rows information.

On my Fujitsu Lifebook S6010 only the block 9 table has actual
data in it. Block 15 is present but all zeroes.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 31 ---
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index c2f73c7d9412..b836dee09f59 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -147,6 +147,7 @@ enum bdb_block_id {
BDB_EXT_MMIO_REGS   = 6, /* VBIOS only */
BDB_SWF_IO  = 7, /* VBIOS only */
BDB_SWF_MMIO= 8, /* VBIOS only */
+   BDB_DOT_CLOCK_OVERRIDE_ALM  = 9,
BDB_PSR = 9, /* 165+ */
BDB_MODE_REMOVAL_TABLE  = 10,
BDB_CHILD_DEVICE_TABLE  = 11,
@@ -650,6 +651,25 @@ struct bdb_reg_table {
/* u16 table_end_marker; */
 } __packed;
 
+/*
+ * Block 9 - Undocumented table (ALM only)
+ */
+
+struct dot_clock_override_entry_gen2 {
+   u32 dotclock;
+   u8 n;
+   u8 m1;
+   u8 m2;
+   u8 p1:5;
+   u8 p1_div_by_2:1;
+   u8 reserved:1;
+   u8 p2_div_by_4:1;
+} __packed;
+
+struct bdb_dot_clock_override_alm {
+   struct dot_clock_override_entry_gen2 t[0];
+} __packed;
+
 /*
  * Block 9 - SRD Feature Block
  */
@@ -801,17 +821,6 @@ struct bdb_driver_persistence {
  * Block 15 - Dot Clock Override Table
  */
 
-struct dot_clock_override_entry_gen2 {
-   u32 dotclock;
-   u8 n;
-   u8 m1;
-   u8 m2;
-   u8 p1:5;
-   u8 p1_div_by_2:1;
-   u8 reserved:1;
-   u8 p2_div_by_4:1;
-} __packed;
-
 struct dot_clock_override_entry_gen3 {
u32 dotclock;
u8 n;
-- 
2.43.2

[PATCH 18/35] drm/i915/bios: Define VBT block 18 (Driver Rotation) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of block 18 (Driver Rotation).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index c97bca5d12d1..2792da3c916e 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -845,6 +845,18 @@ struct bdb_sv_test_functions {
u8 sv_bits[8];
 } __packed;
 
+/*
+ * Block 18 - Driver Rotation
+ */
+
+struct bdb_driver_rotation {
+   u8 rotation_enable;
+   u8 rotation_flags_1;
+   u16 rotation_flags_2;
+   u32 rotation_flags_3;
+   u32 rotation_flags_4;
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 17/35] drm/i915/bios: Define VBT block 17 (SV Test Functions) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 17 (SV Test Functions).
Nothing real here for us, but might as well define it for
completeness.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index b836dee09f59..c97bca5d12d1 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -156,6 +156,7 @@ enum bdb_block_id {
BDB_EXT_TABLE_PTRS  = 14, /* VBIOS only */
BDB_DOT_CLOCK_OVERRIDE  = 15,
BDB_DISPLAY_SELECT  = 16,
+   BDB_SV_TEST_FUNCTIONS   = 17,
BDB_DRIVER_ROTATION = 18,
BDB_DISPLAY_REMOVE  = 19,
BDB_OEM_CUSTOM  = 20,
@@ -836,6 +837,14 @@ struct bdb_dot_clock_override {
struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */
 } __packed;
 
+/*
+ * Block 17 - SV Test Functions
+ */
+
+struct bdb_sv_test_functions {
+   u8 sv_bits[8];
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 15/35] drm/i915/bios: Define VBT block 15 (Dot Clock Override Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 15 (Dot Clock Override Table)

The contents were reverse engineered by intuition. The gen2 stuff
seems solid as I can verify that against real world VBT data. The
gen3 stuff less so as all the gen3+ VBTs I have just filla the
entire block with zeroes.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 30 +++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2075d53ca317..c2f73c7d9412 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -797,6 +797,36 @@ struct bdb_driver_persistence {
u8 persistent_max_config;
 } __packed;
 
+/*
+ * Block 15 - Dot Clock Override Table
+ */
+
+struct dot_clock_override_entry_gen2 {
+   u32 dotclock;
+   u8 n;
+   u8 m1;
+   u8 m2;
+   u8 p1:5;
+   u8 p1_div_by_2:1;
+   u8 reserved:1;
+   u8 p2_div_by_4:1;
+} __packed;
+
+struct dot_clock_override_entry_gen3 {
+   u32 dotclock;
+   u8 n;
+   u8 m1;
+   u8 m2;
+   u8 p1;
+   u8 p2;
+} __packed;
+
+struct bdb_dot_clock_override {
+   u8 row_size; /* 8 == gen2, 9 == gen3+ */
+   u8 num_rows;
+   struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 14/35] drm/i915/bios: Define VBT block 12 (Driver Persistent Algorithm) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 12 (Driver Persistent Algorithm).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index d78523cd4214..2075d53ca317 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -778,6 +778,25 @@ struct bdb_driver_features {
u16 pc_feature_valid:1; /* 159+ */
 } __packed;
 
+/*
+ * Block 13 - Driver Persistent Algorithm
+ */
+
+struct bdb_driver_persistence {
+   u16 hotkey_persistent_algorithm:1;
+   u16 lid_switch_persistent_algorithm:1;
+   u16 power_management_persistent_algorithm:1;
+   u16 hotkey_persistent_on_mds_twin:1;
+   u16 hotkey_persistent_on_refresh_rate:1;
+   u16 hotkey_persistent_on_restore_pipe:1;
+   u16 hotkey_persistent_on_mode:1;
+   u16 edid_persistent_on_mode:1;
+   u16 dvo_hotplug_persistent_on_mode:1;
+   u16 docking_persistent_algorithm:1;
+   u16 rsvd:6;
+   u8 persistent_max_config;
+} __packed;
+
 /*
  * Block 22 - SDVO LVDS General Options
  */
-- 
2.43.2

[PATCH 13/35] drm/i915/bios: Define VBT block 10 (Mode Removal Table) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 10 (Mode Removal Table).

There seem to be two variants:
- 8 byte entries for desktop systems
- 10 byte entries for mobile systems, with the extra
  panel_flags being a bitmask of LFPs

It seems starting from HSW only the mobile variant is
used anymore.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 4f0b8be3034c..d78523cd4214 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -677,6 +677,29 @@ struct bdb_psr {
u32 psr2_tp2_tp3_wakeup_time;   /* 226+ */
 } __packed;
 
+/*
+ * Block 10 - Mode Removal Table
+ */
+
+struct mode_removal_table {
+   u16 x_res;
+   u16 y_res;
+   u8 bpp;
+   u16 refresh_rate;
+   u8 removal_flags;
+   u16 panel_flags;
+} __packed;
+
+struct bdb_mode_removal {
+   u8 row_size; /* 8 or 10 bytes */
+   /*
+* VBT spec says this is always 20 entries,
+* but ALM seems to have only 15 entries.
+*/
+   struct mode_removal_table modes[];
+   /* u16 terminator; 0x */
+} __packed;
+
 /*
  * Block 12 - Driver Features Data Block
  */
-- 
2.43.2

[PATCH 12/35] drm/i915/bios: Define VBT blocks 6, 7, 8 (register tables) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents for VBT blocks:
- Block 6 (Extended MMIO Register Table)
- Block 7 (IO Software Flag Table)
- Block 8 (MMIO SWF Register Table)

All of these use the same basic layout, with two known variants:
- data_access_size==0xce -> offset,value tuples are u8,u8
- data_access_size==0x02 -> offset,value tuples are u32,u32

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f3478a20ff16..4f0b8be3034c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -634,6 +634,22 @@ struct bdb_generic_mode_table_mgm {
struct generic_mode_timings timings[3];
 } __packed;
 
+/*
+ * Block 6 - Extended MMIO Register Table, VBIOS only
+ * Block 7 - IO Software Flag Table, VBIOS only
+ * Block 8 - MMIO SWF Register Table, VBIOS only
+ */
+struct bdb_reg_table {
+   u16 table_id;
+   u8 data_access_size;
+   /*
+* offset,value tuples:
+* data_access_size==0xce -> u8,u8
+* data_access_size==0x02 -> u32,u32
+*/
+   /* u16 table_end_marker; */
+} __packed;
+
 /*
  * Block 9 - SRD Feature Block
  */
-- 
2.43.2

[PATCH 11/35] drm/i915/bios: Define VBT block 5 (Generic Mode Table)

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 5 (Generic Mode Table).

Details were mostly gleaned from some VBIOS sources.

There are apparently two variants of the block: ALM only
vs. MGM, defined here as bdb_generic_mode_table_alm
and bdb_generic_mode_table_mgm. And those are the only two
platforms where I've seen this block.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 54 +++
 1 file changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index c9ecf3b48999..f3478a20ff16 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -580,6 +580,60 @@ struct bdb_mode_support_list {
u16 mode_list_length;
 } __packed;
 
+/*
+ * Block 5 - Generic Mode Table
+ */
+
+struct generic_mode_table {
+   u16 x_res;
+   u16 y_res;
+   u8 color_depths;
+   u8 refresh_rate[3];
+   u8 reserved;
+   u8 text_cols;
+   u8 text_rows;
+   u8 font_height;
+   u16 page_size;
+   u8 misc;
+} __packed;
+
+struct generic_mode_timings {
+   u32 dotclock_khz;
+   u16 hdisplay;
+   u16 htotal;
+   u16 hblank_start;
+   u16 hblank_end;
+   u16 hsync_start;
+   u16 hsync_end;
+   u16 vdisplay;
+   u16 vtotal;
+   u16 vblank_start;
+   u16 vblank_end;
+   u16 vsync_start;
+   u16 vsync_end;
+} __packed;
+
+struct generic_mode_timings_alm {
+   struct generic_mode_timings timings;
+   u8 wm_8bpp;
+   u8 burst_8bpp;
+   u8 wm_16bpp;
+   u8 burst_16bpp;
+   u8 wm_32bpp;
+   u8 burst_32bpp;
+} __packed;
+
+struct bdb_generic_mode_table_alm {
+   struct generic_mode_table table;
+   struct generic_mode_timings_alm timings[3];
+} __packed;
+
+struct bdb_generic_mode_table_mgm {
+   u16 mode_flag;
+   struct generic_mode_table table;
+   struct generic_mode_timings timings[3];
+} __packed;
+
 /*
  * Block 9 - SRD Feature Block
  */
-- 
2.43.2

[PATCH 10/35] drm/i915/bios: Define VBT block 4 (Mode Support List) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 4 (Mode Support List).

Slightly crazy layout with a variable length list at the start,
followed by the length of said list.

No real idea what these "Intel mode numbers" really are. What
I see in real world VBTs seems to be always the same list of
26 numbers, ranging between 0x30 and 0x84.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 7df0a6044425..c9ecf3b48999 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -571,6 +571,15 @@ struct bdb_display_toggle {
u16 list[]; /* ALM only */
 } __packed;
 
+/*
+ * Block 4 - Mode Support List
+ */
+
+struct bdb_mode_support_list {
+   u8 intel_mode_number[0];
+   u16 mode_list_length;
+} __packed;
+
 /*
  * Block 9 - SRD Feature Block
  */
-- 
2.43.2

[PATCH 09/35] drm/i915/bios: Define VBT block 3 (Display Toggle Option) contents

[Ville Syrjala]

From: Ville Syrjälä 

Define the contents of VBT block 3 (Display Toggle Option).

On modern VBTs this is just a single byte, but on ALM there is
also some extra to do with toggle lists or something.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 18f54311a6e8..7df0a6044425 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -141,7 +141,7 @@ struct bdb_header {
 enum bdb_block_id {
BDB_GENERAL_FEATURES= 1,
BDB_GENERAL_DEFINITIONS = 2,
-   BDB_OLD_TOGGLE_LIST = 3,
+   BDB_DISPLAY_TOGGLE  = 3,
BDB_MODE_SUPPORT_LIST   = 4,
BDB_GENERIC_MODE_TABLE  = 5,
BDB_EXT_MMIO_REGS   = 6, /* VBIOS only */
@@ -561,6 +561,16 @@ struct bdb_general_definitions {
u8 devices[];
 } __packed;
 
+/*
+ * Block 3 - Display Toggle Option Block
+ */
+
+struct bdb_display_toggle {
+   u8 feature_bits;
+   u16 num_entries;/* ALM only */
+   u16 list[]; /* ALM only */
+} __packed;
+
 /*
  * Block 9 - SRD Feature Block
  */
-- 
2.43.2

[PATCH 08/35] drm/i915/bios: Add version notes for some blocks

[Ville Syrjala]

From: Ville Syrjälä 

Document which VBT blocks were defined in which BDB version,
for the cases where the spec actually states this accurately.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 0533025d133b..18f54311a6e8 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -147,7 +147,7 @@ enum bdb_block_id {
BDB_EXT_MMIO_REGS   = 6, /* VBIOS only */
BDB_SWF_IO  = 7, /* VBIOS only */
BDB_SWF_MMIO= 8, /* VBIOS only */
-   BDB_PSR = 9,
+   BDB_PSR = 9, /* 165+ */
BDB_MODE_REMOVAL_TABLE  = 10,
BDB_CHILD_DEVICE_TABLE  = 11,
BDB_DRIVER_FEATURES = 12,
@@ -170,10 +170,10 @@ enum bdb_block_id {
BDB_LFP_DATA= 42,
BDB_LFP_BACKLIGHT   = 43,
BDB_LFP_POWER   = 44,
-   BDB_MIPI_CONFIG = 52,
-   BDB_MIPI_SEQUENCE   = 53,
-   BDB_COMPRESSION_PARAMETERS  = 56,
-   BDB_GENERIC_DTD = 58,
+   BDB_MIPI_CONFIG = 52, /* 175+ */
+   BDB_MIPI_SEQUENCE   = 53, /* 177+ */
+   BDB_COMPRESSION_PARAMETERS  = 56, /* 213+ */
+   BDB_GENERIC_DTD = 58, /* 229+ */
BDB_SKIP= 254, /* VBIOS only */
 };
 
-- 
2.43.2