[Intel-gfx] [PATCH v3] drm/i915: add schedule out notification of preempted but completed request

the preempted request has been completed. v2: - refine description, add completed check and notification in execlists_cancel_port_requests. (Chris) v3: - use ternary confitional, remove local variable. (Tvrtko) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Weinan Li <

[Intel-gfx] [PATCH v2] drm/i915: add schedule out notification of preempted but completed request

the preempted request has been completed. v2: - refine description, add completed check and notification in execlists_cancel_port_requests. (Chris) Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Weinan Li <weinan.z...@intel.com> Signed-off-by: Zhenyu Wang <zhen...@

[Intel-gfx] [PATCH] drm/i915: add schedule out notification of completed request during unwind

There is one corner case missing schedule out notification for GVT-g in __unwind_incomplete_requests, it may cause vgpu no response. Add notification when ensure one request has been completed during doing unwind. Signed-off-by: Weinan Li <weinan.z...@intel.com> Signed-off-by: Zhenyu Wang

[Intel-gfx] [PATCH v2 3/4] drm/i915/gvt: refine mocs save restore policy

switch. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++ drivers/gpu/drm/i915/gvt/mmio_context.c | 33 ++--- 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH v2 1/4] drm/i915/gvt: refine trace_render_mmio

Refine trace_render_mmio to show the vm id before and after vgpu switch, tag host id as '0', this patch will be used in the future patch for refine mocs switch policy. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++-- drivers/gpu/drm/i9

[Intel-gfx] [PATCH v2 2/4] drm/i915/gvt: optimize for vGPU mmio switch

mmio save/restore, it will reduce the CPU utilization and performance while there is multi VMs with heavy work load. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/mmio_context.c | 196 ++-- 1 file changed, 85 insertions(+), 111 del

[Intel-gfx] [PATCH v2 4/4] drm/i915/gvt: load host render mocs once in mocs switch

Load host render mocs registers once for delta update of mocs switch, it reduces mmio read times obviously, then brings performance improvement during multi-vms switch. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/mmio_context.

[Intel-gfx] [PATCH v2 0/4] mmio save restore refine in vgpu switch

Weinan Li (4): drm/i915/gvt: refine trace_render_mmio drm/i915/gvt: optimize for vGPU mmio switch drm/i915/gvt: refine mocs save restore policy drm/i915/gvt: load host render mocs once in mocs switch drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++ drivers/gpu/drm/i915/gvt/mmio_context.c

[Intel-gfx] [PATCH 2/3] drm/i915/gvt: refine mocs save restore policy

switch. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++ drivers/gpu/drm/i915/gvt/render.c | 33 ++--- 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 3/3] drm/i915/gvt: load host render mocs once in mocs switch

Load host render mocs registers once for delta update of mocs switch, it reduces mmio read times obviously, then brings performance improvement during multi-vms switch. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/render.

[Intel-gfx] [PATCH 0/3] mmio save restore refine in vgpu switch

Merge switch_mmio_to_vgpu and switch_mmio_to_host, use delta update for mocs save restore, deal host mocs value as fixed, it won't be changed after initialization. These can save vgpu switch time to reduce CPU utilization and improve GPU performance in GVT-g with multi-VMs. Weinan Li (3): drm

[Intel-gfx] [PATCH 1/3] drm/i915/gvt: optimize for vGPU mmio switch

mmio save/restore, it will reduce the CPU utilization and performance while there is multi VMs with heavy work load. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/render.c | 212 -- drivers/gpu/drm/i915/gvt/trace.h | 15

[Intel-gfx] [PATCH] drm/i915/gvt: remove skl_misc_ctl_write handler

". Cc: Zhi Wang <zhi.a.w...@intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> Signed-off-by: Xiong Zhang <xiong.y.zh...@intel.com> --- drivers/gpu/drm/i915/gvt/handlers.c | 45 + 1 file changed, 5 insertions(+), 40 deletions(-)

[Intel-gfx] [PATCH v6] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

virtual HWSP caps check function. v6 : Comments refine. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 1 + drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH v5] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

virtual HWSP caps check function. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pvinfo.h | 1 + drivers/gpu/drm/i915/i915_vgpu.h | 6 +

[Intel-gfx] [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all the host support this feature, need to check the BIT(3) of caps in PVINFO. v3 : Remove unnecessary comments. v4 : Separate VM enable patch with GVT-g implementation patch due to code dependency Signed-off-by: Weinan Li

[Intel-gfx] [PATCH v3 0/2] enable virtual HWSP in GVT-g

v2 : clean merge confict v3 : remove unnecessary comments add address audit in HWSP address update Weinan Li (2): drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM drivers/gpu/drm/i915/gvt

[Intel-gfx] [PATCH v3 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

address audit in HWSP address update. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gvt/execlist.c | 17 ++ drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/han

[Intel-gfx] [PATCH v3 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all the host support this feature, need to check the BIT(3) of caps in PVINFO. v3 : Remove unnecessary comments. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joo

[Intel-gfx] [PATCH v2 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all the host support this feature, need to check the BIT(3) of caps in PVINFO. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_vgpu.

[Intel-gfx] [PATCH v2 0/2] enable virtual HWSP in GVT-g

V2: clean merge confict. Weinan Li (2): drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM drivers/gpu/drm/i915/gvt/execlist.c| 16 + drivers/gpu/drm/i915/gvt/gvt.h | 1

[Intel-gfx] [PATCH v2 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gvt/execlist.c | 16 ++ drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 42 +++-- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gvt/execlist.c | 14 + drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 41 +++-- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all the host support this feature, need to check the BIT(3) of caps in PVINFO. Signed-off-by: Weinan Li <weinan.z...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH v7] drm/i915: return the correct usable aperture size under gvt environment

l.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Zhenyu Wang <zhen...@linux.intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH v6] drm/i915: return the correct usable aperture size under gvt environment

<ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Zhenyu Wang <zhen...@linux.intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + driv

[Intel-gfx] [PATCH v5] drm/i915/gvt: return the correct usable aperture size under gvt environment

c: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + drivers/gpu/drm/i915/i915_vgpu.c| 44 ++--- 3 files

[Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

teardown to balloon and deballoon to make sure the reserved stays correct. Code style refine. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4

[Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

teardown to balloon and deballoon to make sure the reserved stays correct. Code style refine. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4

[Intel-gfx] [PATCH v3] drm/i915/gvt: return the actual aperture size under gvt environment

the reserved size in ggtt by balloon. v3: remain aper_size as total, adjust aper_available_size exclude reserved and pinned. UMD driver need to adjust the max allocation size according to the available aperture size but not total size. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- d

[Intel-gfx] [PATCH v2] drm/i915/gvt: return the actual aperture size under gvt environment

, we also need to exclude the reserved part in GTT. v2: add 'reserved' in struct i915_address_space to record the reserved size in ggtt by balloon. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 6 ++ drivers/gpu/drm/i915/i915_gem_context

[Intel-gfx] [PATCH] drm/i915/gvt: return the actual aperture size under gvt environment

the reserved part by balloon. I915_GEM_CONTEXT_GETPARAM ioctl query the I915_CONTEXT_PARAM_GTT_SIZE, we also need to exclude the reserved part in GTT. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 7 +++ drivers/gpu/drm/i915/i915_gem_context.

[Intel-gfx] [PATCH] drm/i915/gvt: add pcode read/write emulation of BDW

Add pcode read/write emulation in gvt for BDW. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/gvt/handlers.c | 33 ++--- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/g

[Intel-gfx] [PATCH] drm/i915: check status and reply value both in skl_pcode_try_request()

skl_pcode_try_request() call sandybridge_pcode_read(), check both return status and value simultanously, ensure it got correct value without error. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Intel-gfx] [PATCH v3 2/2] drm/i915: clean up unused vgpu_read/write

Having converted the force_wake_get/_put routines for a vGPU to be no-op, we can use the common mmio accessors and remove our specialised routines that simply skipped the calls to control force_wake. Signed-off-by: Weinan Li <weinan.z...@intel.com> Reviewed-by: Chris Wilson <ch

[Intel-gfx] [PATCH v3 1/2] drm/i915: noop forcewake get/put when vgpu activated

(making our vgpu specific mmio routines redundant and to be removed in the next patch). Signed-off-by: Weinan Li <weinan.z...@intel.com> Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_uncore.c | 13 + 1 file changed, 13 insertions(+)

[Intel-gfx] [PATCH v2 3/3] drm/i915: clean up unused vgpu_read/write

Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 58 - 1 file changed, 58 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9fad4de..e9046fa 100644 --- a/d

[Intel-gfx] [PATCH v2 2/3] drm/i915: noop forcewake get/put when vgpu activated

t;. Unnecessary MMIO access in guest waste much CPU cost. Since we full virtualize the MMIO, just noop the forcewake get/put. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH 1/2] drm/i915: ignore posting read when using vgpu

No need to do posting read when vgpu actived. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5

[Intel-gfx] [PATCH 2/2] drm/i915: ignore forcewake get/put when using vgpu

t;. Unnecessary MMIO access in guest waste much CPU cost. Since we full virtualize the MMIO, just ignore the forcewake get/put in low level. Signed-off-by: Weinan Li <weinan.z...@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 78 ++--- 1 file changed, 20 i