Replace all occurences of ADL -> ALDERLAKE in
platform and subplatform defines. This way there is a
consistent pattern to how platforms are referred. While
the change is minor and could be combined to have lesser patches,
splitting to per subpaltform for easier cherrypicks, if needed.
Anu
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915
Driver refers to the platfrom Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
drivers/gpu/drm/i915
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_step.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu
Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
MTL supports both squash and crawl.
Cc: Clint Taylor
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf3b28d71d2b..d82f118809e9
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 181 +-
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 177 +-
ooking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 175 +
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
R)
- s/cdclk_crawl_and_squash/cdclk_compute_crawl_squash_midpoint
- Cleanup Pcode checks in bxt_set_cdclk()
- Correct unsigned/signed checks
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 163 -
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
with a valid frequency.
However the vco is declared as a unsigned variable.
With the above assumption, driver takes crawl path when not needed.
Add explicit check to not crawl in the case of an invalid PLL.
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 161 +
1 file changed, 133 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/g
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/g
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +-
1 file
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/g
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
1 file changed, 129 inse
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display
No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm
No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
1
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15
.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Anusha Srivatsa (4):
drm/i915/display: Change terminology for cdclk actions
drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
drm/i915/display: Move chunks of code out of bxt_set_cdclk()
drm/i915/display: Move squash_ctl register programming to
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15
No functional change. Introduce dg2_cdclk_squash_programming and
move squash_ctl register programming bits to this.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
1 file changed, 14
in terms of checking
if the platform supports them or not. With the changes introduced,
both are a display feature flag.
- Move code from bxt_set_cdclk() to make it more modularized
and easy to read and understand.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Anusha Srivatsa (4):
drm/
No functional change. Moving segments out to simplify
bxt_set_cdlck()
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16
crawl capability checks.(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
1 file changed, 128 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/d
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
the
previous debugs entries to reflect which firmware is needed
and if the needed firmware is loaded or not.
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC.
BSpec: 49788
Cc: Lucas De Marchi
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
the
previous debugs entries to reflect which firmware is needed
and if the needed firmware is loaded or not.
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC.
BSpec: 49788
Cc: Lucas De Marchi
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
adding the cdclk table, align cdclk support with the
new cdclk_crawl_and_squash() introduced in previous patch.
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +-
1 file changed, 93 insertions(+), 2
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
ed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 121 -
1 file changed, 96 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a12e86
Add a helper function to get stringify values of the
desired cdclk action and dump it with rest of the
cdclk config values
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git
Modularising steps and moving them out of
bxt_set_cdclk().
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915
Populate the new struct steps for the legacy modeset
case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +-
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
The struct has the action to be performed - squash, crawl
or modeset and the corresponding cdclk which is the desired
cdclk. This is the structure that gets populated during
atomic check once it is determined what the cdclk change looks
like
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
Populate the new struct steps for squash case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
Populate the new struct steps for crawl case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
Cc: Rodrigo Vivi
Anusha Srivatsa (6):
drm/i915/display Add dg2_prog_squash_ctl() helper
drm/i915/display: add cdclk action struct to cdclk_config
drm/i915/display: Embed the new struct steps for squashing
drm/i915/display: Embed the new struct steps for crawling
drm/i915/display: Embed
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move crawling steps to a switch case (anusha)
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move squashing bits to switch case.(Anusha)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c
to intel_cdclk_squash()
and intel_cdclk_crawl().
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 61 ++
1 file changed, 38 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
this.
Anusha Srivatsa (4):
drm/i915/display: Add CDCLK actions to intel_cdclk_state
drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash
drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
drm/i915/display: Add cdclk checks to atomic check
drivers/gpu/drm/i915/display
With the latest DMC in place, enabling DC5 on DG2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915
With the latest DMC in place, enabling DC5 on DG2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915
to intel_cdclk_squash()
and intel_cdclk_crawl().
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 108 +++--
1 file changed, 77 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++---
1 file changed, 11
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++--
1 file changed, 11
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
: Matt Roper
Anusha Srivatsa (4):
drm/i915/display: Add CDCLK actions to intel_cdclk_state
drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
drm/i915/display: Add cdclk checks to atomic check
drivers/gpu/drm/i915/display
The intention is to check for squashing, crawling conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate this.
Anusha
Cleanup the intel_phy_is_combo
to accommodate for cases where combo phy is not available.
v2: retain comment that explains DG2 returning false from
intel_phy_is_combo() (Arun)
Cc: Arun R Murthy
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Roper
Reviewed-by: Arun R Murthy
gen11_gu_misc_irq_handler() and gen11_gu_misc_ack() do nothing tile
specific.
v2: gen11_gu_misc_irq_ack() tile agnostic like gen11_gu_misc_irq_handler()
(Tvrtko)
Cc: Tvrtko Ursulin
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_irq.c | 16
1 file
No functional change. Cleanup the intel_phy_is_combo
to accommodate for cases where combo phy is not available.
v2: retain comment that explains DG2 returning false from
intel_phy_is_combo() (Arun)
Cc: Arun R Murthy
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
No functional change. Cleanup the intel_phy_is_combo
to accomodate for cases where combo phy is not available.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu
gen11_gu_misc_irq_handler() does not do anything tile specific.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_irq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
Enable DC5 on dg2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44
up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 42
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 42
up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 43 +++
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 +++-
2 files changed
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu/drm/i915/display/intel_dmc.c
up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 43 +++
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 +++-
2 files changed
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