[Intel-gfx] [PATCH v2 1/2] drm/i915: Add 16bit register/mask operators

Add the support macros to define/extract bits as 16bits. v2: checkpatch fixes Reviewed-by: Gustavo Sousa Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg_defs.h | 48 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h

[Intel-gfx] [PATCH v2 0/2] C20 Computed HDMI TMDS pixel clocks

Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz modes. Add 16 Bit mask operators to support C20 phy programming. v2: checkpatch fixes BSPEC: 64568 Cc: Imre Deak Cc: Mika Kahola Cc: Radhakrishna Sripada Cc: Gustavo Sousa Signed-off-by: Clint Taylor Clint Taylor (2

[Intel-gfx] [PATCH v2 2/2] drm/i915/hdmi: C20 computed PLL frequencies

Use algorithm to generate HDMI C20 PLL clock frequencies. i v2: checkpatch fixes BSPEC: 64568 Cc: Radhakrishna Sripada Cc: Mika Kahola Cc: Anusha Srivatsa Reviewed-by: Gustavo Sousa Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89

[Intel-gfx] [PATCH 2/2] drm/i915/hdmi: C20 computed PLL frequencies

Use algorithm to generate HDMI C20 PLL clock frequencies. BSPEC: 64568 Cc: Radhakrishna Sripada Cc: Mika Kahola Cc: Anusha Srivatsa Cc: Gustavo Sousa Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89 +-- .../gpu/drm/i915/display

[Intel-gfx] [PATCH 0/2] C20 Computed HDMI TMDS pixel clocks

Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz modes. Add 16 Bit mask operators to support C20 phy programming. BSPEC: 64568 Cc: Imre Deak Cc: Mika Kahola Cc: Radhakrishna Sripada Cc: Gustavo Sousa Signed-off-by: Clint Taylor Clint Taylor (2): drm/i915: Add

[Intel-gfx] [PATCH 1/2] drm/i915: Add 16bit register/mask operators

Add the support macros to define/extract bits as 16bits. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg_defs.h | 49 1 file changed, 49 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index

Re: [Intel-gfx] [PATCH 13/13] drm/i915/mtl: Enable TC ports

); + intel_ddi_init(dev_priv, PORT_TC3); + intel_ddi_init(dev_priv, PORT_TC4); Reviewed-by: Clint Taylor -Clint } else if (IS_DG2(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B);

[Intel-gfx] [PATCH] drm/i915/audio: update audio keepalive clock values

BSPEC has updated the cdclk audio keepalives AUD_TS_CDCLK_M value to 60 for all supported platforms and refclks. BSPEC: 54034 BSPEC: 55409 BSPEC: 65243 Cc: Kai Vehmanen Cc: Uma Shankar Cc: Ville Syrjälä Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_audio.c | 6 +- 1

[Intel-gfx] [PATCH] drm/i915/display: Audio keep alive timestamp cdclk divisors

From: "Taylor, Clinton A" Use BSPEC values for the Audio Keep alive M and N values as included in the cdclk BSPEC pages for display > 13 BSPEC: 54034, 55409 Cc: Kai Vehmanen Cc: Uma Shankar Cc: Ville Syrjälä Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_audio.c |

[Intel-gfx] [PATCH] drm/i915/dgfx: DGFX uses direct VBT pin mapping

DDC pin mapping for DGFX cards uses direct VBT pin mapping Cc: Lucas De Marchi Cc: Matt Roper Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_bios.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers

Re: [Intel-gfx] [PATCH] drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence

Matches BSPEC for DKL Phy. Reviewed-by: Clint Taylor -Clint On 1/13/22 9:48 AM, José Roberto de Souza wrote: TC voltage swing programming sequence was updated with a new step. BSpec: 54956 Cc: sta...@vger.kernel.org Cc: Jani Nikula Cc: Clint Taylor Cc: Imre Deak Signed-off-by: José

Re: [Intel-gfx] [PATCH] drm/i915/display/ehl: Update voltage swing table

matches BSPEC. Reviewed-by: Clint Taylor -Clint On 1/13/22 8:04 AM, José Roberto de Souza wrote: EHL table was recently updated with some minor fixes. BSpec: 21257 Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 10

Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/dg2: extend Wa_1409120013 to DG2

Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: From: Matt Atwood Extend existing workaround 1409120013 to DG2. Cc: José Roberto de Souza Signed-off-by: Matt Atwood Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2

Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/dg2: Add Wa_16013000631

Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: From: Ramalingam C Invalidate IC cache through pipe control command as part of the ctx restore flow through indirect ctx pointer. v2: - Move pipe control from xcs indirect context to the rcs indirect context

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/dg2: Add Wa_16011777198

Correct, Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: Coarse power gating for render should not be enabled on some DG2 steppings. Bspec: 52698 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++ 1 file changed, 11

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/dg2: Add Wa_14010547955

Looks correct. Reviewed-by: Clint Taylor -Clint On 11/16/21 9:48 AM, Matt Roper wrote: This workaround is documented a bit strangely in the bspec; it's listed as an A0 workaround, but the description clarifies that the workaround is implicitly handled by the hardware and what the driver

Re: [Intel-gfx] [PATCH 1/3] drm/i915/xehpsdv: Add initial workarounds

Reviewed-by: Clint Taylor -Clint On 11/2/21 3:25 PM, Matt Roper wrote: From: Stuart Summers Add the initial set of workarounds for Xe_HP SDV. There are some additional workarounds specific to the compute engines that we're holding back for now. Those will be added later, after general

Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg2: Program recommended HW settings

Reviewed-by: Clint Taylor -Clint On 11/2/21 3:25 PM, Matt Roper wrote: The bspec's performance guide suggests programming specific values into a few registers for optimal performance. Although these aren't workarounds, it's easiest to handle them inside the GT workaround functions (which

Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV

Appears to match latest BSPEC Reviewed-by: Clint Taylor -Clint On 9/3/21 5:35 PM, Matt Roper wrote: From: Lucas De Marchi Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to memory for L3 des

Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/adl_p: Disable PSR2

psr2(dev_priv, crtc_state->cpu_transcoder)) { drm_dbg_kms(_priv->drm, "PSR2 not supported in transcoder %s\n", Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gf

Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/adl_p: Allow DC3CO in pipe and port B

_A || - dig_port->base.port != PORT_A) + if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) return; /* Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel

ls = max_t(u8, 1, dev_priv->dram_info.num_channels); int deinterleave; int ipqdepth, ipqdepthpch; int dclk_max; Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.free

Re: [Intel-gfx] [PATCH 2/5] drm/i915/adl_p: Handle TC cold

ld(struct intel_digital_port *dig_port); void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy); +bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port); + #endif /* __INTEL_TC_H__ */ Reviewed-by: Clint Taylor -Clint _

Re: [Intel-gfx] [PATCH 1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia()

, wakeref); + mutex_unlock(_port->tc_lock); drm_WARN_ON(>drm, val == 0x); Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables

Values match current BSPEC. Reviewed-by: Clint Taylor -Clint On 5/14/21 8:10 PM, Matt Roper wrote: From: Mika Kahola Define and use DP voltage swing and pre-emphasis translation tables for ADL-P. v2: - Update according to recent bspec updates; there are now separate tables for RBR

Re: [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support

Reviewed-by: Clint Taylor -Clint On 5/14/21 8:10 PM, Matt Roper wrote: From: Anusha Srivatsa The clocks in ALD_P is similar to that of TGL. The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL. This patch adds the helper function intel_mg_pll_enable_reg() which is similar

Re: [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming

Reviewed-by: Clint Taylor -Clint On 5/14/21 8:10 PM, Matt Roper wrote: From: Anusha Srivatsa When scalers are enabled, we need to program underrun bubble counter to 0x50 to avoid Soft Pipe A underruns. Make sure other bits dont get overwritten. Cc: Matt Roper Cc: Clint Taylor Cc: José

Re: [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT

drm_dbg_kms(_priv->drm, + "plane %d pitch (%d) must be power of two for tiled buffers\n", + i, mode_cmd->pitches[i]); + goto err; + } + Reviewed-by: Clint Taylo

Re: [Intel-gfx] [PATCH v2] drm/i915/dg1: Update voltage swing tables for DP

t it would be consistent. Feel free to change the name or leave it. The code appears to match the current BSPEC table. Reviewed-by: Clint Taylor -Clint + /* NT mV Trans mV db*/ + { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 35

Re: [Intel-gfx] [PATCH] drm/i915/tgl, rkl, dg1: Apply WA_1406941453 to TGL, RKL and DG1

image quality */ wa_masked_en(wal, Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Dump skl+ watermark changes

Reviewed-by: Clint Taylor -Clint On 2/8/19 12:05, Ville Syrjala wrote: From: Ville Syrjälä Currently we're only dumping out the ddb allocation changes, let's do the same for the watermarks. This should help with debugging underruns and whatnot. First I tried one line per plane per wm

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence

Oops, failure caused by ICL_PORT_TX_DW7 not being defined yet. Still waiting on r-b for a patch that includes the DW7 definition. -Clint On 12/14/18 10:15, Patchwork wrote: == Series Details == Series: drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence URL :

Re: [Intel-gfx] [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC

On 12/03/2018 04:19 AM, Ville Syrjälä wrote: On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. BSpec: 21257 Cc: Ville

Re: [Intel-gfx] [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC

On 11/30/2018 03:15 PM, Imre Deak wrote: On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. BSpec: 21257 Cc: Ville Syrjälä

Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Fix PLL mapping sanitization for DP ports

since our MST HW readout is incomplete. +*/ + if (WARN_ON(is_mst)) + return; + } if (clk_enabled == !!encoder->base.crtc) return; Fixes the mDP lock up issue. Reviewed-by: Clint

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Remove CNL from WA 827

Gen9:all */ + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) return true; return false; Looks good. Reviewed-by: Clint Taylor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedes

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values

On 10/15/2018 04:31 AM, Jani Nikula wrote: On Mon, 15 Oct 2018, Jani Nikula wrote: On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote: From: Clint Taylor HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value mode instead of HDMI specification values. Signed-off

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Initialize SCDC registers according to spec

On 10/15/2018 06:41 AM, Ville Syrjälä wrote: On Fri, Oct 12, 2018 at 01:14:45PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor Initialize SCDC Source Version and TDMS_Config_0 registers to nominal values during intel_hdmi_detect(). The i915 driver currently doesn't implement

Re: [Intel-gfx] [PATCH] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

On 10/08/2018 03:33 AM, Ville Syrjälä wrote: On Fri, Oct 05, 2018 at 03:18:44PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SC

Re: [Intel-gfx] [PATCH v3] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

On 06/29/2018 02:09 AM, Imre Deak wrote: On Thu, Jun 28, 2018 at 11:14:30AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope

Re: [Intel-gfx] [PATCH V2] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

On 06/25/2018 03:33 AM, Imre Deak wrote: On Wed, Jun 13, 2018 at 02:48:49PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope

Re: [Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

On 06/08/2018 06:31 AM, Imre Deak wrote: Hi Clint, nice debugging! On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal

Re: [Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

tel.com (2018-04-12 00:13:26) From: Clint Taylor <clinton.a.tay...@intel.com> In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available."), the patch was always selecting the alternate refresh rate even though user space was asking for the higher rate

Re: [Intel-gfx] [PATCH] drm/i915/kbl: Add KBL GT2 sku

L_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ + INTEL_VGA_DEVICE(0x591C, info), /* Mobile GT2 */ \ KBL-R Y 2+2 should actually be labeled as ULX GT2 instead of Mobile GT2. Of course this information is conveniently missing from the spec. With that change: Reviewed-by: Clint Taylor &l

Re: [Intel-gfx] [PATCH] drm/i915: Fix LSPCON TMDS output buffer enabling from low-power state

irmware loaded. Customer was concerned about the fix being in DRM instead of i915. However, there are no other SOCs that use this DRM function. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> Tested-by: Clint Taylor <clinton.a.tay...@intel.com> -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix intel_edp_compare_alt_mode.

On 03/13/2018 06:11 AM, Ville Syrjälä wrote: On Tue, Mar 13, 2018 at 10:28:55AM +0100, Maarten Lankhorst wrote: On fi-cnl-y3 we have 2 modes that differ only by crtc_clock. This means that if we request the normal mode, we automatically get the downclocked mode. This can be seen during boot:

Re: [Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

On 04/11/2018 04:11 PM, Chris Wilson wrote: Quoting clinton.a.tay...@intel.com (2018-04-12 00:13:26) From: Clint Taylor <clinton.a.tay...@intel.com> In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available."), the patch was always selecting the a

Re: [Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

On 03/02/2018 10:10 AM, Rodrigo Vivi wrote: On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> DisplayPort Phy compliance test patterns register definitions. Hi Clint, what's the current plan to add the actu

Re: [Intel-gfx] [PATCH] drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts

On 08/16/2017 02:19 PM, Rodrigo Vivi wrote: It seems this quirk is randomly masking the real issue. It could be masking the real issue. The most likely cause of this issue is a slow power fall off to the panel when the PPS requests power-off. We would need physical access to the platform

Re: [Intel-gfx] [PATCH i-g-t] tools/intel_vbt_decode: Fix decoding of child device structure

This patch fixes the alignment. I spotted another issue with teh structure and will fix it once this one is merged. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> Tested-by: Clint Taylor <clinton.a.tay...@intel.com> On 08/16/2017 07:20 AM, ville.syrj...@linux.intel.com

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

On 08/14/2017 07:40 AM, Daniel Vetter wrote: On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read.

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

stedt, Marta <marta.lofst...@intel.com> Subject: [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read. Adjust the t

Re: [Intel-gfx] [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read

com>; Lofstedt, Marta <marta.lofst...@intel.com> Subject: [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID re

Re: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read

Of clinton.a.tay...@intel.com Sent: Friday, August 4, 2017 9:23 PM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read From: Clint Taylor <clinton.a.tay...@intel.com> Current 50ms max threshold timing for an EDID read is very

Re: [Intel-gfx] [PATCH] drm/i915/cnl: New DMC release: 1.05.

On 07/12/2017 04:47 PM, Rodrigo Vivi wrote: Version 1.05 is now available for CNL. According to its release notes the only difference is: - Change from aux A pwrreq always turn on during restore, to saving and restoring aux A pwrreq. Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 07/11/2017 07:10 AM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 07/09/2017 11:53 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to intel_framebuffer_init

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Add NV12 as supported format for primary plane

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Upscale scaler max scale for NV12

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) Needs rebase again. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Update format_is_yuv() to include NV12

On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to format_is_yuv() function and made it available for both primary and sprite planes small nit on the commit message: static function in intel_sprite.c is not available

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Set scaler mode for NV12

Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor -Clint On 06/19/2017 11:10 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode,

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.

for this information. Cc: Clint Taylor <clinton.a.tay...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_bios.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Cannonlake color init.

Reviewed-by: Clinton Taylor <clinton.a.tay...@intel.com> -Clint On 07/06/2017 02:01 PM, Rodrigo Vivi wrote: Cannonlake has same color setup as Geminilake. Legacy color load luts doesn't work anymore on Cannonlake+. Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Ander Conselvan

Re: [Intel-gfx] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for

Re: [Intel-gfx] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy

Re: [Intel-gfx] [PATCH i-g-t 3/5] lib/cnl: Add Cannonlake PCI IDs for Y-skus.

Matches i915 support PCI device IDs Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for

Re: [Intel-gfx] [PATCH i-g-t 2/5] lib/cnl: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:18 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also

Re: [Intel-gfx] [PATCH i-g-t] lib/cfl: Introduce Coffeelake platform definition.

Identical to other platforms. Reviewed-by: Clinton Taylor On 06/29/2017 10:18 AM, Rodrigo Vivi wrote: Coffeelake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. On following patches we

Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts

Looks Good. Reviewed-by: Clinton Taylor -Clint On 06/28/2017 05:14 PM, Manasi Navare wrote: This patch fixes the DP AUX CH timeouts observed during CI IGT tests thus fixing the CI failures. This is done by adding a quirk for a particular PCI device that requires

Re: [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 12 +++- 1 file changed, 11

Re: [Intel-gfx] [PATCH libdrm 2/3] intel: PCI Ids for H SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 8 +++- 1 file changed, 7

Re: [Intel-gfx] [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 17 - 1 file changed, 16

Re: [Intel-gfx] [RESEND i-g-t 3/3] lib/cfl: Add PCI Ids for U SKU in CFl

On 06/22/2017 09:28 AM, Anusha Srivatsa wrote: From: anushasr Follow the spec and add ID for U SKU v2: Update IDs in accordance to the kernel commit: d29fe702c9cb682df99146d24d06e5455f043101 (Chris) Cc: Rodrigo Vivi Signed-off-by: Anusha

Re: [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- intel/intel_chipset.h | 12 +++- 1 file changed, 11

Re: [Intel-gfx] [i-g-t 3/3] lib/cfl: Add PCI Ids for U SKU in CFl

On 06/21/2017 09:34 AM, Anusha Srivatsa wrote: From: anushasr Follow the spec and add ID for U SKU v2: Update IDs. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- lib/i915_pciids.h | 9 - 1 file

Re: [Intel-gfx] [i-g-t 1/3] lib/cfl: Add Coffeelake PCI IDs for S SKU.

EVICE(0x3E96, info) /* SRV GT2 */ + Matches current documentation Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_IDS(info) + #endif /* _I915_PCIIDS_H */ diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c index 199fa2d..

Re: [Intel-gfx] [i-g-t 2/3] lib/cfl: Add PCI IDs to H SKU in CFl

EVICE(0x3E96, info) /* SRV GT2 */ + +#define INTEL_CFL_H_IDS(info) \ + INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ + Device ID's Matches current documentation Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> #d

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Enable wrpll computation for CNL

Matches pseudo code in BSpec. Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com> On 06/08/2017 04:03 PM, Rodrigo Vivi wrote: From: "Kahola, Mika" <mika.kah...@intel.com> Enable wrpll computation for Cannonlake platform to support pll's required for HDMI outp

Re: [Intel-gfx] [PATCH] drm/i915/glk: RGB565 planes now allow 90/270 rotation

On 06/08/2017 04:45 AM, Szwichtenberg, Radoslaw wrote: On Wed, 2017-06-07 at 10:45 -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> RGB565 Pixel format planes can now be rotated at 90 and 270 degrees Signed-off-by: Clint Taylor <clin

Re: [Intel-gfx] [PATCH] drm/i915/glk: RGB565 planes now allow 90/270 rotation

On 06/07/2017 10:55 AM, Ville Syrjälä wrote: On Wed, Jun 07, 2017 at 10:45:25AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> RGB565 Pixel format planes can now be rotated at 90 and 270 degrees "now" == since when? GLK, I will u

Re: [Intel-gfx] [PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

On 04/06/2017 12:15 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also the new Spec style what makes the review much more easy and

Re: [Intel-gfx] [PATCH] drm/i915/dvo: fix debug logging on unknown DID

On 05/31/2017 03:16 AM, Jani Nikula wrote: Print DID not VID on the DID error path. Looks like a copy-paste error from the VID error path. Clarify and clean up error logging, making them distinguishable from each other, while at it. Reviewed-by: Clinton Taylor

Re: [Intel-gfx] [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

Reviewed-by: Clinton Taylor -Clint On 05/30/2017 03:42 PM, Rodrigo Vivi wrote: As for BXT, PP_DIVISOR was removed from CNP PCH and power cycle delay has been moved to PP_CONTROL. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi

Re: [Intel-gfx] [RFC PATCH 6/7] drm: add support for DisplayPort CEC-Tunneling-over-AUX

On 05/26/2017 12:18 AM, Daniel Vetter wrote: On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote: From: Hans Verkuil This adds support for the DisplayPort CEC-Tunneling-over-AUX feature that is part of the DisplayPort 1.3 standard. Unfortunately, not all

Re: [Intel-gfx] [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 02:29 PM, Hans Verkuil wrote: On 05/30/2017 10:32 PM, Clint Taylor wrote: On 05/30/2017 09:54 AM, Hans Verkuil wrote: On 05/30/2017 06:49 PM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017

Re: [Intel-gfx] [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 09:54 AM, Hans Verkuil wrote: On 05/30/2017 06:49 PM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote: On 05/29/2017 09:00 PM, Daniel Vetter

Re: [Intel-gfx] [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 09:49 AM, Hans Verkuil wrote: On 05/30/2017 04:19 PM, Clint Taylor wrote: On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote: On 05/29/2017 09:00 PM, Daniel Vetter wrote: On Fri, May 26, 2017 at 12:20:48PM +0200

Re: [Intel-gfx] [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

On 05/29/2017 04:06 AM, Jani Nikula wrote: On Thu, 18 May 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: On 05/18/2017 04:10 AM, Jani Nikula wrote: Face the fact, there are Display Port sink and branch devices out there in the wild that don't follow the Display Port specific

Re: [Intel-gfx] [RFC PATCH 7/7] drm/i915: add DisplayPort CEC-Tunneling-over-AUX support

On 05/30/2017 12:11 AM, Jani Nikula wrote: On Tue, 30 May 2017, Hans Verkuil wrote: On 05/29/2017 09:00 PM, Daniel Vetter wrote: On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote: On 05/26/2017 09:15 AM, Daniel Vetter wrote: Did you look into also wiring

Re: [Intel-gfx] [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

ille Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Adam Jackson <a...@redhat.com> Cc: Harry Wentland <harry.wentl...@amd.com> Signed-off-by: Jani Nikula <jani.nik...@int

Re: [Intel-gfx] [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database

devices ended up in regressions for other devices. So here we are. v2: Rebase on DRM DP desc read helpers Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay...@intel.com> Cc: Adam Jackson &l

Re: [Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 03:03 AM, Jani Nikula wrote: On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The Analogix 7737 DP to HDMI converter requires reduced N and M values when to operate correctly at HBR2. Detect this IC by its OUI

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 02:57 AM, Jani Nikula wrote: From: Clint Taylor <clinton.a.tay...@intel.com> The Analogix 7737 DP to HDMI converter requires reduced M and N values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9 via the DPCD quirk list. v2 by Jani: R

Re: [Intel-gfx] [PATCH 1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

properly. Naturally, the workaround of reducing main link attributes for all devices ended up in regressions for other devices. So here we are. Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Clint Taylor <clinton.a.tay..

Re: [Intel-gfx] [PATCH] drm/i915/dp: reduce link M/N parameters

a: https://bugs.freedesktop.org/show_bug.cgi?id=93578 Tested-by: Mads <m...@ab3.no> Tested-by: PJ <foo...@pjmodos.net> Tested-by: François Guerraz <kubr...@fgv6.net> Tested-by: Lev Popov <l...@nabam.net> Tested-by: Igor Krivenko <igor.s.krive...@gmail.com> Cc: Clint Taylor &

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/24/2017 04:25 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: I would prefer a solution for B (rules for M/N), but the code doesn't appear to be broken and I don't believe we should "Fix" something that is working. The d

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/23/2017 10:23 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote: On 03/23/2017 05:30 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Several major vendor

Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

On 03/23/2017 05:30 AM, Jani Nikula wrote: On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor <clinton.a.tay...@intel.com> Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane signal if the Data Link N is greater than 0x8. Patch detec

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