Re: [Intel-gfx] [PATCH] drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission

2019-11-15 Thread Daniele Ceraolo Spurio
On 11/15/2019 2:22 PM, Hiatt, Don wrote: From: Ceraolo Spurio, Daniele Sent: Friday, November 15, 2019 2:02 PM To: Hiatt, Don ; intel-gfx@lists.freedesktop.org Cc: Ewins, Jon ; KiteStramuort ; S . Zharkoff ; Wajdeczko, Michal ; Summers, Stuart ; Chris Wilson ; Tomas Janousek Subject: Re:

Re: [Intel-gfx] [PATCH] drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission

2019-11-15 Thread Daniele Ceraolo Spurio
On 11/15/19 10:20 AM, don.hi...@intel.com wrote: From: Don Hiatt On some platforms (e.g. KBL) that do not support GuC submission, but the user enabled the GuC communication (e.g for HuC authentication) calling the GuC EXIT_S_STATE action results in lose of ability to enter RC6. We can remove

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC method to determine if submission is active.

2019-11-06 Thread Daniele Ceraolo Spurio
On 11/6/19 9:40 AM, don.hi...@intel.com wrote: From: Don Hiatt Add intel_guc_submission_is_enabled() function to determine if GuC submission is active. Based on code by Michal Wajdeczko. Signed-off-by: Don Hiatt --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-

[Intel-gfx] [PATCH 4/4] drm/i915/guc: kill the GuC client

2019-11-06 Thread Daniele Ceraolo Spurio
We now only use 1 client without any plan to add more. The client is also only holding information about the WQ and the process desc, so we can just move those in the intel_guc structure and always use stage_id 0. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc

[Intel-gfx] [PATCH 2/4] drm/i915/guc: add a helper to allocate and map guc vma

2019-11-06 Thread Daniele Ceraolo Spurio
We already have a couple of use-cases in the code and another one will come in one of the later patches in the series. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 34

[Intel-gfx] [PATCH 1/4] drm/i915/guc: Drop leftover preemption code

2019-11-06 Thread Daniele Ceraolo Spurio
Remove unused enums and ctx_save_restore_disabled() function, leftover from the legacy preemption removal. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 --- 1 file changed

[Intel-gfx] [PATCH 3/4] drm/i915/guc: kill doorbell code and selftests

2019-11-06 Thread Daniele Ceraolo Spurio
come with the new code, but they will look different from what we have now so if doesn't seem worth it to keep the file around in the meantime. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8

[Intel-gfx] [PATCH 0/4] Start removing legacy guc code

2019-11-06 Thread Daniele Ceraolo Spurio
to GuC while the latter won't make sense in the new flow as the proxy submission mechanism is gone. Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Daniele Ceraolo Spurio (4): drm/i915/guc: Drop leftover preemption code drm/i915/guc: add a helper to allocate and map guc vma drm

[Intel-gfx] PR - i915 firmware updates (GuC and HuC for EHL and TGL)

2019-11-06 Thread Daniele Ceraolo Spurio
-firmware ehl_tgl_guc_huc for you to fetch changes up to 4debf2173804396540d1890fa2347af7689c4420: i915: Add HuC firmware v7.0.3 for TGL (2019-11-06 11:42:42 -0800) Daniele Ceraolo Spurio (4): i915: Add GuC firmware v33.0.4 for EHL

[Intel-gfx] [PATCH v2] drm/i915/guc: Properly capture & release GuC interrupts on Gen11+

2019-11-05 Thread Daniele Ceraolo Spurio
it. v2 (Daniele): replace the gen9 paths instead of keeping gen9 and gen11 functions since we won't support guc submission on any pre-gen11 platform. Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio Cc: John Harrison Cc: Matthew Brost

[Intel-gfx] [PATCH 1/2] drm/i915: drop lrc header page

2019-10-30 Thread Daniele Ceraolo Spurio
Recent GuC binaries (including all the ones we're currently using) don't require this shared area anymore, having moved the relevant entries into the stage pool instead. i915 itself doesn't write anything into it either, so we can safely drop it. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris

[Intel-gfx] [PATCH 2/2] drm/i915/guc: drop guc shared area

2019-10-30 Thread Daniele Ceraolo Spurio
implement it as part of the new flow. [1] https://patchwork.freedesktop.org/patch/295038/ Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Cc: Fernando Pacheco --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 50 ++ drivers/gpu/drm

Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: define GuC and HuC binaries for TGL

2019-10-30 Thread Daniele Ceraolo Spurio
On 10/26/19 3:44 AM, Michal Wajdeczko wrote: On Sat, 26 Oct 2019 02:35:06 +0200, Daniele Ceraolo Spurio wrote: GuC 35.2.0 and HuC 7.0.3 are the first production releases for TGL. GuC 35.2 for gen12 is interface-compatible with 33.0 on older gens, because the differences are related

Re: [Intel-gfx] [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture

2019-10-29 Thread Daniele Ceraolo Spurio
On 10/29/19 2:51 PM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-10-29 21:46:46) On 10/29/19 2:58 AM, Matthew Auld wrote: Since we have no way access it from the CPU. For such cases just fallback to internal objects. Since the problem is not limited to rings but it applies

Re: [Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture

2019-10-29 Thread Daniele Ceraolo Spurio
On 10/29/19 2:44 PM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16) On 10/29/19 2:58 AM, Matthew Auld wrote: From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Signed-off

Re: [Intel-gfx] [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture

2019-10-29 Thread Daniele Ceraolo Spurio
On 10/29/19 2:58 AM, Matthew Auld wrote: Since we have no way access it from the CPU. For such cases just fallback to internal objects. Since the problem is not limited to rings but it applies to all stolen objects, wouldn't it be better to just skip the stolen initialization or return an

Re: [Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture

2019-10-29 Thread Daniele Ceraolo Spurio
On 10/29/19 2:58 AM, Matthew Auld wrote: From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4

Re: [Intel-gfx] [RFC 1/2] drm/i915: add display uncore helpers

2019-10-29 Thread Daniele Ceraolo Spurio
/ with these, to finally be able to get rid of the implicit dev_priv local parameter use. The idea is that any non-u32 reads or writes are special enough that they can use the intel_uncore_* functions directly. Cc: Chris Wilson Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Lucas De Marchi Cc: Rodrigo

Re: [Intel-gfx] [RFC 0/3] Display uncore

2019-10-29 Thread Daniele Ceraolo Spurio
On 10/29/19 2:23 AM, Jani Nikula wrote: On Wed, 07 Aug 2019, Daniele Ceraolo Spurio wrote: I've been trying to identify MMIO ranges to clearly define what belongs to display_uncore to do a check on access, but there are lots of exceptions and differences across gens (with a few more coming

Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled

2019-10-28 Thread Daniele Ceraolo Spurio
On 10/28/19 11:17 AM, Hiatt, Don wrote: From: Ceraolo Spurio, Daniele Sent: Monday, October 28, 2019 9:44 AM To: Hiatt, Don ; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled On 10/24/19 9:29 AM,

Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled

2019-10-28 Thread Daniele Ceraolo Spurio
On 10/24/19 9:29 AM, don.hi...@intel.com wrote: From: Don Hiatt Check to see if GuC submission is enabled before requesting the EXIT_S_STATE action. You're only skipping the resume, but does it make any sense to do the suspend action if we're not going to call the resume one? Does guc do

[Intel-gfx] [PATCH 2/2] HAX: force enable_guc=2

2019-10-25 Thread Daniele Ceraolo Spurio
From: Anusha Srivatsa Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 56058978bb27..99d5ed597495 100644 ---

[Intel-gfx] [PATCH 1/2] drm/i915/uc: define GuC and HuC binaries for TGL

2019-10-25 Thread Daniele Ceraolo Spurio
the relevant features are enabled. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc

[Intel-gfx] [CI] PR for TGL GuC/HuC binaries

2019-10-25 Thread Daniele Ceraolo Spurio
up to 090625847b8e2f255bbd4e0aa1641983a570ac76: i915: Add HuC firmware v7.0.3 for TGL (2019-10-25 16:54:38 -0700) Daniele Ceraolo Spurio (4): i915: Add GuC firmware v33.0.4 for EHL i915: Add HuC firmware v9.0.0 for EHL

Re: [Intel-gfx] [PATCH 3/4] drm/i915: do not set MOCS control values on dgfx

2019-10-25 Thread Daniele Ceraolo Spurio
On 10/24/19 12:51 PM, Lucas De Marchi wrote: On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc log relay write

2019-10-23 Thread Daniele Ceraolo Spurio
On 10/23/19 8:14 AM, Patchwork wrote: == Series Details == Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc log relay write URL : https://patchwork.freedesktop.org/series/68406/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155_full ->

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Move uncore fw selftests to operate on intel_gt

2019-10-22 Thread Daniele Ceraolo Spurio
version that uses a separate lock and skips forcewake. Reviewed-by: Daniele Ceraolo Spurio Daniele On the particular patch only comment is that I would consider one or two i915 locals for better readability. Regards, Tvrtko Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Daniele

Re: [Intel-gfx] [PATCH] drm/i915: Do not end i915 batch buffers prematurely

2019-10-17 Thread Daniele Ceraolo Spurio
On 10/17/19 12:37 PM, Stuart Summers wrote: During engine initialization in i915 load, the batch buffers being used to set up the initial context are being prematurely ended. In most scenarios, this does not cause a problem, but That's not a batch that we add the BBEND to, that's the context

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915: Add microcontrollers documentation section

2019-10-17 Thread Daniele Ceraolo Spurio
On 10/14/19 3:04 PM, Patchwork wrote: == Series Details == Series: series starting with [v3,1/3] drm/i915: Add microcontrollers documentation section URL : https://patchwork.freedesktop.org/series/67986/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7090 ->

[Intel-gfx] [PATCH v3 3/3] drm/i915/huc: improve documentation

2019-10-14 Thread Daniele Ceraolo Spurio
for better text organization (Martin) Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Martin Peres Acked-by: Anna Karas Reviewed-by: Martin Peres --- Documentation/gpu/i915.rst| 16 +-- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 35

[Intel-gfx] [PATCH v3 1/3] drm/i915: Add microcontrollers documentation section

2019-10-14 Thread Daniele Ceraolo Spurio
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Acked-by: Anna Karas Reviewed-by: Martin Peres --- Documentation/gpu/i915.rst | 18

[Intel-gfx] [PATCH v3 2/3] drm/i915/guc: improve documentation

2019-10-14 Thread Daniele Ceraolo Spurio
(Martin) Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Matthew Brost Cc: Martin Peres Acked-by: Anna Karas Reviewed-by: Martin Peres --- Documentation/gpu/i915.rst| 22 - drivers/gpu/drm/i915/gt/uc/intel_guc.c| 31

[Intel-gfx] [PATCH v2 1/3] drm/i915: Add microcontrollers documentation section

2019-10-09 Thread Daniele Ceraolo Spurio
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Acked-by: Anna Karas Reviewed-by: Martin Peres --- Documentation/gpu/i915.rst | 18

[Intel-gfx] [PATCH v2 2/3] drm/i915/guc: improve documentation

2019-10-09 Thread Daniele Ceraolo Spurio
Add a short description of what we expect from GuC and some minor improvements to existing documentation. Also remove a comment about a difference between GuC and HuC that is not true anymore. v2: add that the GuC is not mandatory (Martin) Signed-off-by: Daniele Ceraolo Spurio Cc: Michal

[Intel-gfx] [PATCH v2 3/3] drm/i915/huc: improve documentation

2019-10-09 Thread Daniele Ceraolo Spurio
Ceraolo Spurio Cc: Michal Wajdeczko Cc: Martin Peres Acked-by: Anna Karas --- Documentation/gpu/i915.rst| 16 +-- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 33 --- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 --- 3 files changed, 43 insertions

Re: [Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation

2019-10-09 Thread Daniele Ceraolo Spurio
On 10/9/19 2:44 PM, Daniele Ceraolo Spurio wrote: On 10/9/19 7:41 AM, Martin Peres wrote: On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote: Better explain the usage of the microcontroller and what i915 is responsible of. While at it, fix the documentation for the auth function, which

[Intel-gfx] [PATCH 1/2] drm/i915/tgl: the BCS engine supports relative MMIO

2019-10-09 Thread Daniele Ceraolo Spurio
The specs don't mention any specific HW limitation on the blitter and manual inspection shows that the HW does set the relative MMIO bit in the LRI of the blitter context image, so we can remove our limitations. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: John Harrison Cc: Mika

[Intel-gfx] [PATCH 2/2] drm/i915/tgl: simplify the lrc register list for !RCS

2019-10-09 Thread Daniele Ceraolo Spurio
engine within the class for virtual engine because the HW can handle that, instead of having a separate define for the BCS we can just restrict the programming to the part we're interested in, which is common across the engines. Bspec: 45584 Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc

Re: [Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation

2019-10-09 Thread Daniele Ceraolo Spurio
On 10/9/19 7:41 AM, Martin Peres wrote: On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote: Better explain the usage of the microcontroller and what i915 is responsible of. While at it, fix the documentation for the auth function, which doesn't do any pinning anymore. Signed-off-by: Daniele

[Intel-gfx] [PATCH 1/3] drm/i915: Add microcontrollers documentation section

2019-09-27 Thread Daniele Ceraolo Spurio
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko --- Documentation/gpu/i915.rst | 18 ++ 1 file changed, 18 insertions

[Intel-gfx] [PATCH 2/3] drm/i915/guc: improve documentation

2019-09-27 Thread Daniele Ceraolo Spurio
Add a short description of what we expect from GuC and some minor improvements to existing documentation. Also remove a comment about a difference between GuC and HuC that is not true anymore. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Matthew Brost --- Documentation/gpu

[Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation

2019-09-27 Thread Daniele Ceraolo Spurio
Better explain the usage of the microcontroller and what i915 is responsible of. While at it, fix the documentation for the auth function, which doesn't do any pinning anymore. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko --- Documentation/gpu/i915.rst| 10

Re: [Intel-gfx] [PATCH] drm/i915/guc: Update H2G enable logging action definition

2019-09-27 Thread Daniele Ceraolo Spurio
On 9/27/19 11:04 AM, Robert M. Fosha wrote: GuC enable logging H2G action definition changed some time ago from 0xE000 to 0x40. All current GuC FW blobs use this definition, so fix the action definition in driver to match. Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)

2019-09-27 Thread Daniele Ceraolo Spurio
And pushed. Daniele On 9/26/19 8:30 AM, Patchwork wrote: == Series Details == Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2) URL : https://patchwork.freedesktop.org/series/66560/ State : success == Summary == CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full

Re: [Intel-gfx] [PATCH] drm/i915/huc: fix version parsing from CSS header

2019-09-27 Thread Daniele Ceraolo Spurio
On 9/26/19 12:37 AM, Michal Wajdeczko wrote: On Thu, 26 Sep 2019 01:03:20 +0200, Summers, Stuart wrote: On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote: The HuC FW has silently switched to encoding the version the same way as the GuC FW does, i.e. major.minor.patch instead

[Intel-gfx] [PATCH] drm/i915/huc: fix version parsing from CSS header

2019-09-25 Thread Daniele Ceraolo Spurio
binaries, however, will have non-zero values in there, so we need to make sure to parse them correctly. Signed-off-by: Daniele Ceraolo Spurio Cc: Anusha Srivatsa Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 23 drivers/gpu/drm/i915/gt/uc

[Intel-gfx] [CI] drm/i915/dmc: Update ICL DMC version to v1.09

2019-09-25 Thread Daniele Ceraolo Spurio
From: Anusha Srivatsa We have a new version of DMC for ICL - v1.09. This version adds the Half Refresh Rate capability into DMC. Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Reviewed-by: José Roberto de Souza Signed-off-by: Daniele Ceraolo Spurio Link: https

Re: [Intel-gfx] [PATCH 20/27] drm/i915: Remove logical HW ID

2019-09-25 Thread Daniele Ceraolo Spurio
from request alloc (ctx hw id %u, on %s): %d\n", -   ctx->hw_id, engine->name, +    pr_err("Unexpected error from request alloc (on %s): %d\n", +   engine->name,              (int)PTR_

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

2019-09-20 Thread Daniele Ceraolo Spurio
On 9/20/19 5:51 AM, Patchwork wrote: == Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66955/ State : failure == Summary == CI Bug Log - changes from

Re: [Intel-gfx] [PATCH] drm/i915: disable set/get_tiling ioctl on gen12+

2019-09-19 Thread Daniele Ceraolo Spurio
On 8/21/19 8:20 AM, Daniel Vetter wrote: On Wed, Aug 21, 2019 at 3:55 PM Ville Syrjälä wrote: On Tue, Aug 20, 2019 at 01:57:44PM -0700, Daniele Ceraolo Spurio wrote: On 8/20/19 12:54 PM, Daniel Vetter wrote: The cpu (de)tiler hw is gone, this stopped being useful. Plus it never

[Intel-gfx] [CI 2/2] HAX: force enable_guc=2

2019-09-19 Thread Daniele Ceraolo Spurio
From: Anusha Srivatsa Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..f9fbb1f2fabf 100644 ---

[Intel-gfx] [CI 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

2019-09-19 Thread Daniele Ceraolo Spurio
e changes in huc_def (Daniele) Suggested-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Anusha Srivatsa Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

2019-09-19 Thread Daniele Ceraolo Spurio
On 9/14/19 4:06 PM, Patchwork wrote: == Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66685/ State : failure == Summary == CI Bug Log - changes from

[Intel-gfx] [PATCH v2] drm/i915: fix SFC reset flow

2019-09-18 Thread Daniele Ceraolo Spurio
failure (Chris), improve comments (Tvrtko). Reported-by: Owen Zhang Signed-off-by: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Cc: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_reset.c | 51 +-- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers

Re: [Intel-gfx] [PATCH] drm/i915: Allow set context SSEU on platforms after gen 11

2019-09-18 Thread Daniele Ceraolo Spurio
On 9/18/19 10:31 AM, Stuart Summers wrote: Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559 What's the planned usage here? TGL HW only supports slice-level power-gating and with only 1 slice on TGL we don't really have a choice of what to program, do we? Daniele Cc:

Re: [Intel-gfx] [PATCH] drm/i915: fix SFC reset flow

2019-09-17 Thread Daniele Ceraolo Spurio
On 9/17/2019 12:49 PM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-17 20:45:02) On 9/17/2019 11:57 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-17 19:36:35) On 9/17/2019 12:57 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-16 22:41:04

Re: [Intel-gfx] [PATCH] drm/i915: fix SFC reset flow

2019-09-17 Thread Daniele Ceraolo Spurio
On 9/17/2019 11:57 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-17 19:36:35) On 9/17/2019 12:57 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-16 22:41:04) Our assumption that the we can ask the HW to lock the SFC even if not currently in use does

Re: [Intel-gfx] [PATCH] drm/i915: fix SFC reset flow

2019-09-17 Thread Daniele Ceraolo Spurio
On 9/17/2019 12:57 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-16 22:41:04) Our assumption that the we can ask the HW to lock the SFC even if not currently in use does not match the HW commitment. The expectation from the HW is that SW will not try to lock the SFC

Re: [Intel-gfx] [PATCH] drm/i915: fix SFC reset flow

2019-09-17 Thread Daniele Ceraolo Spurio
On 9/17/2019 3:22 AM, Tvrtko Ursulin wrote: On 16/09/2019 22:41, Daniele Ceraolo Spurio wrote: Our assumption that the we can ask the HW to lock the SFC even if not currently in use does not match the HW commitment. The expectation from the HW is that SW will not try to lock the SFC

[Intel-gfx] [PATCH] drm/i915: fix SFC reset flow

2019-09-16 Thread Daniele Ceraolo Spurio
the ack and ignoring our lock request, but this is not guaranteed and we shouldn't expect it going forward. Reported-by: Owen Zhang Signed-off-by: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_reset.c | 25 + 1 file changed, 17 insertions

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

2019-09-16 Thread Daniele Ceraolo Spurio
On 9/16/19 1:54 PM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-16 21:37:26) On 9/14/19 1:25 AM, Chris Wilson wrote: Before we execute a batch, we must first issue any and all TLB invalidations so that batch picks up the new page table entries. Tigerlake's preparser

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

2019-09-16 Thread Daniele Ceraolo Spurio
of the batch buffer before we have setup its page table (and so it loads the wrong page and executes indefinitely). Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio Cc: Mika Kuoppala --- Suggestions welcome as this does not seem intended behaviour, so I suspect there is a strong pipecontrol flag

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Introduce gen12 forcewake ranges

2019-09-13 Thread Daniele Ceraolo Spurio
with ranges from bspec. v4: avoid GEN11_NEEDS_FORCEWAKE (Mika) v5: bspec ref (Daniele) BSpec: 52078 Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 75 ++- drivers/gpu

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Update Gen11 forcewake ranges

2019-09-13 Thread Daniele Ceraolo Spurio
On 9/13/19 7:16 AM, Mika Kuoppala wrote: Daniele noticed new render ranges in Gen11 fw table. Bspec: 18331 Cc: Daniele Ceraolo Spurio Signed-off-by: Mika Kuoppala Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/intel_uncore.c | 23 +-- 1

Re: [Intel-gfx] [RFC] drm/i915/guc: Enable guc logging on guc log relay write

2019-09-12 Thread Daniele Ceraolo Spurio
On 9/11/19 2:28 PM, Fosha, Robert M wrote: On 9/10/19 5:48 PM, Daniele Ceraolo Spurio wrote: On 9/10/19 3:46 PM, Robert M. Fosha wrote: Creating and opening the GuC log relay file enables and starts the relay potentially before the caller is ready to consume logs. Change the behavior so

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Disable preemption while being debugged

2019-09-12 Thread Daniele Ceraolo Spurio
On 9/12/19 6:23 AM, Chris Wilson wrote: We see failures where the context continues executing past a preemption event, eventually leading to situations where a request has executed before we have event submitted it to HW! It seems like tgl is AFAIK on TGL the CS can detect tail updates in

Re: [Intel-gfx] [PATCH 1/4] drm/i915/tgl: Introduce gen12 forcewake ranges

2019-09-12 Thread Daniele Ceraolo Spurio
with the display uncore split (if I manage to find time to get back to it). BSpec: 18331. This should be 52078 for TGL. Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 75

Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: Update GuC and HuC firmware naming convention

2019-09-11 Thread Daniele Ceraolo Spurio
You're not touching GuC at all in this patch, so the subject is incorrect. You should also mention in the subject that you're updating the required FW version. with the title fixed: Reviewed-by: Daniele Ceraolo Spurio Daniele On 9/10/19 3:42 PM, Anusha Srivatsa wrote: Make both GuC and HuC

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement Wa_1409142259

2019-09-11 Thread Daniele Ceraolo Spurio
On 9/9/19 4:14 PM, Radhakrishna Sripada wrote: Disable CPS aware color pipe by setting chicken bit. BSpec: 52890 HSDES: 1409142259 v2: Move WA to ctx WA's(Daniele) Cc: Daniele Ceraolo Spurio Cc: Stuart Summers Cc: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Daniele

Re: [Intel-gfx] [RFC] drm/i915/guc: Enable guc logging on guc log relay write

2019-09-10 Thread Daniele Ceraolo Spurio
values flush the log relay as before. Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Robert M. Fosha --- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 38 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 2 ++ drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

2019-09-10 Thread Daniele Ceraolo Spurio
e platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL v4.0.0 ICL - v9.0.0 CML - v4.0.0 v2: Remove the separator parameter altogether from __MAKE_UC_FW_PATH.(Daniele) - Squash all firmware update patches (Daniele) Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivats

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Only unwedge if we can reset first

2019-09-10 Thread Daniele Ceraolo Spurio
On 9/9/19 11:06 PM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-10 01:59:38) On 9/9/19 3:55 PM, Chris Wilson wrote: Unwedging the GPU requires a successful GPU reset before we restore the default submission, or else we may see residual context switch events that we were

Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

2019-09-10 Thread Daniele Ceraolo Spurio
e versions of huc being loaded of the platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL v4.0.0 ICL - v9.0.0 CML - v4.0.0 v2: Remove the separator parameter altogether from __MAKE_UC_FW_PATH.(Daniele) - Squash all firmware update patches (Daniele) Suggested-by: Daniele Ceraolo Spurio

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Only unwedge if we can reset first

2019-09-09 Thread Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_reset.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index fe57296b790c..5242496a893a 100644 --- a/drivers/gpu/drm/i915/gt

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-09 Thread Daniele Ceraolo Spurio
On 9/6/19 6:10 PM, Matt Roper wrote: On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote: On 9/6/19 3:41 PM, Radhakrishna Sripada wrote: Disable CPS aware color pipe by setting chicken bit. BSpec: 52890 HSDES: 1409142259 Cc: Stuart Summers Cc: Matt Roper Signed-off

Re: [Intel-gfx] [PATCH] drm/i915: Don't unwedge if reset is disabled

2019-09-09 Thread Daniele Ceraolo Spurio
On 9/7/19 1:39 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05) On 9/5/19 2:09 AM, Janusz Krzysztofik wrote: When trying to reset a device with reset capability disabled or not supported while rings are full of requests, it has been observed when running

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-06 Thread Daniele Ceraolo Spurio
On 9/6/19 3:41 PM, Radhakrishna Sripada wrote: Disable CPS aware color pipe by setting chicken bit. BSpec: 52890 HSDES: 1409142259 Cc: Stuart Summers Cc: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +

Re: [Intel-gfx] [PATCH] drm/i915: Don't unwedge if reset is disabled

2019-09-06 Thread Daniele Ceraolo Spurio
edge already happened. Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Janusz Krzysztofik --- drivers/gpu/drm/i915/gt/intel_reset.c | 26 ++ 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 1/9] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

2019-09-06 Thread Daniele Ceraolo Spurio
On 9/6/19 12:47 PM, Anusha Srivatsa wrote: Update MAKE_HUC_FW_PATH macro to follow the same convention as the MAKE_GUC_FW_PATH with the separator changing from "_" to "." and removing "ver". The current convention being: _uc_..patch.bin Suggested-by: Dani

Re: [Intel-gfx] [PATCH 0/9] HuC updates

2019-09-06 Thread Daniele Ceraolo Spurio
On 9/6/19 12:47 PM, Anusha Srivatsa wrote: Updating HuC versions for gen9 and ICL platforms. Also updating MAKE_HUC_FW_PATH. The whole series needs to be squashed in a single patch, otherwise it won't work in the middle. Also, need to add a renamed EHL blob in the FW repo as well. I'm

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12

2019-09-06 Thread Daniele Ceraolo Spurio
from the previous gens, while keeping the registers that are contiguous in functions we can reuse. v2: alias, virtual engine, rpcs, prune unused regs v3: use engine base (Daniele), take ctx_bb for all Bspec: 46255 Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 1/8] drm/i915/firmware: Load v2.0.0 HuC for SKL

2019-09-05 Thread Daniele Ceraolo Spurio
be required for that. Daniele On 9/5/19 11:39 AM, Anusha Srivatsa wrote: Add support to load the latest version of HuC on SKL. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Register state context definition for Gen12

2019-09-05 Thread Daniele Ceraolo Spurio
On 9/5/19 9:13 AM, Daniele Ceraolo Spurio wrote: On 9/5/2019 4:34 AM, Mika Kuoppala wrote: From: Michel Thierry Gen12 has subtle changes in the reg state context offsets (some fields are gone, some are in a different location), compared to previous Gens. The simplest approach seems

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Register state context definition for Gen12

2019-09-05 Thread Daniele Ceraolo Spurio
from the previous gens, while keeping the registers that are contiguous in functions we can reuse. v2: alias, virtual engine, rpcs, prune unused regs (Mika) Bspec: 46255 Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Joonas Lahtinen Signed-off-by: Michel Thierry Signed

Re: [Intel-gfx] [PATCH v3 0/7] Tiger Lake batch 3.5

2019-08-29 Thread Daniele Ceraolo Spurio
On 8/29/19 2:25 AM, Lucas De Marchi wrote: Mostly the same patches as revision 5 of https://patchwork.freedesktop.org/series/65290/ with some dropped and some trivial ones added. Implementation for the first patches changed though, in order to address the review comments. Intention here is to

Re: [Intel-gfx] [PATCH 1/3] drm/i915/uc: Extract common code from GuC stop/disable comm

2019-08-28 Thread Daniele Ceraolo Spurio
, Daniele Ceraolo Spurio wrote: On 8/27/19 5:45 PM, Fernando Pacheco wrote: During normal driver unload we attempt to disable GuC communication while it is currently stopped. This results in a nop'd call to intel_guc_ct_disable within guc_disable_communication because stop/disable rely on the same

Re: [Intel-gfx] [PATCH 1/3] drm/i915/uc: Extract common code from GuC stop/disable comm

2019-08-28 Thread Daniele Ceraolo Spurio
co Cc: Chris Wilson Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 30 --- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index

[Intel-gfx] [PATCH v2] drm/i915: use a separate context for gpu relocs

2019-08-27 Thread Daniele Ceraolo Spurio
the CS also checks the LRCA when deciding if it can lite-restore. v2: limit new context to gen12+, release in eb_destroy, add a comment in emit_fini_breadcrumb (Chris). Suggested-by: Chris Wilson Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson --- .../gpu/drm/i915/gem

Re: [Intel-gfx] [PATCH] drm/i915: use a separate context for gpu relocs

2019-08-26 Thread Daniele Ceraolo Spurio
On 8/26/19 11:10 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-08-26 18:56:53) On 8/24/2019 1:54 AM, Chris Wilson wrote: Note that this requires us to fix the tagging so that we don't perform a lite-restore from the reloc instance to the user instance. What's wrong

Re: [Intel-gfx] [PATCH] drm/i915: use a separate context for gpu relocs

2019-08-26 Thread Daniele Ceraolo Spurio
On 8/24/2019 1:54 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-08-24 01:20:22) The CS pre-parser can pre-fetch commands across memory sync points and starting from gen12 it is able to pre-fetch across BB_START and BB_END boundaries as well, so when we emit gpu relocs the pre

[Intel-gfx] [PATCH] drm/i915: use a separate context for gpu relocs

2019-08-23 Thread Daniele Ceraolo Spurio
pre-fetch across the ctx switch, so we use a separate context to guarantee that the memory is syncronized before the parser can get to it. Suggested-by: Chris Wilson Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 27

Re: [Intel-gfx] [PATCH] drm/i915/uc: define GuC and HuC FWs for EHL

2019-08-23 Thread Daniele Ceraolo Spurio
Thanks for the reviews and the testing, pushed. Daniele On 8/19/19 6:23 PM, Daniele Ceraolo Spurio wrote: First uc firmware release for EHL. Signed-off-by: Daniele Ceraolo Spurio Cc: Matt Roper Cc: Anusha Srivatsa Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 13

[Intel-gfx] [CI] PR for EHL GuC/HuC binaries

2019-08-23 Thread Daniele Ceraolo Spurio
ehl_firmwares for you to fetch changes up to b115fab46c782d47783a7ecb5fc4b182129caebf: i915: Add HuC firmware v9.0.0 for EHL (2019-08-19 17:26:06 -0700) Daniele Ceraolo Spurio (2): i915: Add GuC firmware v33.0.4 for EHL

Re: [Intel-gfx] [RFC] drm/i915/tgl: Advanced preparser support for GPU relocs

2019-08-23 Thread Daniele Ceraolo Spurio
On 8/23/19 9:31 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-08-23 16:56:54) On 8/23/19 8:52 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-08-23 16:39:14) On 8/23/19 8:28 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-23 16:10:48) Quoting Daniele

Re: [Intel-gfx] [RFC] drm/i915/tgl: Advanced preparser support for GPU relocs

2019-08-23 Thread Daniele Ceraolo Spurio
On 8/23/19 8:52 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-08-23 16:39:14) On 8/23/19 8:28 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-23 16:10:48) Quoting Daniele Ceraolo Spurio (2019-08-23 16:05:45) On 8/23/19 7:26 AM, Chris Wilson wrote: Quoting Chris

Re: [Intel-gfx] [RFC] drm/i915/tgl: Advanced preparser support for GPU relocs

2019-08-23 Thread Daniele Ceraolo Spurio
On 8/23/19 8:28 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-23 16:10:48) Quoting Daniele Ceraolo Spurio (2019-08-23 16:05:45) On 8/23/19 7:26 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-23 08:27:25) Quoting Daniele Ceraolo Spurio (2019-08-23 03:09:09) TGL has

Re: [Intel-gfx] [RFC] drm/i915/tgl: Advanced preparser support for GPU relocs

2019-08-23 Thread Daniele Ceraolo Spurio
On 8/23/19 7:26 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-23 08:27:25) Quoting Daniele Ceraolo Spurio (2019-08-23 03:09:09) TGL has an improved CS pre-parser that can now pre-fetch commands across batch boundaries. This improves performances when lots of small batches are used

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Introduce intel_reg_types.h

2019-08-23 Thread Daniele Ceraolo Spurio
On 8/23/19 5:36 AM, Jani Nikula wrote: On Fri, 23 Aug 2019, Jani Nikula wrote: On Thu, 22 Aug 2019, Daniele Ceraolo Spurio wrote: On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: On 8/20/19 8:42 AM, Michal Wajdeczko wrote: On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio

[Intel-gfx] [RFC] drm/i915/tgl: Advanced preparser support for GPU relocs

2019-08-22 Thread Daniele Ceraolo Spurio
even legacy parsing capabilities are disabled in this scenario. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 45 -- drivers/gpu/drm/i915/gt/intel_engine.h| 9 +++ drivers/gpu

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Introduce intel_reg_types.h

2019-08-22 Thread Daniele Ceraolo Spurio
On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: On 8/20/19 8:42 AM, Michal Wajdeczko wrote: On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio wrote: diff --git a/drivers/gpu/drm/i915/intel_reg_types.h b/drivers/gpu/drm/i915/intel_reg_types.h new file mode 100644 index

  1   2   3   4   5   6   7   8   9   >