[Intel-gfx] [PATCH V3] drm/i915: Add sprite watermark programming for VLV and CHV

- Changed to bitwise shorthand operator for sprite_dl assignment Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/i915_reg.h |9 +++-- drivers/gpu/drm/i915/intel_pm.c | 33 + 2 files changed, 36 insertions(+), 6 deletions(-) diff

[Intel-gfx] [PATCH v3] drm/i915: Generalize drain latency computation

- Use cursor_base instead of reg read v3: Changed to bitwise shorthand operator for plane_dl assignment. Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 87 ++- 2 files changed

[Intel-gfx] [PATCH v2 1/2] drm/i915: Generalize drain latency computation

- Use cursor_base instead of reg read Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 88 +++ 2 files changed, 52 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 2/2] drm/i915: Round-up clock and limit drain latency

Round up clock computation and limit drain latency to maximum of 0x7F. Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_pm.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2] drm/i915: Add sprite watermark programming for VLV and CHV

Program DDL register as part of sprite watermark programming for CHV and VLV. v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 44 +++ 1 file changed, 44 insertions

[Intel-gfx] [PATCH 2/3] drm/i915: Generalize drain latency computation

Modify drain latency computation to use it for any plane. Same function can be used for primary, cursor and sprite planes. Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 82

[Intel-gfx] [PATCH 3/3] drm/i915: Add sprite watermark programming for VLV and CHV

Program DDL register as part sprite watermark programming for CHV and VLV. Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 44 +++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b

[Intel-gfx] [PATCH 1/3] drm/i915: Update DDL only for current CRTC

Instead of looping through all CRTCs, update DDL for current CRTC for which watermark is being updated. CHV is confirmed to have precision of 32/64 which is same as VLV. Signed-off-by: Gajanan Bhat gajanan.b...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 25 + 1

[Intel-gfx] [PATCH 0/3] Update DDL code to support sprite watermarks

.html http://lists.freedesktop.org/archives/intel-gfx/2014-June/048153.html Gajanan Bhat (3): drm/i915: Update DDL only for current CRTC drm/i915: Generalize drain latency computation drm/i915: Add sprite watermark programming for VLV and CHV drivers/gpu/drm/i915/i915_reg.h |1 + drivers