[PATCH v1 2/3] drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

From: Harish Chegondi Xe_LPG+ (IP version 12.74) should take the same general code paths as Xe_LPG (versions 12.70 and 12.71). Xe_LPG+'s workaround list will be handled by the next patch. Signed-off-by: Harish Chegondi Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt

[PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

-off-by: Harish Chegondi Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 + drivers/gpu/drm/i915/i915_perf.c| 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff

[PATCH v1 1/3] drm/i915: Add additional ARL PCI IDs

From: Matt Roper Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list. Bspec: 55420 Signed-off-by: Matt Roper --- include/drm/i915_pciids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/i915_pciids.h

[PATCH v1 0/3] Extend ARL support

Some SKUs of Arrow Lake use a slightly newer Xe_LPG+ graphics IP (version 12.74). Add some additional PCI IDs and extend the code to support this newer IP version. The general code flow should continue to match existing MTL and Xe_LPG code paths. Harish Chegondi (1): drm/i915/xelpg: Extend

[PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

-off-by: Harish Chegondi Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 + drivers/gpu/drm/i915/i915_perf.c| 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff

[PATCH v1 2/3] drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

From: Harish Chegondi Xe_LPG+ (IP version 12.74) should take the same general code paths as Xe_LPG (versions 12.70 and 12.71). Xe_LPG+'s workaround list will be handled by the next patch. Signed-off-by: Harish Chegondi Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt

[PATCH v1 1/3] drm/i915: Add additional ARL PCI IDs

From: Matt Roper Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list. Bspec: 55420 Signed-off-by: Matt Roper --- include/drm/i915_pciids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/i915_pciids.h

[PATCH v1 0/3] Extend ARL support

Some SKUs of Arrow Lake use a slightly newer Xe_LPG+ graphics IP (version 12.74). Add some additional PCI IDs and extend the code to support this newer IP version. The general code flow should continue to match existing MTL and Xe_LPG code paths. Harish Chegondi (1): drm/i915/xelpg: Extend

[PATCH v2] drm/i915/mtl: Add fake PCH for Meteor Lake

interrupt(Matt Roper) Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/display/intel_backlight.c | 2 +- drivers/gpu/drm/i915/display/intel_bios.c| 3 +-- drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-

[PATCH] drm/i915/mtl: Add fake PCH for Meteor Lake

allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Removed unused macros of LNL amd MTL as well. Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/display/intel_backlight.

[PATCH] drm/i915/xelpg: Add fake PCH for xelpg

allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/display/intel_backlight.c | 2 +- drivers/gpu/drm/i915/display/inte

[PATCH] drm/i915: Add Wa_14019877138

Enable Force Dispatch Ends Collection for DG2. BSpec: 46001 Signed-off-by: Haridhar Kalvala Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Add Wa_14019877138

Enable Force Dispatch Ends Collection for DG2. BSpec: 46001 Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b

[Intel-gfx] [PATCH] drm/i915: ATS-M device ID update

ATS-M device ID update. BSpec: 44477 Signed-off-by: Haridhar Kalvala --- include/drm/i915_pciids.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 1c9ea6ab3eb9..fcf1849aa47c 100644 --- a/include/drm/i915_pciids.h

[Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_14017856879

Wa_14017856879 implementation for mtl. Bspec: 46046 Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers

[Intel-gfx] [PATCH dii-client] drm/i915/mtl: Add Wa_14017856879 for mtl

Wa_14017856879 implementation for mtl. Bspec: 46046 Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers