> -Original Message-
> From: Deak, Imre
> Sent: Friday, May 17, 2024 6:19 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K
> Subject: Re: [PATCH 2/2] drm/i915/hdcp: Check mst_port
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, May 2, 2024 4:14 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nautiyal, Ankit K
> ; Kandpal, Suraj
> Subject: Re: [PATCH 1/2] drm/i915/hdcp: Move aux assignment after
&
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Tuesday, April 30, 2024 12:05 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2
> on HDMI
>
> Hi Suraj,
>
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, April 24, 2024 3:19 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Kandpal, Suraj
>
> Subject: Re: [RFC 0/3] Enable darkscreen detection
>
> On Wed, 24 Apr
> -Original Message-
> From: Sebastian Wick
> Sent: Wednesday, April 24, 2024 2:51 AM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Kumar, Naveen1
>
>
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, April 23, 2024 10:14 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> S
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, April 23, 2024 8:25 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> S
> -Original Message-
> From: Sebastian Wick
> Sent: Wednesday, April 17, 2024 3:54 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Nikula, Jani
> ; Kumar, N
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, April 16, 2024 6:25 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Bhadane, Dnyaneshwar
> Subject: Re: [PATCH 1/2]
> -Original Message-
> From: Sebastian Wick
> Sent: Tuesday, April 16, 2024 7:10 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Nikula, Jani
> ; Kumar, Naveen
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, April 16, 2024 2:28 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kandpal, Suraj
> Subject: Re: [PATCH] drm/i915
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, April 16, 2024 1:08 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Bhadane, Dnyaneshwar
> ; Kandpal, Suraj
>
> Sub
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 11:50 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Syrjala, Ville
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 11:26 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Nikula, Jani
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 11:26 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Nikula, Jani
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 11:50 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Syrjala, Ville
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 10:55 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Syrjala, Ville
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 11:02 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Syrjala, Ville
> ; Kumar, Naveen
> -Original Message-
> From: Sebastian Wick
> Sent: Friday, April 5, 2024 10:46 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Syrjala, Ville
> ; Kumar, Naveen
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, April 4, 2024 2:34 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Syrjala, Ville ; Kumar, Naveen1
>
> Subject: [PATCH] drm/i915: Fix i915_display_info output when connectors are
> not active
>
> From: Ville Syrjälä
>
> Currently intel_connector_info(), which prints the per-connector output for
> i915_display_info, just bails out early if the connector doesn't have a
> current
> encoder. That
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Wednesday, March 27, 2024 9:32 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: Initalizalize capability variables
>
>
>
> > -Original
> Subject: [PATCH] drm/i915/dp: Fix the computation for compressed_bpp for
> DISPLAY < 13
>
> For DISPLAY < 13, compressed bpp is chosen from a list of supported
> compressed bpps. Fix the condition to choose the appropriate compressed
> bpp from the list.
>
LGTM,
Reviewed-by: Suraj Kandpal
>
> Hello Suraj,
>
> > -Original Message-
> > From: Kandpal, Suraj
> > Sent: Tuesday, March 26, 2024 10:45 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Borah, Chaitanya Kumar ; Kandpal,
> > Suraj
> > Subject: [PATCH] drm/i915/displ
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, March 6, 2024 5:57 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma ;
> Nautiyal, Ankit K
> Subject: Re: [PATCH] drm/i915/dp: Enable AUX based backlight for HDR
>
> On
> Subject: [PATCH 1/4] drm/i915/hdcp: Move intel_hdcp_gsc_message def away
> from header file
>
> Move intel_hdcp_gsc_message definition into intel_hdcp_gsc.h so that
> intel_hdcp_gsc_message can be redefined for xe as needed.
>
> --v2
> -Correct commit message to reflect what patch is
>
> Hey,
>
> Where is xe_hdcp_gsc_message.c defined in this series?
>
> I would move this part there.
>
Hi Maarten
So there is no xe_hdcp_gsc_message.c but just intel_hdcp_gsc_message.c which\
Was separated from intel_hdcp_gsc.c for the purpose of code sharing and this
Patch just build the
> > interaction of HDCP as a client with the GSC CS interface.
> >
> > --v2
> > -add kfree at appropriate place [Daniele] -remove useless define
> > [Daniele] -move host session logic to xe_gsc_submit.c [Daniele] -call
> > xe_gsc_check_and_update_pending directly in an if condition [Daniele]
> >
>
> On 2/9/2024 2:14 AM, Suraj Kandpal wrote:
> > Use xe_device struct instead of drm_i915_private so as to not cause
> > confusion and comply with Xe standards even though xe_device gets
> > translated to drm_i915_private.
>
> AFAIU xe_device does not get translated to drm_i915_private, it's
> Subject: Re: [PATCH 2/3] drm/xe/hdcp: Enable HDCP for XE
>
>
>
> On 2/2/2024 12:37 AM, Suraj Kandpal wrote:
> > Enable HDCP for Xe by defining functions which take care of
> > interaction of HDCP as a client with the GSC CS interface.
> >
> > Signed-off-by: Suraj Kandpal
> > ---
> >
> Subject: Re: [PATCH 2/2] drm/i915/lnl: Program PKGC_LATENCY register
>
> On Mon, 05 Feb 2024, Suraj Kandpal wrote:
> > Program the PKGC_LATENCY register with the highest latency from level
> > 1 and above LP registers else program with all 1's.
> > This is used to improve package C residency
=
>
> On 1/24/2024 6:50 PM, Nautiyal, Ankit K wrote:
> >
> > On 1/12/2024 1:11 PM, Suraj Kandpal wrote:
> >> Currently we are only checking capability of remote device and not
> >> immediate downstream device but during capability check we need are
> >> concerned with only the HDCP capability of
> Subject: [PATCH] drm/i915: Try to preserve the current shared_dpll for fastset
> on type-c ports
>
> From: Ville Syrjälä
>
> Currently icl_compute_tc_phy_dplls() assumes that the active PLL will be the
> TC PLL (as opposed to the TBT PLL). The actual PLL will be selected during the
> modeset
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, November 22, 2023 12:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj ; Manna, Animesh
> ; jani.nik...@linux.intel.com; Nautiyal, Ankit K
>
> Subject: [PATCH] drm/i915/displ
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer unit data for
> hblank_early calculation.
>
> v2:
> -Fix tu_data calculation while dealing with U6.4 format.
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
> v1:
> Replace the computation of 'data_clock' with 'data_clock =
> DIV_ROUND_UP(data_clock, 16).' (Sui
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 ; Kulkarni, Vandita
> ; Kandpal, Suraj ;
> suijingf...@loongson.cn
> Subject
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 ; Kulkarni, Vandita
> ; Kandpal, Suraj ;
> suijingf...@loongson.cn
> Subject
> Subject: [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per
> DSC precision support
>
> Currently we iterate over the bpp_x16 in step of 16.
> Use DSC fractional bpp precision supported by the sink to compute the
> appropriate steps to iterate over the bpps.
>
LGTM.
Reviewed-by:
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 ; Kulkarni, Vandita
> ; Kandpal, Suraj ;
> suijingf...@loongson.cn
> Subject
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, November 9, 2023 9:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: remove excess functions from plane
> protection check
>
> Reduce the
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, November 9, 2023 9:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: abstract plane protection check
>
> Centralize the conditions in a
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, November 7, 2023 9:48 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 4/4] drm/i915/dp: Ignore max_requested_bpc if its
> too low for DSC
>
> At the moment,
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, November 7, 2023 9:48 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Use helpers to get dsc
> min/max input bpc
>
> Use helpers for
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Monday, October 16, 2023 10:51 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/vdsc: Remove old comment about
> DSC 444 support
>
> DSC with YCbCr420 is now supported, so
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Monday, October 16, 2023 10:51 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: Use helper to calculate
> range_bpg_offset
>
> We get range_bpg_offset for different
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, October 26, 2023 3:34 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nautiyal, Ankit K
> ; Kandpal, Suraj
> Subject: Re: [PATCH 2/3] drm/i915/hdcp: Create a blanket
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, October 26, 2023 1:02 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nautiyal, Ankit K
> ; Kandpal, Suraj
> Subject: Re: [PATCH 1/2] drm/i915/hdcp: Create a blanket
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, October 9, 2023 6:08 PM
> To: Kandpal, Suraj
> Cc: Jani Nikula ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Free crtc_state in
> verify_crtc_state
>
> On
> -Original Message-
> From: Jani Nikula
> Sent: Monday, October 9, 2023 4:07 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Free crtc_state in
> verify_crtc_state
>
> On Mon, 09 Oct 2023, Suraj
> -Original Message-
> From: Jani Nikula
> Sent: Monday, October 9, 2023 3:37 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v5 1/2] drm/i915/hdcp: Move checks for gsc
> health status
>
> On Mon, 09 Oct 2023, Suraj
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/ddi: Fix i2c_adapter assignment
>
> On Thu, 05 Oct 2023, Ville Syrjälä wrote:
> > On Thu, Oct 05, 2023 at 12:12:58PM +0530, Suraj Kandpal wrote:
> >> i2c_adapter is being assigned using intel_connector even before the
> >> NULL check occurs and even
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/ddi: Fix i2c_adapter assignment
>
> Hi Suraj,
>
> On Thu, Oct 05, 2023 at 12:12:58PM +0530, Suraj Kandpal wrote:
> > i2c_adapter is being assigned using intel_connector even before the
> > NULL check occurs and even though it shouldn't be a problem
> Subject: Re: [PATCH v3 2/2] drm/i915/hdcp: Move common message filling
> function to its own file
>
> On Wed, 20 Sep 2023, Suraj Kandpal wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h
> > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h
> > new file mode
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message
> filling function to its own file
>
> On Wed, 20 Sep 2023, Suraj Kandpal wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> > index
> Subject: [Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
>
Commit message style should be imperative so the header becomes something
Around the lines of
"Add Wa_18022495364"
> Set the instruction and state cache invalidate bit using INDIRECT_CTX on every
> gpu context switch.
> The
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
I think you forgot to add my reviewed by that I gave in the last revision
Anyways,
LGTM.
Reviewed-by:
> Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
>
> From: Ankit Nautiyal
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
>
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> ---
>
> Subject: [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when
> forced from debugfs
>
> From: Swati Sharma
>
> If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
> compressed bpp is fractional. Continue if the computed compressed bpp turns
> out to be a integer.
> Subject: [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC
> fractional
> bpp
>
> From: Swati Sharma
>
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to
> depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If
> Subject: [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step
> size
>
> From: Ankit Nautiyal
>
> This patch adds support to iterate over compressed output bpp as per the
> fractional step, supported by DP sink.
>
> v2:
> -Avoid ending up with compressed bpp, same as pipe
> Subject: [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp
>
> From: Vandita Kulkarni
>
> Consider the fractional bpp while reading the qp values.
>
> v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by:
> Subject: RE: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4
> format
>
> > Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4
> > format
> >
> > From: Ankit Nautiyal
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the
> Subject: [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while
> computing tu_data
>
> From: Ankit Nautiyal
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation
> Subject: [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while
> computing m_n values
>
> From: Ankit Nautiyal
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while
> Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
>
> From: Ankit Nautiyal
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
>
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
I think this should also be floated in drm-devel mailing list.
Regards,
Suraj Kandpal
>
> Signed-off-by:
> Subject: RE: [Intel-gfx] [PATCH 3/3] drm/i915/display: Configure and
> initialize
> HDMI audio capabilities
>
> Hi Suraj,
>
> > -Original Message-
> > From: Kandpal, Suraj
> > Sent: 05 September 2023 14:47
> > To: Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 5/8] drm/i915/dsc: drop redundant = 0 assignments
>
> Directly assign the values instead of first assigning 0 and then |= the
> values.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Suraj Kandpal
> Cc: Ankit Nautiyal
> Signed-off-by: Jani Nikula
> ---
>
> Subject: [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends
> for PPS0 and PPS1
>
> Use the register helper macros for PPS0 and PPS1 register contents.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Suraj Kandpal
> Cc: Ankit Nautiyal
> Signed-off-by: Jani Nikula
> ---
>
> Subject: [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content
> macros
>
> Improve clarity by specifying the PPS number in the register content macros.
> It's
> easier to notice if macros are being used for the wrong register.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Suraj
> Subject: [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content
> macros
>
> Improve clarity by specifying the PPS number in the register content macros.
> It's
> easier to notice if macros are being used for the wrong register.
LGTM.
Reviewed-by : Suraj Kandpal
>
> Cc:
> Subject: [PATCH 6/8] drm/i915/dsc: clean up pps comments
>
> Unify comments to be the simple "PPS n" instead of all sorts of variants.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Suraj Kandpal
> Cc: Ankit Nautiyal
> Signed-off-by: Jani Nikula
> ---
>
> Subject: [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write()
>
> Make the function name conform to existing style better.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Suraj Kandpal
> Cc: Ankit Nautiyal
> Signed-off-by: Jani Nikula
> ---
>
> Subject: [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() return the value
>
> Register read functions usually return the value instead of passing via
> pointer
> parameters. Return the multiple register verification results via a pointer
> parameter, which can also be NULL to skip the
> Subject: [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify()
> return the value
>
> Register read functions usually return the value instead of passing via
> pointer
> parameters. The calling code becomes easier to read.
>
> Make the name conform to existing style better while at
> Subject: [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write
> helpers
Should be clarity here in the commit header
With that fixed
Reviewed-by: Suraj Kandpal
>
> Make it clear what's the number of vdsc per pipe, and what's the number of
> registers to grab. Have
> Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display: Configure and initialize
> HDMI
> audio capabilities
>
> Initialize the source audio capabilities in the crtc_state property, setting
> them to
Nit: maybe mention the above as intel_crtc_state rather than crtc_state
property as
property
> Subject: [Intel-gfx] [PATCH 2/3] drm: Add Wrapper Functions for ELD SAD
> Extraction
>
> Add wrapper functions to facilitate extracting Short Audio Descriptor (SAD)
> information from EDID-Like Data (ELD) pointers with different constness
> requirements.
>
> 1. `drm_eld_sad`: This function
> Subject: RE: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for
> fractional
> bpp
>
> > Subject: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for
> > fractional bpp
> >
> > From: Vandita Kulkarni
> >
> > Consider the fractional bpp while reading the qp values.
> >
> > v2: Use
> Subject: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional
> bpp
>
> From: Vandita Kulkarni
>
> Consider the fractional bpp while reading the qp values.
>
> v2: Use helpers for fractional, integral bits of bits_per_pixel.
>
> Signed-off-by: Vandita Kulkarni
>
> Subject: RE: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
>
> > Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed
> > bpp in
> > U6.4 format
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 27
> +
> include/drm/display/drm_dp_helper.h | 1 +
> 2 files changed, 28 insertions(+)
>
> diff --git
> Subject: [Intel-gfx] [PATCH 3/9] drm/i915/display: Consider fractional vdsc
> bpp while computing m_n values
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
>
> > Add helper to get the DSC bits_per_pixel precision for the DP sink.
> >
> > Signed-off-by: Ankit Nautiyal
Wouldn't we also need to send this patch to dri-devel
Regards,
Suraj Kandpal
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 27
> > +
> >
> Subject: [Intel-gfx] [PATCH 4/9] drm/i915/audio : Consider fractional vdsc bpp
> while computing tu_data
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer
> Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
> integral part
> >> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out
> >> of the main _max_lane_count() func
> >>
> >> From: Luca Coelho
> >>
> >> This makes the code a bit more symmetric and readable, especially
> >> when we start adding more display version-specific alternatives.
> >>
> >>
> On Wed, 2023-08-16 at 08:54 +0000, Kandpal, Suraj wrote:
> > > This makes the code a bit more symmetric and readable, especially
> > > when we start adding more display version-specific alternatives.
> > >
> > > Signed-off-by: Luca Coelho
> > > --
> On Wed, 2023-08-16 at 08:54 +0000, Kandpal, Suraj wrote:
> > > This makes the code a bit more symmetric and readable, especially
> > > when we start adding more display version-specific alternatives.
> > >
> > > Signed-off-by: Luca Coelho
> &
> From: Luca Coelho
>
> It is irrelevant for the caller that the max lane count is being derived from
> a FIA
> register, so having "fia" in the function name is irrelevant. Rename the
> function accordingly.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Luca Coelho
> Reviewed-by:
> It is irrelevant for the caller that the max lane count is being derived from
> a FIA
> register, so having "fia" in the function name is irrelevant. Rename the
> function accordingly.
>
> Signed-off-by: Luca Coelho
LGTM.
Reviewed-by: Suraj Kandpal
> ---
>
> -Original Message-
> From: Intel-gfx On Behalf Of Lucas
> De Marchi
> Sent: Wednesday, August 23, 2023 10:37 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Coelho, Luciano
> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
>
> Subject: [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for
> planar yuv on xe2lpd
>
> From: Juha-Pekka Heikkilä
>
> Enable odd size and panning for planar yuv formats.
>
> Cc: Suraj Kandpal
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Lucas De Marchi
Maybe add the
0/4] drm/i915/tc: some clean-ups in max
> lane count handling code
>
> On Fri, Jul 21, 2023 at 02:11:17PM +0300, Luca Coelho wrote:
> >Hi,
> >
> >Here are four patches with some clean-ups in the code that handles the
> >max lane count of Type-C connections.
> >
> >This is done mostly in
>
> On Thu, 17 Aug 2023, Imre Deak wrote:
> > A follow-up patch will need to limit the output link bpp both in the
> > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > separately in the link_config_limits struct.
> >
> > Use .4 fixed point format for link bpp matching the
] [PATCH] drm/i915/dsi: Explicit first_line_bpg_offset
> assignment for DSI
>
> On Wed, 16 Aug 2023, "Kandpal, Suraj" wrote:
> >>
> >> On Wed, 16 Aug 2023, Jani Nikula wrote:
> >> > On Wed, 16 Aug 2023, "Kandpal, Suraj"
&g
> >
> > On Wed, 16 Aug 2023, Jani Nikula wrote:
> > > On Wed, 16 Aug 2023, "Kandpal, Suraj"
> wrote:
> > >>> On Mon, 07 Aug 2023, Suraj Kandpal
> wrote:
> > >>> > Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1
>
> On Wed, 16 Aug 2023, Jani Nikula wrote:
> > On Wed, 16 Aug 2023, "Kandpal, Suraj" wrote:
> >>> On Mon, 07 Aug 2023, Suraj Kandpal wrote:
> >>> > Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for
> >>> >
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