this is not
true and hence we would need to program PLL values by the
driver. The patch suggests a workaround as enabling full
modeset when booting up. This way we force the driver to
write the PLL values to the hw.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +
1
This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index
by the driver.
Signed-off-by: Mika Kahola
Mika Kahola (2):
Revert "drm/i915/display: Skip C10 state verification in case of
fastset"
drm/i915/display: Force full modeset for eDP
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
drivers/gpu/drm/i915/display/intel_dp.c
We used to select between MPLLA/B with the following
state->tx[0] & C20_PHY_USE_MPLLB
Since this is used a few places within C20 PLL setting,
let's introduce a helper function to clean up the code
a bit.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy
The function intel_c20_use_mplla() is not really
widely used and can be replaced with the more suitable
pll->tx[0] & C20_PHY_USE_MPLLB
expression. Let's remove the intel_c20_use_mplla()
alltogether and replace mplla/mpllb selection by
checking mpllb bit.
Signed-off-by: Mika Kahola
---
We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c |
if these two
selections match.
Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")
v2: reword commit message and include fix to a
original commit (Imre)
Compare pll selection (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_
Signed-off-by: Mika Kahola
Mika Kahola (3):
drm/i915/display: Fix C20 pll selection for state verification
drm/i915/display: Store hw clock for C20
drm/i915/display: Cleanup mplla/mpllb selection
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 153 ++-
1 file changed, 78
We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c |
if these two
selections match.
Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")
v2: reword commit message and include fix to a
original commit (Imre)
Compare pll selection (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_
The function intel_c20_use_mplla() is not really
widely used and can be replaced with the more suitable
pll->tx[0] & C20_PHY_USE_MPLLB
expression. Let's remove the intel_c20_use_mplla()
alltogether and replace mplla/mpllb selection by
checking mpllb bit.
Signed-off-by: Mika Kahola
---
Signed-off-by: Mika Kahola
Mika Kahola (3):
drm/i915/display: Fix C20 pll selection for state verification
drm/i915/display: Store hw clock for C20
drm/i915/display: Cleanup mplla/mpllb selection
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 153 ++-
1 file changed, 78
PLL's are not programmed in case of fastset so the state
verfication compares bios programmed PLL values against
sw PLL values. To overcome this limitation, we can skip
the state verification for C10 in fastset case as the
driver is not writing PLL values.
Signed-off-by: Mika Kahola
---
drivers
Add clock state verification for C20. Since we
are usign either A or B contexts, which are
selected based on clock rate, we first need to
calculate hw clock and use that clock to select
which context we are using.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8
: Cleanup for increased readibility (Imre)
BSpec: 65380
For VLK-53734
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915
: 65380
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f64d348a969e..79ec17fa3edd 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
Print out clock rate for C10 chip and clock rate and link bitrate
for C20 chip for debugging purposes.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
to corresponding PLL clock rate.
while at it, update clock on C10 pll state as well.
Signed-off-by: Clint Taylor
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 38 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
drivers/gpu/drm/i915/display
Moving intel_c20pll_readout_hw_state() for better place
to better suit for upcoming changes.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 116 +--
1 file changed, 58 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
While reading HW state for C10 and C20 chips, let's update the PLL
clock rates. For C20 the clock rate differs from link bit rate on
DP2.0 cases and hence a conversion from link bitrate to clock is
needed.
Signed-off-by: Mika Kahola
Mika Kahola (3):
drm/i915/display: Move C20 HW readout
drm
tries."
Signed-off-by: Mika Kahola
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a8
tries."
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a8fa76580802..3a30cffd450c 100644
--- a/drivers/gp
itted one frame earlier")
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8d180132a74b..204da50e3f28 100644
---
At least one TGL had regression when using u8 types
for entry setup frames calculation. So, let's switch
to use ints instead.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
Add state verification for C20 as we have one
for C10.
V2: Use abstractation of HW readout (Gustavo)
Drop MPLLA/B from message for TX and CMN
parameters (Gustavo)
Reviewed-by: Gustavo Sousa (v1)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 120
d of dev_priv (Jouni)
Signed-off-by: Mika Kahola
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 82 +++
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
3 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/dr
Add state verification for C20 as we have one
for C10.
v2: use register values as u32 instead of u8
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 107 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
.../drm/i915/display
try Setup Frames register to indicate
Lunarlake specificity (Jouni)
v3: Modify setup entry frames calculation function to
return the actual frames (Ville)
Match comment with actual implementation (Jouni)
Signed-off-by: Mika Kahola
---
.../drm/i915/display/intel_display_types.h|
Add state verification for C20 as we have one
for C10.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 111 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 2 +-
3 files changed, 88
It is possible that sticky bits or error bits are left on
message bus status register. Reading and then writing the
value back to messagebus status register clears all possible
sticky bits and errors.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14
tup Frames register to indicate Lunarlake specificity
(Jouni)
Signed-off-by: Mika Kahola
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 77 ++-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
3 files changed,
ver should enable sending VSC SDP one frame earlier before sending
the capture frame.
BSpec: 69895 (PSR Entry Setup Frames 17:16)
Signed-off-by: Mika Kahola
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 35 ---
drivers/gpu/
every successful or unsuccessful
read or write operation.
v2: Add FIXME's to indicate the experimental nature of
this workaround (Rodrigo)
v3: Dropping the additional delay as moving reset to *_read_once()
and *_write_once() functions seem unnecessary delay
Signed-off-by: Mika Kahola
.
v2: Add FIXME's to indicate the experimental nature of
this workaround (Rodrigo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm
removal as irrelevant for this patch (Ville)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index bb65881e87cc
Currently we are not using watchdog timers for PSR/PSR2
with Lunarlake. The patch removes the use of these timers
from the driver code.
BSpec: 69895
v2: Reword commit message (Ville)
Drop HPD mask from LNL (Ville)
Revise masking logic (Jouni)
Signed-off-by: Mika Kahola
---
drivers/gpu
Currently we are not using watchdog timers for PSR/PSR2.
The patch disables these timers so they are not in use.
BSpec: 69895
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_psr.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git
every successful or unsuccessful
read or write operation. However, testing revealed that this
alone is not sufficient method an additiona delay is also
introduces anything from 200us to 300us. This delay is experimental
value and has no specification to back it up.
Signed-off-by: Mika Kahola
ove reset to corresponding
timeout error and drop the excess reset function calls from
read/write functions.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
for lanes and revise the commit message (Luca)
Reviewed-by: Arun R Murthy (v1)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers
In case when only two or less lanes are owned such as MFD (DP-alt with x2 lanes)
we need to reset only one lane (lane0). With only x2 lanes we don't need
to poll for the phy current status on both lanes since only the owned lane
will respond.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915
While disabling Thunderbolt PLL, we request PLL to be stopped and
wait for ACK bit to be cleared. The expected value should be '0'
instead of '~XELPDP_TBT_CLOCK_ACK' or otherwise we incorrectly
receive dmesg warn "PHY PLL not unlocked in 10us".
Signed-off-by: Mika Kahola
---
drive
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index b192265a3d78..4fca711a58bc 100644
--- a/drivers/gpu/drm
Finally, we can enable TC ports for Meteorlake.
Reviewed-by: Clint Taylor
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915
Readout hw state for Thunderbolt.
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files
-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 951b12ac51dc..b192265a3d78 100644
--- a/drivers/gpu/drm/i915
Enabling and disabling sequence for Thunderbolt PLL.
Bspec: 64568
v2: Use intel_de_wait_for_register() (RK)
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h
-by: Matt Atwood
Signed-off-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display
Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled.
v2: Fix typo in commit message (Animesh)
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
Calculate port clock with C20 phy.
BSpec: 64568
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display
-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 624 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
drivers/gpu/drm/i915/display
() instead of msleep() (Andi)
Reviewed-by: Arun R Murthy
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 288 +++---
.../gpu/drm
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
v2: Fixes for C20 pll programming and hw readout
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Signed-off-by: Anusha Srivatsa
Signed-off-by: Jose Roberto de Souza
Signed-off-by: Mika
-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display/intel_ddi_buf_trans.c| 53
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 138
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
Calculate port clock with C20 phy.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
drivers/gpu/drm/i915/display
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Signed
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Signed
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak
message.
v3:
- Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
of TRANS_DDI_FUNC_CTL_*. (Gustavo)
Signed-off-by: Ankit Nautiyal
Signed-off-by: Taylor, Clinton A
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +---
drivers
ked-by: Matt Roper
Signed-off-by: Satyeshwar Singh
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Ankit Nautiyal
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 +
drivers/gpu/drm/i915/disp
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
v4: Redefine macros (Imre)
Reviewed-by: Vinod Govindapillai (v3)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 249 +++-
drivers/gpu/drm/i915/i915_reg.h | 31 +++-
2 files changed, 273 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 61 +--
drivers/gpu/drm/i9
)
General cleanups and macro definitions (Imre)
Signed-off-by: Mika Kahola
Ankit Nautiyal (1):
drm/i915/display/mtl: Fill port width in
DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
José Roberto de Souza (1):
drm/i915/mtl
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by:
er
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_dis
two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to
with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika
programming (Khaled)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by:
Phy programming support for C10 PICA chips. This is the first part of
the series that adds support for PICA chips. Later the support for
C20 chips are added.
Signed-off-by: Mika Kahola
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Mika Kahola (3):
drm/i915/mtl: Add DP rates
drm
tcss power request with correct parameter.
v3: Use de variant for register wait (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117 ++-
2 files changed, 114 insertions(+), 5 deletions
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 136
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915
Calculate port clock with C20 phy.
v2: Initialize parameters
v3: Revised formula for port clock check
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 70 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display
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