Re: [Intel-gfx] [PATCH] drm/i915: Use ktime on wait_for

[Sagar Arun Kamble]

On 4/20/2018 4:09 PM, Chris Wilson wrote:

Quoting Sagar Arun Kamble (2018-04-20 11:23:50)


On 4/20/2018 3:24 PM, Mika Kuoppala wrote:

We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When this happens
in a wait_for loop, we return timeout errorneously
much earlier than what the real wallclock would say.

We can't afford our waits to timeout prematurely.
Discard jiffies and change to ktime to detect timeouts.

Reported-by: Imre Deak <imre.d...@intel.com>
References: https://lkml.org/lkml/2018/4/18/798 [1]
Cc: Imre Deak <imre.d...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
   drivers/gpu/drm/i915/intel_drv.h | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8b20824e806e..ac7565220aa3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -49,12 +49,12 @@
* check the condition before the timeout.
*/
   #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
- unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
+ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \

Is ktime_get_raw() monotonic? Thomas suggested ktime_get()

It proclaims to be monotonic, without the clock drift calibration. For
the milliseconds we should be sleeping at most, I hope that is
immaterial.
Yes. I remembered from Imre's comment[1] that raw clock can jump and 
will not be calibrated. If jumps are are not > jiffies we should be good 
get_raw then.


[1] 
https://lists.freedesktop.org/archives/dri-devel/2012-October/028878.html

-Chris


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Re: [Intel-gfx] [PATCH] drm/i915: Use ktime on wait_for

[Sagar Arun Kamble]

On 4/20/2018 3:24 PM, Mika Kuoppala wrote:

We use jiffies to determine when wait expires. However
Imre did find out that jiffies can and will do a >1
increments on certain situations [1]. When this happens
in a wait_for loop, we return timeout errorneously
much earlier than what the real wallclock would say.

We can't afford our waits to timeout prematurely.
Discard jiffies and change to ktime to detect timeouts.

Reported-by: Imre Deak 
References: https://lkml.org/lkml/2018/4/18/798 [1]
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Ville Syrjälä 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/intel_drv.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8b20824e806e..ac7565220aa3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -49,12 +49,12 @@
   * check the condition before the timeout.
   */
  #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
-   unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
+   const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \

Is ktime_get_raw() monotonic? Thomas suggested ktime_get()

long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
int ret__;  \
might_sleep();  \
for (;;) {  \
-   bool expired__ = time_after(jiffies, timeout__);\
+   const bool expired__ = ktime_after(ktime_get_raw(), end__); \
OP; \
if (COND) { \
ret__ = 0;  \


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Re: [Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Sagar Arun Kamble]

On 4/13/2018 9:30 PM, Oscar Mateo wrote:

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Praveen Paneri <praveen.pan...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
  drivers/gpu/drm/i915/intel_workarounds.c | 4 
  2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
  #define GEN8_GARBCNTL   _MMIO(0xB004)
  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
  
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)

+#define   DFR_DISABLE  (1 << 9)
+
  /* IVYBRIDGE DPF */
  #define GEN7_L3CDERRST1(slice)_MMIO(0xB008 + (slice) * 0x200) 
/* L3CD Error Status 1 */
  #define   GEN7_L3CDERRST1_ROW_MASK(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 8c2d17c..34a0b56 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
  
+	/* This is not an Wa. Enable to reduce Sampler power */

+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));


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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

[Sagar Arun Kamble]

On 4/9/2018 9:02 PM, Michal Wajdeczko wrote:
On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork 
 wrote:



== Series Details ==

Series: series starting with [v8,01/12] drm/i915: Park before 
resetting the submission backend

URL   : https://patchwork.freedesktop.org/series/41365/
State : failure

== Summary ==

 Possible new issues:


two variants:



Test drm_mm:
    Subgroup sanitycheck:
    pass   -> INCOMPLETE (shard-apl)


#1

<0>[  400.245461] drv_self-5775    1 400208508us : 
intel_guc_submission_disable: intel_guc_submission_disable:1255 
GEM_BUG_ON(dev_priv->gt.awake)


<4>[  400.245871] Call Trace:
<4>[  400.245959]  intel_uc_fini_hw+0x4b/0xe0 [i915]
<4>[  400.246047]  i915_gem_fini_hw+0x16/0x30 [i915]
<4>[  400.246129]  i915_reset+0x1e8/0x2b0 [i915]
<4>[  400.246222]  igt_global_reset+0x38/0xe0 [i915]


Without gem_set_wedged if i915_reset path is invoked we can face this issue.
igt_global_reset and gem_eio resets are directly invoking 
i915_handle_error/i915_reset so I think we should fix the IGTs.

Test drv_hangman:
    Subgroup error-state-capture-blt:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-bsd:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-render:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-vebox:
    pass   -> INCOMPLETE (shard-apl)
Test drv_selftest:
    Subgroup live_guc:
    pass   -> SKIP   (shard-apl)
    Subgroup live_hangcheck:
    pass   -> DMESG-FAIL (shard-apl)
Test gem_eio:
    Subgroup execbuf:
    pass   -> INCOMPLETE (shard-apl)


#2:

<3>[  227.833798] intel_engine_unpin_breadcrumbs_irq:219 
GEM_BUG_ON(!b->irq_enabled)


<4>[  227.834607] Call Trace:
<4>[  227.834691]  intel_engines_park+0xef/0x180 [i915]
<4>[  227.834709]  ? synchronize_irq+0x3e/0xb0
<4>[  227.834781]  __i915_gem_park+0x3e/0x160 [i915]
<4>[  227.834850]  i915_gem_idle_work_handler+0x1cd/0x220 [i915]
<4>[  227.834868]  process_one_work+0x21a/0x640


irq disabling with GuC submission is not taking into consideration if it 
was enabled by waiter.
May be we should skip disarming interrupts while parking if there was no 
waiter since we will disarm them

during engine->park. Something like below?

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c

index 671a6d6..f8c0c4d 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -231,6 +231,13 @@ void intel_engine_disarm_breadcrumbs(struct 
intel_engine_cs *engine)

    return;

    /*
+    * In case of reset with GuC submission we disarm the interrupts
+    * while parking if there are no waiters.
+    */
+   if (USES_GUC_SUBMISSION(engine->i915) && !b->irq_wait)
+   return;
+
+   /*
 * We only disarm the irq when we are idle (all requests 
completed),

 * so if the bottom-half remains asleep, it missed the request
 * completion.

    Subgroup in-flight-external:
    pass   -> INCOMPLETE (shard-apl)
Test gem_mocs_settings:
    Subgroup mocs-reset-dirty-render:
    pass   -> INCOMPLETE (shard-apl)
Test gem_request_retire:
    Subgroup retire-vma-not-inactive:
    pass   -> INCOMPLETE (shard-apl)
Test gem_workarounds:
    Subgroup reset-context:
    pass   -> INCOMPLETE (shard-apl)
Test kms_vblank:
    Subgroup pipe-a-query-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-ts-continuation-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-forked-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-b-query-forked-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-forked-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-forked-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-ts-continuation-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
Test perf:
    Subgroup gen8-unprivileged-single-ctx-counters:
    pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
    pass   -> SKIP   (shard-apl) fdo#103199
Test gem_eio:
    Subgroup in-flight-suspend:
    pass   -> INCOMPLETE (shard-apl) fdo#103375
Test kms_flip:
    Subgroup flip-vs-expired-vblank:

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

As we always call intel_uc_sanitize after every call to
intel_uc_fini_hw we may drop redundant call and sanitize
uC from the fini_hw function.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

With change to sanitize during uc_init_mmio this looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c | 2 --
  drivers/gpu/drm/i915/intel_uc.c | 9 +++--
  drivers/gpu/drm/i915/intel_uc.h | 1 -
  3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ceec5a0..decda1a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3077,7 +3077,6 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
}
  
  	i915_gem_revoke_fences(dev_priv);

-   intel_uc_sanitize(dev_priv);
  
  	return err;

  }
@@ -5062,7 +5061,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machine in an unusable condition.
 */
i915_gem_fini_hw(dev_priv);
-   intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
  
  	intel_runtime_pm_put(dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..0439966 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -322,18 +322,13 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
intel_guc_fini(guc);
  }
  
-void intel_uc_sanitize(struct drm_i915_private *i915)

+static void __uc_sanitize(struct drm_i915_private *i915)
  {
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
  
-	if (!USES_GUC(i915))

-   return;
-
GEM_BUG_ON(!HAS_GUC(i915));
  
-	guc_disable_communication(guc);

-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
  
@@ -445,6 +440,8 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)

intel_guc_submission_disable(guc);
  
  	guc_disable_communication(guc);

+
+   __uc_sanitize(dev_priv);
  }
  
  int intel_uc_suspend(struct drm_i915_private *i915)

diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 25d73ad..64aaf93 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -33,7 +33,6 @@
  void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
  int intel_uc_init_misc(struct drm_i915_private *dev_priv);
  void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
-void intel_uc_sanitize(struct drm_i915_private *dev_priv);
  int intel_uc_init_hw(struct drm_i915_private *dev_priv);
  void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
  int intel_uc_init(struct drm_i915_private *dev_priv);


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Re: [Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

By calling i915_gem_init_hw in i915_gem_resume and not calling
i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry
in init_hw/fini_hw calls. Let's fix that.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6f71099..ceec5a0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5061,6 +5061,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machines is a good idea, we don't - just in case it leaves the
 * machine in an unusable condition.
 */
+   i915_gem_fini_hw(dev_priv);
intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
  


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Re: [Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

We have i915_gem_init_hw function that on failure requires some
cleanup in uC and then in other places we were trying to do
such cleanup directly. Let's fix that by adding i915_gem_fini_hw
for nice symmetry with init_hw and call it on cleanup paths.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.h |  1 +
  drivers/gpu/drm/i915/i915_gem.c | 13 +++--
  2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8bc276..dbd95a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3144,6 +3144,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
  int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
  void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
  void i915_gem_fini(struct drm_i915_private *dev_priv);
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
  void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
  int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fb99485..6f71099 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5257,6 +5257,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
goto out;
  }
  
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv)

+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   intel_uc_fini_hw(dev_priv);
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
  static int __intel_engines_record_defaults(struct drm_i915_private *i915)
  {
struct i915_gem_context *ctx;
@@ -5482,7 +5491,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
  err_init_hw:
i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED);
i915_gem_contexts_lost(dev_priv);
-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
  err_uc_init:
intel_uc_fini(dev_priv);
  err_pm:
@@ -5526,7 +5535,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
  
  	mutex_lock(_priv->drm.struct_mutex);

-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);


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Re: [Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

We should keep i915_gem_init/fini functions together for easier
tracking of their symmetry.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.c | 20 
  drivers/gpu/drm/i915/i915_drv.h |  1 +
  drivers/gpu/drm/i915/i915_gem.c | 20 
  3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f770be1..854b26c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -625,26 +625,6 @@ static bool i915_switcheroo_can_switch(struct pci_dev 
*pdev)
.can_switch = i915_switcheroo_can_switch,
  };
  
-static void i915_gem_fini(struct drm_i915_private *dev_priv)

-{
-   /* Flush any outstanding unpin_work. */
-   i915_gem_drain_workqueue(dev_priv);
-
-   mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
-   intel_uc_fini(dev_priv);
-   i915_gem_cleanup_engines(dev_priv);
-   i915_gem_contexts_fini(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
-
-   intel_uc_fini_misc(dev_priv);
-   i915_gem_cleanup_userptr(dev_priv);
-
-   i915_gem_drain_freed_objects(dev_priv);
-
-   WARN_ON(!list_empty(_priv->contexts.list));
-}
-
  static int i915_load_modeset_init(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9bca104..f8bc276 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3143,6 +3143,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
  int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
  int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
  void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
+void i915_gem_fini(struct drm_i915_private *dev_priv);
  void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
  int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 26294e8..fb99485 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5520,6 +5520,26 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
return ret;
  }
  
+void i915_gem_fini(struct drm_i915_private *dev_priv)

+{
+   /* Flush any outstanding unpin_work. */
+   i915_gem_drain_workqueue(dev_priv);
+
+   mutex_lock(_priv->drm.struct_mutex);
+   intel_uc_fini_hw(dev_priv);
+   intel_uc_fini(dev_priv);
+   i915_gem_cleanup_engines(dev_priv);
+   i915_gem_contexts_fini(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
+   intel_uc_fini_misc(dev_priv);
+   i915_gem_cleanup_userptr(dev_priv);
+
+   i915_gem_drain_freed_objects(dev_priv);
+
+   WARN_ON(!list_empty(_priv->contexts.list));
+}
+
  void i915_gem_init_mmio(struct drm_i915_private *i915)
  {
i915_gem_sanitize(i915);


--
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Sagar

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Re: [Intel-gfx] [PATCH] drm/i915: Park before resetting the submission backend

[Sagar Arun Kamble]

On 4/9/2018 3:48 PM, Chris Wilson wrote:

As different backends may have different park/unpark callbacks, we
should only ever switch backends (reset_default_submission on wedge
recovery, or on enabling the guc) while parked.

v2: Remove the assert from the guc code, as we are currently trying to
modify the engine vfuncs pointer on a live system after reset (not just
wedging). We will just have to hope that the system is balanced.
v3: Rebase onto __i915_gem_park and improve grammar.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c| 15 ---
  drivers/gpu/drm/i915/intel_engine_cs.c |  3 +++
  2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28ab0beff86c..dd3e292ba243 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -144,8 +144,6 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
if (!i915->gt.awake)
return I915_EPOCH_INVALID;
  
-	GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);

-
/*
 * Be paranoid and flush a concurrent interrupt to make sure
 * we don't reactivate any irq tasklets after parking.
@@ -173,6 +171,7 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
  
  	intel_runtime_pm_put(i915);
  
+	GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);

return i915->gt.epoch;
  }
  
@@ -3435,7 +3434,17 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)

}
}
i915_retire_requests(i915);
-   GEM_BUG_ON(i915->gt.active_requests);
+
+   /*
+* Park before disengaging the old submit mechanism as different
+* backends may have different park/unpack callbacks.
+*
+* We are idle; the idle-worker will be queued, but we need to run
+* it now. As we already hold the struct mutex, we can park the GPU
+* right away, letting the lazy worker see that we are already active
+* again by the time it acquires the mutex.
+*/
+   __i915_gem_park(i915);
  
  	/*

 * Undo nop_submit_request. We prevent all new i915 requests from
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8f534b..b4ea77a2896c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1651,6 +1651,9 @@ void intel_engines_reset_default_submission(struct 
drm_i915_private *i915)
struct intel_engine_cs *engine;
enum intel_engine_id id;
  
+	/* Must be parked first! */

+   GEM_BUG_ON(i915->gt.awake);
+
for_each_engine(engine, i915, id)
engine->set_default_submission(engine);
  }


--
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Park before resetting the submission backend

[Sagar Arun Kamble]

On 4/5/2018 4:32 PM, Chris Wilson wrote:

As different backends may have different park/unpark callbacks, we
should only ever switch backends (reset_default_submission on wedge
recovery, or on enabling the guc) while parked.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
  drivers/gpu/drm/i915/i915_gem.c | 11 +++
  drivers/gpu/drm/i915/intel_engine_cs.c  |  3 +++
  drivers/gpu/drm/i915/intel_guc_submission.c |  1 +
  3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e148db310ea6..e2880de2fc7e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3380,6 +3380,17 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
  
+	/*

+* Park before disengaging the old submit mechanism as different
+* backends may have different park/unpack callbacks.
+*
+* We are idle; the idle-worker will be queued, but we need to run
+* it now. As we already hold the struct mutex, we can get park
+* the GPU right away, letting the lazy worker see that we are
+* already active again by the time it acquires the mutex.
+*/
+   i915_gem_park(i915);

I think we should be calling this before gem_unset_wedged in i915_reset.
With GuC, hitting the GEM_BUG_ON(awake) in guc_submission_enable.
Also idle_work can execute just before reset so GEM_BUG_ON(!awake) in 
gem_park can be hit I think.

+
/*
 * Undo nop_submit_request. We prevent all new i915 requests from
 * being queued (by disallowing execbuf whilst wedged) so having
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8f534b..b4ea77a2896c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1651,6 +1651,9 @@ void intel_engines_reset_default_submission(struct 
drm_i915_private *i915)
struct intel_engine_cs *engine;
enum intel_engine_id id;
  
+	/* Must be parked first! */

+   GEM_BUG_ON(i915->gt.awake);
+
for_each_engine(engine, i915, id)
engine->set_default_submission(engine);
  }
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 97121230656c..225fa3927a02 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1243,6 +1243,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
/* Take over from manual control of ELSP (execlists) */
guc_interrupts_capture(dev_priv);
  
+	GEM_BUG_ON(dev_priv->gt.awake); /* Must be idle switching park/unpark */

for_each_engine(engine, dev_priv, id) {
struct intel_engine_execlists * const execlists =
>execlists;


--
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v6,01/12] drm/i915: Correctly handle error path in i915_gem_init_hw

[Sagar Arun Kamble]

On 4/5/2018 6:03 AM, Patchwork wrote:

== Series Details ==

Series: series starting with [v6,01/12] drm/i915: Correctly handle error path 
in i915_gem_init_hw
URL   : https://patchwork.freedesktop.org/series/41159/
State : failure

== Summary ==

 Possible new issues:

Test gem_eio:
 Subgroup execbuf:
 pass   -> INCOMPLETE (shard-apl)

I am seeing this failure w/o this patch series too.
Working fix  that I have tried is to unpark from reset path explicitly 
if GT is awake:


diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index d354627..2fc9d0e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1960,6 +1960,9 @@ void i915_reset(struct drm_i915_private *i915)
    goto error;
    }

+   if (i915->gt.awake)
+   intel_engines_unpark(i915);
+
    i915_queue_hangcheck(i915);

 finish:

This way we will balance the irq refcounts.

 Subgroup in-flight-external:
 pass   -> INCOMPLETE (shard-apl)
 Subgroup throttle:
 pass   -> INCOMPLETE (shard-apl)
Test perf:
 Subgroup gen8-unprivileged-single-ctx-counters:
 pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
 pass   -> SKIP   (shard-apl) fdo#103199
Test gem_eio:
 Subgroup in-flight-suspend:
 pass   -> INCOMPLETE (shard-apl) fdo#103375
 Subgroup suspend:
 pass   -> INCOMPLETE (shard-apl) fdo#103927 +1
Test kms_flip:
 Subgroup 2x-flip-vs-expired-vblank:
 fail   -> PASS   (shard-hsw) fdo#102887 +1
 Subgroup plain-flip-ts-check-interruptible:
 fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_sysfs_edid_timing:
 warn   -> PASS   (shard-apl) fdo#100047

fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:2701 pass:1404 dwarn:1   dfail:0   fail:6   skip:1274 
time:6843s
shard-hswtotal:3499 pass:1786 dwarn:1   dfail:0   fail:1   skip:1710 
time:11567s
shard-snbtotal:3499 pass:1378 dwarn:1   dfail:0   fail:2   skip:2118 
time:7127s
Blacklisted hosts:
shard-kbltotal:2429 pass:1334 dwarn:4   dfail:0   fail:6   skip:1065 
time:4018s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8581/shards.html
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--
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Re: [Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

On 3/30/2018 7:07 PM, Michal Wajdeczko wrote:
On Fri, 30 Mar 2018 10:31:50 +0200, Sagar Arun Kamble 
<sagar.a.kam...@intel.com> wrote:


diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/intel_guc_slpc.h

index 66c76fe..81250c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -6,6 +6,8 @@
 #ifndef _INTEL_GUC_SLPC_H_
 #define _INTEL_GUC_SLPC_H_
+#include 


Please use "" instead of <>

Yes. will hopefully not forget this next time :)



+
 struct intel_guc_slpc {
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h

new file mode 100644
index 000..9400af4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
@@ -0,0 +1,211 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+#ifndef _INTEL_GUC_SLPC_FWIF_H_
+#define _INTEL_GUC_SLPC_FWIF_H_
+
+#include 
+
+enum slpc_status {


s/slpc_status/intel_guc_slpc_status


I have done this because of following reasons:
1. GuC SLPC interface file shared by firmware team names enums/structs 
as SLPM_* or SLPM_KMD_*. i understand that this isn't strict requirement. :)

2. INTEL_GUC_STATUS|EVENT|PARAM_* becomes more than 80 chars for some values
3. I wanted intel_guc_slpc_fwif.h to be included only in 
intel_guc_slpc.c from where we can export functions as intel_guc_slpc_*

    static functions in intel_guc_slpc.c are named as slpc_*.
   In my series, point 3 above is not done but that was intent. There 
is access to SLPC enums from debugfs.c. Would consolidate all in 
intel_guc_slpc.c and export.


Does this plan look good?

+    SLPC_STATUS_OK = 0,
+    SLPC_STATUS_ERROR = 1,
+    SLPC_STATUS_ILLEGAL_COMMAND = 2,
+    SLPC_STATUS_INVALID_ARGS = 3,
+    SLPC_STATUS_INVALID_PARAMS = 4,
+    SLPC_STATUS_INVALID_DATA = 5,
+    SLPC_STATUS_OUT_OF_RANGE = 6,
+    SLPC_STATUS_NOT_SUPPORTED = 7,
+    SLPC_STATUS_NOT_IMPLEMENTED = 8,
+    SLPC_STATUS_NO_DATA = 9,
+    SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+    SLPC_STATUS_REGISTER_LOCKED = 11,
+    SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+    SLPC_STATUS_VALUE_ALREADY_SET = 13,
+    SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+    SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+    SLPC_STATUS_MEMIO_ERROR = 16,
+    SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+    SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+    SLPC_STATUS_NO_EVENT_QUEUED = 19,
+    SLPC_STATUS_OUT_OF_SPACE = 20,
+    SLPC_STATUS_TIMEOUT = 21,
+    SLPC_STATUS_NO_LOCK = 22,
+    SLPC_STATUS_MAX


s/SLPC_STATUS/INTEL_GUC_SLPC_STATUS


+};
+
+enum slpc_event_id {


s/slpc_event_id/intel_guc_slpc_event


+    SLPC_EVENT_RESET = 0,
+    SLPC_EVENT_SHUTDOWN = 1,
+    SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+    SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+    SLPC_EVENT_FLIP_COMPLETE = 4,
+    SLPC_EVENT_QUERY_TASK_STATE = 5,
+    SLPC_EVENT_PARAMETER_SET = 6,
+    SLPC_EVENT_PARAMETER_UNSET = 7,


s/SLPC_EVENT/INTEL_GUC_SLPC_EVENT


+};
+
+enum slpc_param_id {


s/slpc_param_id/intel_guc_slpc_param


+    SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+    SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+    SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+    SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+    SLPC_PARAM_TASK_ENABLE_DCC = 4,
+    SLPC_PARAM_TASK_DISABLE_DCC = 5,
+    SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+    SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+    SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+    SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+    SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+    SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+    SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+    SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+    SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+    SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+    SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+    SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+    SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+    SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,


s/SLPC_PARAM/INTEL_GUC_SLPC_PARAM


+    SLPC_MAX_PARAM,
+    SLPC_KMD_MAX_PARAM = 32,


hmm, do we really need these two ? please drop

or maybe these are related to SLPC_MAX_OVERRIDE_PARAMETERS ?

Ok. Will drop SLPC_KMD_MAX_PARAM.
There are total 192 params (MAX_OVERRIDE_PARAMS) out of which 32 
(KMD_MAX_PARAM) params can be exposed

to KMD, but currently only params till MAX_PARAM < 32 are exported.



+};
+
+enum slpc_global_state {


s/slpc_global_state/intel_guc_slpc_state


+    SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+    SLPC_GLOBAL_STATE_INITIALIZING = 1,
+    SLPC_GLOBAL_STATE_RESETTING = 2,
+    SLPC_GLOBAL_STATE_RUNNING = 3,
+    SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+    SLPC_GLOBAL_STATE_ERROR = 5


s/SLPC_GLOBAL_STATE/INTEL_GUC_SLPC_STATE


+};
+
+enum slpc_platform_sku {
+    SLPC_PLATFORM_SKU_UNDEFINED = 0,
+    SLPC_PLATFORM_SKU_ULX = 1,
+    SLPC_PLATFORM_SKU_ULT = 2,
+    SLPC_PLATFORM_SKU_T = 3,
+    S

Re: [Intel-gfx] [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

[Sagar Arun Kamble]

Thanks for the review. Will update with all suggestions in the next rev.

On 3/30/2018 6:07 PM, Michal Wajdeczko wrote:
On Fri, 30 Mar 2018 10:31:46 +0200, Sagar Arun Kamble 
<sagar.a.kam...@intel.com> wrote:



From: Tom O'Rourke <Tom.O'rou...@intel.com>

GuC is currently being used for submission and HuC authentication.
Choices can be configured through enable_guc modparam. GuC SLPC is GT
Power and Performance management feature in GuC. Add another option to
enable_guc modparam to control SLPC.

v1: Add early call to sanitize enable_guc_slpc in intel_guc_ucode_init
    Remove sanitize enable_guc_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as part
    of slpc_enable_sanitize function in the next patch. (Sagar) Updated
    slpc option sanitize function call for platforms without GuC 
support.

    This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on kernel
    parameter. Moved sanitization prior to GuC load to use the parameter
    during SLPC state setup during to GuC load. (Sagar)

v6: Commit message update. Rebase.

v7: Moved SLPC option sanitization to intel_uc_sanitize_options.

v8: Clearing SLPC option on GuC load failure. Change moved from later
    patch. (Sagar)

v9: s/enable_slpc/enable_guc_slpc. Rebase w.r.t modparam change.

v10: Rebase. Separate modparam is not needed now that we maintain all
 options in single param enable_guc.

Suggested-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c |  5 +++--
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c    | 23 +++
 drivers/gpu/drm/i915/intel_uc.h    |  6 ++
 4 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c

index 08108ce..40b799b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -150,9 +150,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
 "2=default swing(400mV))");
i915_param_named_unsafe(enable_guc, int, 0400,
-    "Enable GuC load for GuC submission and/or HuC load. "
+    "Enable GuC load for GuC submission and/or HuC load and/or GuC 
SLPC. "

 "Required functionality can be selected using bitmask values. "
-    "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+    "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load, "
+    "4=GuC SLPC)");


Maybe to avoid later surprise, we should explicitly say that:

+    "4=GuC SLPC [requires GuC submission])");


i915_param_named(guc_log_level, int, 0400,
 "GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h

index c963603..2484925 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -32,6 +32,7 @@ struct drm_printer;
#define ENABLE_GUC_SUBMISSION    BIT(0)
 #define ENABLE_GUC_LOAD_HUC    BIT(1)
+#define ENABLE_GUC_SLPC    BIT(2)
#define I915_PARAMS_FOR_EACH(param) \
 param(char *, vbt_firmware, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 1cffaf7..0e4a97f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -56,9 +56,15 @@ static int __get_platform_enable_guc(struct 
drm_i915_private *dev_priv)

 struct intel_uc_fw *huc_fw = _priv->huc.fw;
 int enable_guc = 0;
-    /* Default is to enable GuC/HuC if we know their firmwares */
-    if (intel_uc_fw_is_selected(guc_fw))
+    /*
+ * Default is to enable GuC submission/SLPC/HuC if we know their
+ * firmwares
+ */
+    if (intel_uc_fw_is_selected(guc_fw)) {
 enable_guc |= ENABLE_GUC_SUBMISSION;
+    enable_guc |= ENABLE_GUC_SLPC;
+    }
+
 if (intel_uc_fw_is_selected(huc_fw))
 enable_guc |= ENABLE_GUC_LOAD_HUC;
@@ -110,10 +116,11 @@ static void sanitize_options_early(struct 
drm_i915_private *dev_priv)

 if (i915_modparams.enable_guc < 0)
 i915_modparams.enable_guc = 
__get_platform_enable_guc(dev_priv);

-    DRM_DEBUG_DRIVER("enable

[Intel-gfx] [PATCH v12 16/17] drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces

[Sagar Arun Kamble]

When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic numbers (Nick)
Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

v5: Added SLPC banner to i915_rps_boost_info and keep printing
driver internal values. (Chris)

v6: Commit message update.

v7: Rebase.

v8: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a66507..5d2ac24 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1068,6 +1068,9 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
struct intel_rps *rps = _priv->gt_pm.rps;
int ret = 0;
 
+   if (USES_GUC_SLPC(dev_priv))
+   seq_puts(m, "SLPC Active\n");
+
intel_runtime_pm_get(dev_priv);
 
if (IS_GEN5(dev_priv)) {
@@ -2209,6 +2212,9 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
struct intel_rps *rps = _priv->gt_pm.rps;
struct drm_file *file;
 
+   if (USES_GUC_SLPC(dev_priv))
+   seq_puts(m, "SLPC Active\n");
+
seq_printf(m, "RPS enabled? %d\n", rps->enabled);
seq_printf(m, "GPU busy? %s [%d requests]\n",
   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v12 12/17] drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

Adds debugfs hooks for enabling/disabling each SLPC task.

The enable/disable debugfs files are:
i915_guc_slpc_gtperf, i915_guc_slpc_balancer, and i915_guc_slpc_dcc.

Each of these can take the values: "default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
separate functions to update the task status only in the SLPC
shared memory. Passing dev_priv as parameter.

v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write.
Moved functions to intel_slpc.c. RPM Get/Put added before setting
parameters and sending RESET event explicitly. (Sagar)

v7: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 200 
 1 file changed, 200 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ff90577..d646a04 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2580,6 +2580,203 @@ static const struct file_operations 
i915_guc_log_relay_fops = {
.release = i915_guc_log_relay_release,
 };
 
+static const char *slpc_task_status_stringify(int state)
+{
+   const char *str = NULL;
+
+   switch (state) {
+   case SLPC_PARAM_TASK_DEFAULT:
+   str = "default\n";
+   break;
+
+   case SLPC_PARAM_TASK_ENABLED:
+   str = "enabled\n";
+   break;
+
+   case SLPC_PARAM_TASK_DISABLED:
+   str = "disabled\n";
+   break;
+
+   default:
+   str = "unknown\n";
+   break;
+   }
+
+   return str;
+}
+
+static int slpc_task_status_show(struct seq_file *m,
+u32 enable_id,
+u32 disable_id)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+   const char *status = NULL;
+   u64 val;
+   int ret;
+
+   mutex_lock(>lock);
+   ret = intel_guc_slpc_task_status(slpc, , enable_id, disable_id);
+   mutex_unlock(>lock);
+
+   if (!ret)
+   status = slpc_task_status_stringify(val);
+
+   seq_printf(m, "%s", status);
+
+   return 0;
+}
+
+static int slpc_task_status_write(struct seq_file *m,
+ const char __user *ubuf,
+ size_t len,
+ u32 enable_id,
+ u32 disable_id)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+   int ret = 0;
+   char status[10];
+   u64 val;
+
+   if (len >= sizeof(status))
+   ret = -EINVAL;
+   else if (copy_from_user(status, ubuf, len))
+   ret = -EFAULT;
+   else
+   status[len] = '\0';
+
+   if (ret)
+   return ret;
+
+   if (!strncmp(status, "default", 7))
+   val = SLPC_PARAM_TASK_DEFAULT;
+   else if (!strncmp(status, "enabled", 7))
+   val = SLPC_PARAM_TASK_ENABLED;
+   else if (!strncmp(status, "disabled", 8))
+   val = SLPC_PARAM_TASK_DISABLED;
+   else
+   return -EINVAL;
+
+   mutex_lock(>lock);
+   ret = intel_guc_slpc_task_control(slpc, val, enable_id, disable_id);
+   mutex_unlock(>lock);
+
+   return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+   return slpc_task_status_show(m,
+SLPC_PARAM_TASK_ENABLE_GTPERF,
+SLPC_PARAM_TASK_DISABLE_GTPERF);
+}
+
+static int i915_guc_slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+   struct drm_i915_private *dev_priv = inode->i_private;
+
+   return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t i915_guc_slpc_gtperf_write(struct file *file,
+ const char __user *ubuf,
+  

[Intel-gfx] [PATCH v12 14/17] drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters

[Sagar Arun Kamble]

Add support to set/read parameters and unset the parameters which will
revert them to default SLPC internal values. Explicit SLPC reset is needed
on setting/unsetting some of the parameters.

This patch adds two debugfs interfaces:
1. i915_guc_slpc_params: List of all parameters that Host can configure.
   Currently listing id and description of each.
2. i915_guc_slpc_param_ctl: This allows to change the parameters.
   Syntax is:
   * Update parameter with id  with value :
 echo "write  " > i915_guc_slpc_param_ctl
   * Read parameter with id 
 echo "read " > i915_guc_slpc_param_ctl
 cat i915_guc_slpc_param_ctl
   * Revert parameter with id  to default value
 echo "revert " > i915_guc_slpc_param_ctl.

v2: Moved the SLPC interfaces to i915_debugfs.c. Added error handling to
the range of parameters and parsing. Making use of intel_guc_slpc_enabled
instead of accessing status variable. Optimized token parsing.
(Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and
s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl

v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c| 156 +
 drivers/gpu/drm/i915/intel_guc_slpc.c  |  87 
 drivers/gpu/drm/i915/intel_guc_slpc.h  |  18 
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h |  23 +
 4 files changed, 284 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5c1231f..f90ad52 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2777,6 +2777,160 @@ const struct file_operations i915_guc_slpc_dcc_fops = {
.llseek  = seq_lseek
 };
 
+static int i915_guc_slpc_params_info(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   if (!USES_GUC_SLPC(dev_priv))
+   return -ENODEV;
+
+   intel_guc_slpc_params_print(_priv->guc.slpc, );
+
+   return 0;
+}
+
+static int slpc_param_ctl_show(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+
+   if (!USES_GUC_SLPC(dev_priv))
+   return -ENODEV;
+
+   if (slpc->debug.param_id >= SLPC_MAX_PARAM)
+   return -EINVAL;
+
+   BUILD_BUG_ON(ARRAY_SIZE(slpc_params_desc) != SLPC_MAX_PARAM);
+
+   seq_printf(m, "%s=%u, override=%s\n",
+   slpc_params_desc[slpc->debug.param_id],
+   slpc->debug.param_value,
+   yesno(!!slpc->debug.param_override));
+
+   return 0;
+}
+
+static int slpc_param_ctl_open(struct inode *inode, struct file *file)
+{
+   return single_open(file, slpc_param_ctl_show, inode->i_private);
+}
+
+/*
+ * Parse SLPC parameter control strings: (Similar to Pipe CRC handling)
+ *   command: wsp* op wsp+ param id wsp+ [value] wsp*
+ *   op: "read"/"write"/"revert"
+ *   param id: slpc_param_id
+ *   value: u32 value
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "read 0"   -> read SLPC_PARAM_TASK_ENABLE_GTPERF
+ *  "write 7 500"  -> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to 500MHz
+ *  "revert 7" -> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to
+ *default value.
+ */
+static int slpc_param_ctl_parse(char *buf, size_t len, int *op,
+   u32 *id, u32 *value)
+{
+#define MAX_WORDS 3
+   int n_words;
+   char *words[MAX_WORDS];
+   ssize_t ret;
+
+   n_words = buffer_tokenize(buf, words, MAX_WORDS);
+   if (!(n_words == 3) && !(n_words == 2)) {
+   DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
+MAX_WORDS);
+   return -EINVAL;
+   }
+
+   if (!strcmp(words[0], "read"))
+   *op = READ_OP;
+   else if (!strcmp(words[0], "write"))
+   *op = WRITE_OP;
+   else if (!strcmp(words[0], "revert"))
+   *op = REVERT_OP;
+   else {
+   DRM_DEBUG_DRIVER("unknown operation\n");
+   return -EINVAL;
+   }
+
+   ret = kstrtou32(words[1], 0, id);
+   if (ret)
+   return ret;
+
+   if (n_words == 3) {
+   ret = kstrtou32(words[2], 0, value);

[Intel-gfx] [PATCH v12 11/17] drm/i915/guc/slpc: Add support for sysfs min/max frequency control

[Sagar Arun Kamble]

Update sysfs functions to set SLPC parameters when setting max/min user
frequency limits.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice). Replace
HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris). Changed
intel_slpc_active to guc.slpc.enabled. Carved out SLPC helpers to set
min and max frequencies.

v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
and covered with RPM get/put. Caching SLPC limits post enabling first.

v7: Rebase due to change in the dev_priv->pm.rps structure.

v8: Updated returns from gt_min_freq_mhz_store and gt_max_freq_mhz_store
and i915_min_freq_set and i915_max_freq_set.

v9: Rebase. Debugfs interfaces will be removed hence only updated sysfs.

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 52 +
 drivers/gpu/drm/i915/intel_guc_slpc.c | 86 ++-
 drivers/gpu/drm/i915/intel_guc_slpc.h |  6 +++
 3 files changed, 133 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index c3083fa..d1b4793 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -343,10 +343,20 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct 
device_attribute *attr, char *buf)
 {
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+   u32 freq;
 
-   return snprintf(buf, PAGE_SIZE, "%d\n",
-   intel_gpu_freq(dev_priv,
-  dev_priv->gt_pm.rps.max_freq_softlimit));
+   if (USES_GUC_SLPC(dev_priv)) {
+   mutex_lock(>lock);
+   freq = dev_priv->guc.slpc.max_unslice_freq;
+   mutex_unlock(>lock);
+   } else {
+   mutex_lock(_priv->pcu_lock);
+   freq = dev_priv->gt_pm.rps.max_freq_softlimit;
+   mutex_lock(_priv->pcu_lock);
+   }
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
 }
 
 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -362,12 +372,17 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
if (ret)
return ret;
 
+   val = intel_freq_opcode(dev_priv, val);
+
+   if (USES_GUC_SLPC(dev_priv)) {
+   ret = intel_guc_slpc_max_freq_set(_priv->guc.slpc, val);
+   goto out;
+   }
+
intel_runtime_pm_get(dev_priv);
 
mutex_lock(_priv->pcu_lock);
 
-   val = intel_freq_opcode(dev_priv, val);
-
if (val < rps->min_freq ||
val > rps->max_freq ||
val < rps->min_freq_softlimit) {
@@ -395,16 +410,27 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
intel_runtime_pm_put(dev_priv);
 
+out:
return ret ?: count;
 }
 
 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct 
device_attribute *attr, char *buf)
 {
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+   u32 freq;
 
-   return snprintf(buf, PAGE_SIZE, "%d\n",
-   intel_gpu_freq(dev_priv,
-  dev_priv->gt_pm.rps.min_freq_softlimit));
+   if (USES_GUC_SLPC(dev_priv)) {
+   mutex_lock(>lock);
+   freq = dev_priv->guc.slpc.min_unslice_freq;
+   mutex_unlock(>lock);
+   } else {
+   mutex_lock(_priv->pcu_lock);
+   freq = dev_priv->gt_pm.rps.min_freq_softlimit;
+   mutex_lock(_priv->pcu_lock);
+   }
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
 }
 
 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -420,12 +446,17 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
if (ret)
return ret;
 
+   val = intel_freq_opcode(dev_priv, val);
+
+   if (USES_GUC_SLPC(dev_priv)) {
+   ret = intel_guc_slpc_min_freq_set(_priv->guc.slpc, val);
+   goto out;
+   }
+
intel_runtime_pm_get(dev_priv);
 
mutex_lock(_priv->pcu_lock);
 
-   val = intel_freq_opcode(dev_priv, val);
-
if (val < rps->min_freq ||
val > rps->max_freq

[Intel-gfx] [PATCH v12 15/17] drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

i915_guc_slpc_info shows the contents of SLPC shared data parsed into text
format.

v1: Reformat slpc info (Radek). Squashed query task state info in slpc
info, kunmap before seq_print (Paulo) Return void instead of ignored
return value (Paulo)
Avoid magic numbers and use local variables (Jon Bloomfield). Removed
WARN_ON for checking msb of gtt address of shared gem obj. (Chris)
Moved definition of power plan and power source to earlier patch in
the series. drm/i915/slpc: Allocate/Release/Initialize SLPC shared
data (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
structure. Removed unnecessary checks of vma from i915_slpc_info.
Created helpers for reading the SLPC shared data and string form of
SLPC state. (Sagar)

v6: s/i915_slpc_info/i915_guc_slpc_info. Prepared helpers platform_sku
_to_string, power_plan_to_string and power_source_to_string.
(Michal Wajdeczko)

v7: Moved all SLPC data printing changes to guc_slpc.c and making use of
drm_printer.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  10 ++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 193 ++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   2 +
 3 files changed, 205 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index f90ad52..1a66507 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1053,6 +1053,15 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
NULL, i915_next_seqno_set,
"0x%llx\n");
 
+static int i915_guc_slpc_info(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_guc_slpc *slpc = _priv->guc.slpc;
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   return intel_guc_slpc_info(slpc, );
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5097,6 +5106,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_guc_slpc_params", i915_guc_slpc_params_info, 0},
+   {"i915_guc_slpc_info", i915_guc_slpc_info, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 7bd5e3e..94c6c19 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -487,6 +487,199 @@ static void slpc_get_param(struct intel_guc_slpc *slpc, 
u32 id,
kunmap_atomic(data);
 }
 
+static const char *slpc_platform_sku_stringify(int platform_sku)
+{
+   const char *str = NULL;
+
+   switch (platform_sku) {
+   case SLPC_PLATFORM_SKU_UNDEFINED:
+   str = "undefined";
+   break;
+   case SLPC_PLATFORM_SKU_ULX:
+   str = "ULX";
+   break;
+   case SLPC_PLATFORM_SKU_ULT:
+   str = "ULT";
+   break;
+   case SLPC_PLATFORM_SKU_T:
+   str = "T";
+   break;
+   case SLPC_PLATFORM_SKU_MOBL:
+   str = "Mobile";
+   break;
+   case SLPC_PLATFORM_SKU_DT:
+   str = "DT";
+   break;
+   case SLPC_PLATFORM_SKU_UNKNOWN:
+   default:
+   str = "unknown";
+   break;
+   }
+
+   return str;
+}
+
+static const char *slpc_power_plan_stringify(int power_plan)
+{
+   const char *str = NULL;
+
+   switch (power_plan) {
+   case SLPC_POWER_PLAN_UNDEFINED:
+   str = "undefined";
+   break;
+   case SLPC_POWER_PLAN_BATTERY_SAVER:
+   str = "battery saver";
+   break;
+   case SLPC_POWER_PLAN_BALANCED:
+   str = "balanced";
+   break;
+   case SLPC_POWER_PLAN_PERFORMANCE:
+   str = "p

[Intel-gfx] [PATCH v12 17/17] HAX: drm/i915/guc: Enable GuC

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 2484925..dd2de06 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v12 13/17] drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing

[Sagar Arun Kamble]

Input string parsing used in CRC control parameter parsing is generic and
can be reused for other debugfs interfaces. We plan to use this in the
next patch for SLPC debugfs control. Hence name it as buffer_tokenize
instead of tying to display_crc. Also fix the function desciption for CRC
control parsing that was misplaced at tokenize function.

v2: Moved buffer_tokenize to i915_debugfs.c (Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Tomeu Vizoso <tomeu.viz...@collabora.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 31 +++
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_pipe_crc.c | 57 ---
 3 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d646a04..5c1231f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5158,3 +5158,34 @@ int i915_debugfs_connector_add(struct drm_connector 
*connector)
 
return 0;
 }
+
+int buffer_tokenize(char *buf, char *words[], int max_words)
+{
+   int n_words = 0;
+
+   while (*buf) {
+   char *end;
+
+   /* skip leading white space */
+   buf = skip_spaces(buf);
+   if (!*buf)
+   break;  /* end of buffer */
+
+   /* find end of word */
+   for (end = buf; *end && !isspace(*end); end++)
+   ;
+
+   if (n_words == max_words) {
+   DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
+max_words);
+   return -EINVAL; /* ran out of words[] before bytes */
+   }
+
+   if (*end)
+   *end++ = '\0';
+   words[n_words++] = buf;
+   buf = end;
+   }
+
+   return n_words;
+}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d17e778..7473d34 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3326,6 +3326,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private 
*dev_priv, u32 size,
 int i915_debugfs_register(struct drm_i915_private *dev_priv);
 int i915_debugfs_connector_add(struct drm_connector *connector);
 void intel_display_crc_init(struct drm_i915_private *dev_priv);
+int buffer_tokenize(char *buf, char *words[], int max_words);
 #else
 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) 
{return 0;}
 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c 
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 4f367c1..6519526 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -710,49 +710,6 @@ static int pipe_crc_set_source(struct drm_i915_private 
*dev_priv,
return ret;
 }
 
-/*
- * Parse pipe CRC command strings:
- *   command: wsp* object wsp+ name wsp+ source wsp*
- *   object: 'pipe'
- *   name: (A | B | C)
- *   source: (none | plane1 | plane2 | pf)
- *   wsp: (#0x20 | #0x9 | #0xA)+
- *
- * eg.:
- *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
- *  "pipe A none"->  Stop CRC
- */
-static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
-{
-   int n_words = 0;
-
-   while (*buf) {
-   char *end;
-
-   /* skip leading white space */
-   buf = skip_spaces(buf);
-   if (!*buf)
-   break;  /* end of buffer */
-
-   /* find end of word */
-   for (end = buf; *end && !isspace(*end); end++)
-   ;
-
-   if (n_words == max_words) {
-   DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
-max_words);
-   return -EINVAL; /* ran out of words[] before bytes */
-   }
-
-   if (*end)
-   *end++ = '\0';
-   words[n_words++] = buf;
-   buf = end;
-   }
-
-   return n_words;
-}
-
 enum intel_pipe_crc_object {
PIPE_CRC_OBJECT_PIPE,
 };
@@ -807,6 +764,18 @@ display_crc_ctl_parse_source(const char *buf, enum 
intel_pipe_crc_source *s)
return -EINVAL;
 }
 
+/*
+ * Parse pipe CRC command strings:
+ *   command: wsp* object wsp+ name wsp+ source wsp*
+ *   object: 'pipe'
+ *   name: (A | B | C)
+ *   source: (none | plane1 | plane2 | pf)
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
+ *  "pipe A none"->  St

[Intel-gfx] [PATCH v12 09/17] drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED

[Sagar Arun Kamble]

On engine reset, SLPC needs to be notified for it to clear metrics/stats.
This is done by sending GUC_SLPC_EVENT_RESET with a flag
GUC_SLPC_RESET_FLAG_TDR_OCCURRED.

v2: Full GPU reset in i915 triggers reload of GuC and SLPC reset happens
along that path. Hence only handling engine reset.

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c   |  3 +++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 36 +++
 drivers/gpu/drm/i915/intel_guc_slpc.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c   |  5 +
 drivers/gpu/drm/i915/intel_uc.h   |  1 +
 5 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cc7dd85..726391c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3020,6 +3020,9 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
wake_up_bit(_priv->gpu_error.flags,
I915_RESET_ENGINE + engine->id);
}
+
+   if (!engine_mask)
+   intel_uc_handle_engine_reset(dev_priv);
}
 
if (!engine_mask)
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 7f75d218..bdafbaa 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -390,6 +390,20 @@ static bool slpc_stopped(struct intel_guc_slpc *slpc)
return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
 }
 
+static void host2guc_slpc_tdr_reset(struct intel_guc_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+   struct slpc_event_input data = {0};
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 3);
+   data.args[0] = shared_data_gtt_offset;
+   data.args[1] = 0;
+   data.args[2] = SLPC_RESET_FLAG_TDR_OCCURRED;
+
+   slpc_send(slpc, , 5);
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
@@ -471,6 +485,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
 }
 
 /**
+ * intel_guc_slpc_handle_engine_reset() - Notify SLPC about engine reset.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * On engine reset, SLPC needs to be notified for it to clear metrics/stats.
+ * This function notifies by invoking SLPC_EVENT_RESET with a flag
+ * SLPC_RESET_FLAG_TDR_OCCURRED.
+ */
+void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc)
+{
+   mutex_lock(>lock);
+
+   host2guc_slpc_tdr_reset(slpc);
+
+   /* Check whether SLPC is running */
+   if (wait_for(slpc_running(slpc), 5))
+   DRM_ERROR("SLPC not enabled! State = %s\n",
+ slpc_get_state(slpc));
+
+   mutex_unlock(>lock);
+}
+
+/**
  * intel_guc_slpc_disable() - Stop SLPC tasks.
  * @slpc: pointer to intel_guc_slpc.
  *
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 87dac07..75f0b5d 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -16,6 +16,7 @@ struct intel_guc_slpc {
 
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
+void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_disable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ece6687..c050444 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -475,6 +475,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
+void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv)
+{
+   intel_guc_slpc_handle_engine_reset(_priv->guc.slpc);
+}
+
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 76139d3..1d67ad3 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -35,6 +35,7 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv);
 void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
 void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
+void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv);
 voi

[Intel-gfx] [PATCH v12 07/17] drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks

[Sagar Arun Kamble]

Host to GuC actions for SLPC receive additional data as output through
scratch registers currently. intel_guc_send_and_receive handles this.
We need to define SLPC specific Host to GuC send action (slpc_send) as
wrapper on top of it to process the SLPC status that is received in
SOFT_SCRATCH(1).

Send host2guc SLPC reset event to GuC post GuC load for enabling SLPC.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done by waiting for maximum 5ms.
SLPC reset event also needs to be sent when parameters in shared data
are updated.

v1: Extract host2guc_slpc to handle slpc status code and style changes.
(Paulo). Removed WARN_ON for checking msb of gtt address of shared
 gem obj. (Chris). host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

v5: Updated patch as host2guc_slpc is moved to earlier patch. SLPC
activation status message put after checking the state from shared
data during intel_init_gt_powersave.

v6: Added definition of host2guc_slpc and clflush the shared data only
for required size. Setting state to NOT_RUNNING before sending RESET
event. Output data for SLPC actions is to be retrieved during
intel_guc_send with lock protection so created wrapper
__intel_guc_send that outputs GuC output data if needed. Clearing
pm_rps_events on confirming SLPC RUNNING status so that even if
host touches any of the PM registers by mistake it should not have
any effect. (Sagar)

v7: Added save/restore_default_rps as Uncore sanitize will clear the
RP_CONTROL setup by BIOS. s/i915_ggtt_offset/guc_ggtt_offset.

v8: Added support for handling TDR based SLPC reset. Added functions
host2guc_slpc_tdr_reset, intel_slpc_reset_prepare and
intel_slpc_tdr_reset to handle TDR based SLPC reset.

v9: Moved TDR support to later patch. Removed intel_slpc_get_status
and waiting for maximum of 5ms for SLPC state to turn RUNNING instead
of hiding the latency across uc_init_hw and init_gt_powersave.
s/if..else/switch..case in intel_guc_slpc_get_state_str. Removed SLPC
sanitization from init_gt_powersave. (Michal Wajdeczko)

v10: Rebase.

v11: Rebase. Created slpc_send func as wrapper on guc_send_and_receive.

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 239 ++
 1 file changed, 239 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 974a3c0..bc2c717 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -163,6 +163,211 @@ static void slpc_shared_data_init(struct intel_guc_slpc 
*slpc)
kunmap_atomic(data);
 }
 
+static const char *slpc_status_stringify(int status)
+{
+   const char *str = NULL;
+
+   switch(status) {
+   case SLPC_STATUS_OK:
+   str = "Ok";
+   break;
+   case SLPC_STATUS_ERROR:
+   str = "Error";
+   break;
+   case SLPC_STATUS_ILLEGAL_COMMAND:
+   str = "Illegal command";
+   break;
+   case SLPC_STATUS_INVALID_ARGS:
+   str = "Invalid args";
+   break;
+   case SLPC_STATUS_INVALID_PARAMS:
+   str = "Invalid params";
+   break;
+   case SLPC_STATUS_INVALID_DATA:
+   str = "Invalid data";
+   break;
+   case SLPC_STATUS_OUT_OF_RANGE:
+   str = "Out of range";
+   break;
+   case SLPC_STATUS_NOT_SUPPORTED:
+   str = "Not supported";
+   break;
+   case SLPC_STATUS_NOT_IMPLEMENTED:
+   str = "Not implemented";
+   break;
+   case SLPC_STATUS_NO_DATA:
+   str = "No data";
+   break;
+   case SLPC_STATUS_EVENT_NOT_REGISTERED:
+   str = "Event not registered";
+   break;
+   case SLPC_STATUS_REGISTER_LOCKED:
+   str = "Register locked";
+   break;
+   case SLPC_STATUS_TEMPORARILY_UNAVAILABLE:
+   str = "Temporarily unavailable";
+   break;
+   case SLPC_STATUS_VALUE_ALREADY_SET:
+   str = "Value already set";
+   break;
+   case SLPC_STATUS_VALUE_ALREADY_UNSET:
+   

[Intel-gfx] [PATCH v12 10/17] drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions

[Sagar Arun Kamble]

SLPC behavior can be changed through set of parameters. These parameters
can be updated and queried from i915 though Host to GuC SLPC events. This
patch adds parameter update events for setting/unsetting/getting params.
Setting parameter leads to overridding of default parameter value. Unset
leads to restoring of default value by communicating with GuC SLPC through
parameter updates in the shared data.
i915 can only query/get parameters that it overrides, so getting parameter
value is done by only reading from the shared data.

SLPC has various tasks, GTPERF, BALANCER and DCC. These can be controlled
through pair of GuC SLPC parameters. Enable/disable of these tasks require
combined update to both parameters hence new actions are added to control
and query the status of tasks.

v1: Use host2guc_slpc. Update slcp_param_id enum values for SLPC 2015.2.4
Return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated input structure to host2guc_slpc. Added functions to update
only parameters in the SLPC shared memory. This will allow to setup
shared data with all parameters and send single event to SLPC take
them into effect. Commit message update. (Sagar)

v6: Rearranged helpers to use them in slpc_shared_data_init. Added defn.
of SLPC_KMD_MAX_PARAM.

v7: Added definition of host2guc_slpc with rearrangement of patches. Added
task control/status functions.

v8: Rebase w.r.t s/intel_guc_send/intel_guc_send_mmio.

v9: Created intel_guc_slpc_send_mmio with SLPC specific H2G action send
function. Rebase. Defined slpc_statuslist and using the same in
intel_guc_slpc_send_mmio. (Michal Wajdeczko)

v10: Rebase. Added kernel documentation to the task control functions.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 173 ++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   5 +
 2 files changed, 178 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index bdafbaa..011e442 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -404,6 +404,179 @@ static void host2guc_slpc_tdr_reset(struct intel_guc_slpc 
*slpc)
slpc_send(slpc, , 5);
 }
 
+static void host2guc_slpc_set_param(struct intel_guc_slpc *slpc,
+   u32 id, u32 value)
+{
+   struct slpc_event_input data = {0};
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+   data.args[0] = id;
+   data.args[1] = value;
+
+   slpc_send(slpc, , 4);
+}
+
+static void host2guc_slpc_unset_param(struct intel_guc_slpc *slpc,
+ u32 id)
+{
+   struct slpc_event_input data = {0};
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+   data.args[0] = id;
+
+   slpc_send(slpc, , 3);
+}
+
+static void slpc_set_param(struct intel_guc_slpc *slpc, u32 id, u32 value)
+{
+   struct slpc_shared_data *data = NULL;
+   struct page *page;
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+   GEM_BUG_ON(!slpc->vma);
+
+   lockdep_assert_held(>lock);
+
+   page = i915_vma_first_page(slpc->vma);
+   data = kmap_atomic(page);
+   slpc_mem_set_param(data, id, value);
+   kunmap_atomic(data);
+
+   host2guc_slpc_set_param(slpc, id, value);
+}
+
+static void slpc_unset_param(struct intel_guc_slpc *slpc, u32 id)
+{
+   struct slpc_shared_data *data = NULL;
+   struct page *page;
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+   GEM_BUG_ON(!slpc->vma);
+
+   lockdep_assert_held(>lock);
+
+   page = i915_vma_first_page(slpc->vma);
+   data = kmap_atomic(page);
+   slpc_mem_unset_param(data, id);
+   kunmap_atomic(data);
+
+   host2guc_slpc_unset_param(slpc, id);
+}
+
+static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id,
+  int *overriding, u32 *value)
+{
+   struct slpc_shared_data *data = NULL;
+   struct page *page;
+   u32 bits;
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+   GEM_BUG_ON(!slpc->vma);
+
+   lockdep_assert_held(>lock);
+
+   page = i915_vma_first_page(slpc->vma);
+   data = kmap_atomic(page);
+   if (overriding) {
+   bits = data->override_params_set_bits[id >> 5];
+   *overriding = (0 != (bits & (1 << (id % 32;
+   }
+  

[Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

Communication with SLPC is via Host to GuC interrupt through shared data
and parameters. This patch defines the structure of shared data,
parameters, data structure to be passed as input and received as output
from SLPC. This patch also defines the events to be sent as input and
status values output by GuC on processing SLPC events.
SLPC shared data has details of SKU type, Slice count, IA Perf MSR values,
SLPC state, Power source/plan, SLPC tasks status. Parameters allow
overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

v9: Removed struct slpc_param, slpc_paramlist and corresponding defines.
Will be added in later patches where they are used.

v10: Rebase. Prepared separate header for SLPC firmware interface.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.h  |   2 +
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h | 211 +
 2 files changed, 213 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 66c76fe..81250c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -6,6 +6,8 @@
 #ifndef _INTEL_GUC_SLPC_H_
 #define _INTEL_GUC_SLPC_H_
 
+#include 
+
 struct intel_guc_slpc {
 };
 
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
new file mode 100644
index 000..9400af4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h
@@ -0,0 +1,211 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+#ifndef _INTEL_GUC_SLPC_FWIF_H_
+#define _INTEL_GUC_SLPC_FWIF_H_
+
+#include 
+
+enum slpc_status {
+   SLPC_STATUS_OK = 0,
+   SLPC_STATUS_ERROR = 1,
+   SLPC_STATUS_ILLEGAL_COMMAND = 2,
+   SLPC_STATUS_INVALID_ARGS = 3,
+   SLPC_STATUS_INVALID_PARAMS = 4,
+   SLPC_STATUS_INVALID_DATA = 5,
+   SLPC_STATUS_OUT_OF_RANGE = 6,
+   SLPC_STATUS_NOT_SUPPORTED = 7,
+   SLPC_STATUS_NOT_IMPLEMENTED = 8,
+   SLPC_STATUS_NO_DATA = 9,
+   SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+   SLPC_STATUS_REGISTER_LOCKED = 11,
+   SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+   SLPC_STATUS_VALUE_ALREADY_SET = 13,
+   SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+   SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+   SLPC_STATUS_MEMIO_ERROR = 16,
+   SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+   SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+   SLPC_STATUS_NO_EVENT_QUEUED = 19,
+   SLPC_STATUS_OUT_OF_SPACE = 20,
+   SLPC_STATUS_TIMEOUT = 21,
+   SLPC_STATUS_NO_LOCK = 22,
+   SLPC_STATUS_MAX
+};
+
+enum slpc_event_id {
+   SLPC_EVENT_RESET = 0,
+   SLPC_EVENT_SHUTDOWN = 1,
+   SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+   SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+   SLPC_EVENT_FLIP_COMPLETE = 4,
+   SLPC_EVENT_QUERY_TASK_STATE = 5,
+   SLPC_EVENT_PARAMETER_SET = 6,
+   SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+enum slpc_param_id {
+   SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+   SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+   SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+   SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+   SLPC_PARAM_TASK_ENABLE_DCC = 4,
+   SLPC_PARAM_TASK_DISABLE_DCC = 5,
+   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+   SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+   SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+   SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+   SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+   SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+   SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+   SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+   SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+   SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+   SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,

[Intel-gfx] [PATCH v12 08/17] drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

Send SLPC shutdown event during uc_fini_hw or prior to enabling SLPC
done while communicating updated parameters in shared data.

v1: Return void instead of ignored error code (Paulo). Removed WARN_ON
for checking msb of gtt address of shared gem obj. (Chris)
Added SLPC state update during disable, suspend and reset. Changed
semantics of reset. It is supposed to just disable. (Sagar)

v2-v4: Rebase.

v5: Updated the input data structure. (Sagar)

v6: Rebase.

v7: s/i915_ggtt_offset/guc_ggtt_offset.

v8: Updated the status check post disabling to wait for 20us. (Sagar)

v9: Updated the status check wait time to 5ms for safe margin as it is
handled similar to reset by SLPC. s/slpc_disabled/slpc_stopped

v10: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_slpc.c | 38 +++
 drivers/gpu/drm/i915/intel_uc.c   |  6 +++---
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index bc2c717..7f75d218 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -368,6 +368,28 @@ static bool slpc_running(struct intel_guc_slpc *slpc)
return (data.global_state == SLPC_GLOBAL_STATE_RUNNING);
 }
 
+static void host2guc_slpc_shutdown(struct intel_guc_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+   struct slpc_event_input data = {0};
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+   data.args[0] = shared_data_gtt_offset;
+   data.args[1] = 0;
+
+   slpc_send(slpc, , 4);
+}
+
+static bool slpc_stopped(struct intel_guc_slpc *slpc)
+{
+   struct slpc_shared_data data;
+
+   slpc_read_shared_data(slpc, );
+
+   return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
+}
+
 /**
  * intel_guc_slpc_init() - Initialize the SLPC shared data structure.
  * @slpc: pointer to intel_guc_slpc.
@@ -448,8 +470,24 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
return 0;
 }
 
+/**
+ * intel_guc_slpc_disable() - Stop SLPC tasks.
+ * @slpc: pointer to intel_guc_slpc.
+ *
+ * This function will stop GuC SLPC tasks by sending Host to GuC action.
+ */
 void intel_guc_slpc_disable(struct intel_guc_slpc *slpc)
 {
+   mutex_lock(>lock);
+
+   host2guc_slpc_shutdown(slpc);
+
+   /* Ensure SLPC is not running */
+   if (wait_for(slpc_stopped(slpc), 5))
+   DRM_ERROR("SLPC not disabled! State = %s\n",
+ slpc_get_state(slpc));
+
+   mutex_unlock(>lock);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 5bf33c8..ece6687 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -359,6 +359,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
 
GEM_BUG_ON(!HAS_GUC(i915));
 
+   if (USES_GUC_SLPC(dev_priv))
+   intel_guc_slpc_disable(>slpc);
+
guc_disable_communication(guc);
 
intel_huc_sanitize(huc);
@@ -484,9 +487,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (USES_GUC_SUBMISSION(dev_priv))
intel_guc_submission_disable(guc);
 
-   if (USES_GUC_SLPC(dev_priv))
-   intel_guc_slpc_disable(>slpc);
-
guc_disable_communication(guc);
 }
 
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

GuC is currently being used for submission and HuC authentication.
Choices can be configured through enable_guc modparam. GuC SLPC is GT
Power and Performance management feature in GuC. Add another option to
enable_guc modparam to control SLPC.

v1: Add early call to sanitize enable_guc_slpc in intel_guc_ucode_init
Remove sanitize enable_guc_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as part
of slpc_enable_sanitize function in the next patch. (Sagar) Updated
slpc option sanitize function call for platforms without GuC support.
This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on kernel
parameter. Moved sanitization prior to GuC load to use the parameter
during SLPC state setup during to GuC load. (Sagar)

v6: Commit message update. Rebase.

v7: Moved SLPC option sanitization to intel_uc_sanitize_options.

v8: Clearing SLPC option on GuC load failure. Change moved from later
patch. (Sagar)

v9: s/enable_slpc/enable_guc_slpc. Rebase w.r.t modparam change.

v10: Rebase. Separate modparam is not needed now that we maintain all
 options in single param enable_guc.

Suggested-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c |  5 +++--
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c| 23 +++
 drivers/gpu/drm/i915/intel_uc.h|  6 ++
 4 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..40b799b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -150,9 +150,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
"2=default swing(400mV))");
 
 i915_param_named_unsafe(enable_guc, int, 0400,
-   "Enable GuC load for GuC submission and/or HuC load. "
+   "Enable GuC load for GuC submission and/or HuC load and/or GuC SLPC. "
"Required functionality can be selected using bitmask values. "
-   "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+   "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load, "
+   "4=GuC SLPC)");
 
 i915_param_named(guc_log_level, int, 0400,
"GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..2484925 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -32,6 +32,7 @@ struct drm_printer;
 
 #define ENABLE_GUC_SUBMISSION  BIT(0)
 #define ENABLE_GUC_LOAD_HUCBIT(1)
+#define ENABLE_GUC_SLPCBIT(2)
 
 #define I915_PARAMS_FOR_EACH(param) \
param(char *, vbt_firmware, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..0e4a97f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -56,9 +56,15 @@ static int __get_platform_enable_guc(struct drm_i915_private 
*dev_priv)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
int enable_guc = 0;
 
-   /* Default is to enable GuC/HuC if we know their firmwares */
-   if (intel_uc_fw_is_selected(guc_fw))
+   /*
+* Default is to enable GuC submission/SLPC/HuC if we know their
+* firmwares
+*/
+   if (intel_uc_fw_is_selected(guc_fw)) {
enable_guc |= ENABLE_GUC_SUBMISSION;
+   enable_guc |= ENABLE_GUC_SLPC;
+   }
+
if (intel_uc_fw_is_selected(huc_fw))
enable_guc |= ENABLE_GUC_LOAD_HUC;
 
@@ -110,10 +116,11 @@ static void sanitize_options_early(struct 
drm_i915_private *dev_priv)
if (i915_modparams.enable_guc < 0)
i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
 
-   DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
+   DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s slpc:%s)\n",
 i915_modparams.enable_guc,
 yesno(intel_uc_is_usin

[Intel-gfx] [PATCH v12 03/17] drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers

[Sagar Arun Kamble]

SLPC operates based on parameters setup in shared data between i915 and
GuC SLPC. This is to be created/initialized in intel_guc_slpc_init. From
there onwards i915 can control the SLPC operations by enabling, disabling
complete SLPC or changing SLPC parameters. During cleanup, SLPC shared
data has to be freed.

v1: Return void instead of ignored error code. Replace HAS_SLPC() use with
intel_slpc_enabled()/ intel_slpc_active() (Paulo)
Enable/disable RC6 in SLPC flows (Sagar)
Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
"drm/i915/bxt: Explicitly clear the Turbo control register"
Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
Performance drop with SLPC was happening as ring frequency table was
not programmed when SLPC was enabled. This patch programs ring
frequency table with SLPC. Initial reset of SLPC is based on kernel
parameter as planning to add slpc state in intel_slpc_active. Cleanup
is also based on kernel parameter as SLPC gets disabled in
disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
(Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
that are based on SLPC active status in GuC. State setup/cleanup needed
for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
init and enabling to GuC enable path as SLPC in GuC can start doing the
setup post GuC init. Commit message update. (Sagar)

v6: Rearranged function definitions.

v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
update.

v8: Changed parameters for SLPC functions to struct intel_slpc*.

v9: Reinstated intel_slpc_active and intel_slpc_enabled as they are more
meaningful.

v10: Rebase changes due to creation of intel_guc.h. Updates in
 intel_guc_cleanup w.r.t slpc cleanup.

v11: s/intel_slpc/intel_guc_slpc. Adjusted place for slpc struct inside
 guc struct. (Michal Wajdeczko)
 Updated comment about intel_slpc_enable as we plan to not defer the
 SLPC status check on enabling later and will have to wait for SLPC
 status as part of intel_slpc_enable itself.
 Prepared guc_slpc_initialized and guc_slpc_enabled to track state
 of SLPC initialization and enabling.

v12: s/guc_slpc_cleanup/guc_slpc_fini. Updated SLPC flows w.r.t uC flows.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/intel_guc.h  |  2 ++
 drivers/gpu/drm/i915/intel_guc_slpc.c | 25 +
 drivers/gpu/drm/i915/intel_guc_slpc.h | 17 +
 drivers/gpu/drm/i915/intel_uc.c   | 30 +-
 5 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0c79c19..499cb89 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -90,6 +90,7 @@ i915-y += intel_uc.o \
  intel_guc_ct.o \
  intel_guc_fw.o \
  intel_guc_log.o \
+ intel_guc_slpc.o \
  intel_guc_submission.o \
  intel_huc.o \
  intel_huc_fw.o
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f1265e1..2d2451a 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
 #include "intel_guc_ct.h"
 #include "intel_guc_log.h"
 #include "intel_guc_reg.h"
+#include "intel_guc_slpc.h"
 #include "intel_uc_fw.h"
 #include "i915_vma.h"
 
@@ -48,6 +49,7 @@ struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
struct intel_guc_ct ct;
+   struct intel_guc_slpc slpc;
 
/* Offset where Non-WOPCM memory starts. */
u32 ggtt_pin_bias;
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
new file mode 100644
index 000..63f100c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2015-2018 Intel Corporation
+ */
+
+#include "intel_guc_slpc.h"
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
+{
+   r

[Intel-gfx] [PATCH v12 02/17] drm/i915/guc/slpc: Disable host RPS

[Sagar Arun Kamble]

On platforms with GuC SLPC enabled, we need to ensure Host RPS functions
don't update HW RPS state that will be controlled by GuC SLPC then.
Host RPS functions are now gated by either USES_GUC_SLPC() or rps->enabled
checks. If SLPC is enabled following functions will be bypassed
  1. gpu_ips_init
  2. intel_enable|disable_rps
  3. rps portion of sanitize_gt_powersave

gen6_rps_irq_handler, rps_work, gen6_set_rps should not get invoked hence
GEM_BUG_ON(USES_GUC_SLPC()) is added in those functions.
We continue to use the state setup by intel_init_gt_powersave as i915 will
be configuring min/max frequency limits.

Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/i915_irq.c   | 18 --
 drivers/gpu/drm/i915/i915_sysfs.c |  5 +++--
 drivers/gpu/drm/i915/intel_pm.c   | 26 +-
 4 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 800230b..5176801 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2599,6 +2599,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
 #define USES_GUC_SUBMISSION(dev_priv)  intel_uc_is_using_guc_submission()
 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
+#define USES_GUC_SLPC(dev_priv)intel_uc_is_using_guc_slpc()
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 
((dev_priv)->info.has_resource_streamer)
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27aee25..cc7dd85 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1192,6 +1192,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
int new_delay, adj, min, max;
u32 pm_iir = 0;
 
+   GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
spin_lock_irq(_priv->irq_lock);
if (rps->interrupts_enabled) {
pm_iir = fetch_and_zero(>pm_iir);
@@ -1742,6 +1744,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private 
*dev_priv, u32 pm_iir)
struct intel_rps *rps = _priv->gt_pm.rps;
 
if (pm_iir & dev_priv->pm_rps_events) {
+   GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
spin_lock(_priv->irq_lock);
gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
if (rps->interrupts_enabled) {
@@ -4256,12 +4260,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GUC_SCHED(dev_priv))
dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
 
-   /* Let's track the enabled rps events */
-   if (IS_VALLEYVIEW(dev_priv))
-   /* WaGsvRC0ResidencyMethod:vlv */
-   dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
-   else
-   dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+   if (!USES_GUC_SLPC(dev_priv)) {
+   /* Let's track the enabled rps events */
+   if (IS_VALLEYVIEW(dev_priv))
+   /* WaGsvRC0ResidencyMethod:vlv */
+   dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+   else
+   dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
+   }
 
rps->pm_intrmsk_mbz = 0;
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6b..c3083fa 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -322,9 +322,10 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
rps->boost_freq = val;
boost = atomic_read(>num_waiters);
}
-   mutex_unlock(_priv->pcu_lock);
-   if (boost)
+
+   if (boost && rps->enabled)
schedule_work(>work);
+   mutex_unlock(_priv->pcu_lock);
 
return count;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19e82aa..51bc147e9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6215,6 +6215,8 @@ static int gen6_set_rps(struct drm_i915_private 
*dev_priv, u8 val)
 {
struct intel_rps *rps = _priv->gt_pm.rps;
 
+   GEM_BUG_ON(USES_GUC_SLPC(dev_priv));
+
/* min/max delay may still have been modified so be sure to
 * write the limits value.
 */
@@ -6310,6 +6312,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
struct intel_r

[Intel-gfx] [PATCH v12 06/17] drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data

[Sagar Arun Kamble]

Populate SLPC shared data with required default values for slice count,
power source/plan, IA perf MSRs.

v1: Update for SLPC interface version 2015.2.4. intel_slpc_active()
returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling fixes (Sagar and Nick Hoath). Added WARN for checking if
upper 32bits of GTT offset of shared object are zero. (Chris)
Updated commit message and moved POWER_PLAN and POWER_SOURCE defn.
from later patch. (Akash)
Add struct_mutex locking while allocating/releasing slpc shared
object. This was caught by CI BAT. Adding SLPC state variable to
determine if it is active as it not just dependent on shared data
setup. Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes.(David)
Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).

v5: SLPC vma map changes and removed explicit type conversions.(Chris).
s/freq_unslice_max|min/unslice__max|min_freq.

v6: Commit message update. s/msr_value/val for reuse later.

v7: Set default values for tasks and min frequency parameters. Moved init
with allocation of data so that post GuC load earlier params persist.

v8: Added check for SLPC status during cleanup of shared data. SLPC
disabling is asynchronous and should complete within 10us.

v9: Enabling Balancer task in SLPC.

v10: Rebase.

v11: Rebase. Added lock specific to SLPC.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |   5 +
 drivers/gpu/drm/i915/intel_guc_slpc.c | 204 ++
 drivers/gpu/drm/i915/intel_guc_slpc.h |   3 +
 3 files changed, 212 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5176801..d17e778 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2416,6 +2416,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
+#define IS_ULX_SKU(dev_priv)   (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv))
+#define IS_ULT_SKU(dev_priv)   (IS_SKL_ULT(dev_priv) || \
+IS_KBL_ULT(dev_priv) || \
+IS_CFL_ULT(dev_priv))
+
 #define SKL_REVID_A0   0x0
 #define SKL_REVID_B0   0x1
 #define SKL_REVID_C0   0x2
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 63f100c..974a3c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -4,10 +4,203 @@
  * Copyright © 2015-2018 Intel Corporation
  */
 
+#include 
+
+#include "i915_drv.h"
 #include "intel_guc_slpc.h"
 
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+   return container_of(slpc, struct intel_guc, slpc);
+}
+
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+   enum slpc_platform_sku platform_sku;
+
+   if (IS_ULX_SKU(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULX;
+   else if (IS_ULT_SKU(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULT;
+   else
+   platform_sku = SLPC_PLATFORM_SKU_DT;
+
+   WARN_ON(platform_sku > 0xFF);
+
+   return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+   unsigned int slice_count = 1;
+
+   if (IS_SKYLAKE(dev_priv))
+   slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+   return slice_count;
+}
+
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+  u32 id,
+  u32 value)
+{
+   data->override_params_set_bits[id >> 5] |= (1 << (id % 32));
+   data->override_params_values[id] = value;
+}
+
+static void slpc_mem_unset_param(struct slpc_shared_data *data,
+u32 id)
+{
+   data->override_params_set_bits[id >> 5] &= (~(1 << (id % 32)));
+   data->override_params_values[id] = 0;
+}
+
+static int slpc_mem_task_control(struct slpc_shared_data *data,
+u64 val, u32 enable_id, u32 disable_id)
+{
+   int ret = 0;
+
+   if (val == SLPC_PARAM_TASK_DEFAULT) {
+   /* set default */
+ 

[Intel-gfx] [PATCH v12 04/17] drm/i915/guc/slpc: Enable SLPC in GuC load control params

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

If SLPC is to enabled, then set GUC_CTL_ENABLE_SLPC flag in GuC control
param GUC_CTL_FEATURE word during GuC load. This is required for early
SLPC init in GuC init path. SLPC gets enabled fully on sending this flag
during GuC load and on doing SLPC reset through Host to GuC action.

v1: Use intel_slpc_enabled() (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)

v6: Changed i915.enable_slpc to intel_slpc_enabled(). (Sagar)

v7: Rebase.

v8: Rebase.

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a00a59a..c8d3ffb 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -272,6 +272,9 @@ void intel_guc_init_params(struct intel_guc *guc)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
 
+   if (USES_GUC_SLPC(dev_priv))
+   params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
params[GUC_CTL_DEBUG] = get_log_control_flags();
-- 
2.7.4

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[Intel-gfx] [PATCH v12 00/17] Add support for GuC-based SLPC

[Sagar Arun Kamble]

l.com>
Cc: Jeff McGee <jeff.mc...@intel.com>
Tested-by: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>

Sagar Arun Kamble (12):
  drm/i915/guc/slpc: Disable host RPS
  drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers
  drm/i915/guc/slpc: Add SLPC communication interfaces
  drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data
  drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks
  drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED
  drm/i915/guc/slpc: Add parameter set/unset/get, task control/status
functions
  drm/i915/guc/slpc: Add support for sysfs min/max frequency control
  drm/i915/debugfs: Create generic string tokenize function and update
CRC control parsing
  drm/i915/guc/slpc: Add debugfs support to read/write/revert the
parameters
  drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces
  HAX: drm/i915/guc: Enable GuC

Tom O'Rourke (5):
  drm/i915/guc/slpc: Add SLPC control to enable_guc modparam
  drm/i915/guc/slpc: Enable SLPC in GuC load control params
  drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks
  drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks
  drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs

 drivers/gpu/drm/i915/Makefile  |1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  403 +++
 drivers/gpu/drm/i915/i915_drv.h|7 +
 drivers/gpu/drm/i915/i915_irq.c|   21 +-
 drivers/gpu/drm/i915/i915_params.c |5 +-
 drivers/gpu/drm/i915/i915_params.h |3 +-
 drivers/gpu/drm/i915/i915_sysfs.c  |   57 +-
 drivers/gpu/drm/i915/intel_guc.c   |3 +
 drivers/gpu/drm/i915/intel_guc.h   |2 +
 drivers/gpu/drm/i915/intel_guc_slpc.c  | 1079 
 drivers/gpu/drm/i915/intel_guc_slpc.h  |   54 ++
 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h |  234 ++
 drivers/gpu/drm/i915/intel_pipe_crc.c  |   57 +-
 drivers/gpu/drm/i915/intel_pm.c|   26 +-
 drivers/gpu/drm/i915/intel_uc.c|   58 +-
 drivers/gpu/drm/i915/intel_uc.h|7 +
 16 files changed, 1946 insertions(+), 71 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc.h
 create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h

-- 
2.7.4

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Re: [Intel-gfx] [PATCH v5 8/8] HAX: Enable GuC for CI

[Sagar Arun Kamble]

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:

v2: except running with HYPERVISOR

Signed-off-by: Michal Wajdeczko 
---
  drivers/gpu/drm/i915/i915_params.h | 2 +-
  drivers/gpu/drm/i915/intel_uc.c| 2 ++
  2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index fec5514..bbb2c36 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private 
*i915)
enable_guc |= ENABLE_GUC_LOAD_HUC;
  
  	/* Any platform specific fine-tuning can be done here */

+   if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+   enable_guc = 0;
  

This is not needed now that GuC logging is fixed.

return enable_guc;
  }


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v5 5/8] drm/i915/uc: Use correct error code for GuC initialization failure

[Sagar Arun Kamble]

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-EIO).

Unfortunately since commit 121981fafe69 ("drm/i915/guc: Combine
enable_guc_loading|submission modparams") we stopped using that
error code to avoid unwanted fallback to execlist submission mode.

In result any GuC initialization failure was treated as non-recoverable
error leading to driver load abort, so we could not even read related
GuC error log to investigate cause of the problem.

Fix that by always returning -EIO on uC hardware related failure.

v2: don't allow -EIO from uc_init
 don't call uc_fini[_misc] on -EIO
 mark guc fw as failed on hw init failure
 prepare uc_fini_hw to run after earlier -EIO

v3: update comments (Sagar)
 use sanitize functions on failure in init_hw (Michal)
 and also sanitize guc/huc fw in fini_hw (Michal)

v4: rebase

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiar...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>



  void intel_uc_fini_hw(struct drm_i915_private *i915)
  {
+   struct intel_guc *guc = >guc;
+
+   if (!intel_guc_is_loaded(guc))
+   return;
I feel above guc_is_loaded check is more applicable in uc_sanitize. So 
callers won't have to bother if GuC is loaded or not.

w/ or w/o that change patch looks good though.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

+
intel_uc_sanitize(i915);
  }
  
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h

index dc33b12..77ad2aa 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -121,6 +121,11 @@ static inline void intel_uc_fw_sanitize(struct intel_uc_fw 
*uc_fw)
uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
  }
  
+static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)

+{
+   return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
+}
+
  /**
   * intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
   * @uc_fw: uC firmware.


--
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Sagar

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Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/uc: Fully sanitize uC in uc_fini_hw

[Sagar Arun Kamble]

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:

Today uc_fini_hw is subset of uc_sanitize, but remaining
code in sanitize function is also desired for uc_fini_hw.
Instead of duplicating the code, just call uc_sanitize,
but leave as separate function to maintain symmetry with
uc_init_hw.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_uc.c | 14 ++
  1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ec90c81..46c4dc4 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -433,19 +433,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
  }
  
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)

+void intel_uc_fini_hw(struct drm_i915_private *i915)
  {
-   struct intel_guc *guc = _priv->guc;
-
-   if (!USES_GUC(dev_priv))
-   return;
-
-   GEM_BUG_ON(!HAS_GUC(dev_priv));
-
-   if (USES_GUC_SUBMISSION(dev_priv))
-   intel_guc_submission_disable(guc);
-
-   guc_disable_communication(guc);
+   intel_uc_sanitize(i915);
  }
  
  int intel_uc_suspend(struct drm_i915_private *i915)


--
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Re: [Intel-gfx] [PATCH v5 3/8] drm/i915/guc: Restore symmetric doorbell cleanup

[Sagar Arun Kamble]

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:

In commit 9192d4fb811e ("drm/i915/guc: Extract doorbell creation
from client allocation") we introduced asymmetry in doorbell cleanup
to avoid warnings due to failed communication with already reset GuC.
As we improved our reset/unload paths, we can restore symmetry in
doorbell cleanup, as GuC should be still active by now.

Suggested-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

This looks good.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

We should extend this functionality further to consider cases when GuC 
doorbell deactivation flow is to be
invoked (when GuC is in sane state) and not to be invoked (when GuC is 
hung) as was prepared in patchset
https://patchwork.freedesktop.org/series/33209/ but that can be done 
after this series if we agree on need for such handling.


Thanks,
Sagar

---
  drivers/gpu/drm/i915/intel_guc_submission.c | 15 +++
  1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 207cda0..26985d8 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -835,18 +835,9 @@ static int guc_clients_doorbell_init(struct intel_guc *guc)
  
  static void guc_clients_doorbell_fini(struct intel_guc *guc)

  {
-   /*
-* By the time we're here, GuC has already been reset.
-* Instead of trying (in vain) to communicate with it, let's just
-* cleanup the doorbell HW and our internal state.
-*/
-   if (guc->preempt_client) {
-   __destroy_doorbell(guc->preempt_client);
-   __update_doorbell_desc(guc->preempt_client,
-  GUC_DOORBELL_INVALID);
-   }
-   __destroy_doorbell(guc->execbuf_client);
-   __update_doorbell_desc(guc->execbuf_client, GUC_DOORBELL_INVALID);
+   if (guc->preempt_client)
+   destroy_doorbell(guc->preempt_client);
+   destroy_doorbell(guc->execbuf_client);
  }
  
  /**


--
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Re: [Intel-gfx] [PATCH v5 2/8] drm/i915/uc: Disable GuC submission during sanitize

[Sagar Arun Kamble]

On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:

We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_uc.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 4aad844..ec90c81 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -330,6 +330,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
  
  	GEM_BUG_ON(!HAS_GUC(i915));
  
+	if (USES_GUC_SUBMISSION(dev_priv))

+   intel_guc_submission_disable(guc);
+
guc_disable_communication(guc);
  
  	intel_huc_sanitize(huc);


--
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Re: [Intel-gfx] [PATCH v5 01/12] drm/i915/guc: Add documentation for MMIO based communication

[Sagar Arun Kamble]

On 3/27/2018 1:18 AM, Michal Wajdeczko wrote:

As we are going to extend our use of MMIO based communication,
try to explain its mechanics and update corresponding definitions.

v2: fix checkpatch MACRO_ARG_REUSE

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Kelvin Gardiner <kelvin.gardi...@intel.com>
Reviewed-by: Michel Thierry <michel.thie...@intel.com> #1
---




  }
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 72941bd..83143e8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -560,7 +560,68 @@ struct guc_shared_ctx_data {
struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
  } __packed;
  
-/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */

+/**
+ * DOC: MMIO based communication
+ *
+ * The MMIO based communication between Host and GuC uses software scratch
+ * registers, where first register holds data treated as message header,
+ * and other registers are used to hold message payload.
+ *
+ * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8

diagram below should be marked as reST literal block with "::"

+ *
+ *  +---+-+-+-+
+ *  |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
+ *  +---+-+-+-+
+ *  | header|  optional payload   |
+ *  +==++=+=+=+
+ *  | 31:28|type| | | |
+ *  +--++ | | |
+ *  | 27:16|data| | | |
+ *  +--++ | | |
+ *  |  15:0|code| | | |
+ *  +--++-+-+-+
+ *
+ * The message header consists of:
+ *
+ * - **type**, indicates message type
+ * - **code**, indicates message code, is specific for **type**
+ * - **data**, indicates message data, optional, depends on **code**
+ *
+ * The following message **types** are supported:
+ *
+ * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
+ *   must be priovided in **code** field. Optional action specific parameters
+ *   can be provided in remaining payload registers or **data** field.
+ *
+ * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
+ *   action response status will be provided in **code** field. Optional
+ *   response data can be returned in remaining payload registers or **data**
+ *   field.
+ */
+
+#define INTEL_GUC_MSG_TYPE_SHIFT   28
+#define INTEL_GUC_MSG_TYPE_MASK(0xF << 
INTEL_GUC_MSG_TYPE_SHIFT)
+#define INTEL_GUC_MSG_DATA_SHIFT   16
+#define INTEL_GUC_MSG_DATA_MASK(0xFFF << 
INTEL_GUC_MSG_DATA_SHIFT)
+#define INTEL_GUC_MSG_CODE_SHIFT   0
+#define INTEL_GUC_MSG_CODE_MASK(0x << 
INTEL_GUC_MSG_CODE_SHIFT)
+
+#define __INTEL_GUC_MSG_GET(T, m) \
+   (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
+#define INTEL_GUC_MSG_TO_TYPE(m)   __INTEL_GUC_MSG_GET(TYPE, m)
+#define INTEL_GUC_MSG_TO_DATA(m)   __INTEL_GUC_MSG_GET(DATA, m)
+#define INTEL_GUC_MSG_TO_CODE(m)   __INTEL_GUC_MSG_GET(CODE, m)
+
+enum intel_guc_msg_type {
+   INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
+   INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
+};
+
+#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
+   (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
+#define INTEL_GUC_MSG_IS_REQUEST(m)__INTEL_GUC_MSG_TYPE_IS(REQUEST, m)

*_MSG_IS_REQUEST isn't used. Do we plan to use this?

+#define INTEL_GUC_MSG_IS_RESPONSE(m)   __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
+
  enum intel_guc_action {
r   INTEL_GUC_ACTION_DEFAULT = 0x0,
INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
@@ -597,24 +658,17 @@ enum intel_guc_report_status {
  #define GUC_LOG_CONTROL_VERBOSITY_MASK(0xF << 
GUC_LOG_CONTROL_VERBOSITY_SHIFT)
  #define GUC_LOG_CONTROL_DEFAULT_LOGGING   (1 << 8)
  
-/*

- * The GuC sends its response to a command by overwriting the
- * command in SS0. The response is distinguishable from a command
- * by the fact that all the MASK bits are set. The remaining bits
- * give more detail.
- */
-#defineINTEL_GUC_RECV_MASK ((u32)0xF000)
-#defineINTEL_GUC_RECV_IS_RESPONSE(x)   ((u32)(x) >= 
INTEL_GUC_RECV_MASK)
-#defineINTEL_GUC_RECV_STATUS(x)(INTEL_GUC_RECV_MASK | (x))
-
-/* GUC will return status back to SOFT_SCRATCH_O_REG */
-enum intel_guc_status {
-   INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0),
-   INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10),
-   INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20),
-   INTEL_GUC_STAT

Re: [Intel-gfx] [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw

[Sagar Arun Kamble]

On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:

Today uc_fini_hw is subset of uc_sanitize, but remaining
code in sanitize function is also desired for uc_fini_hw.
Instead of duplicating the code, just call uc_sanitize,
but leave as separate function to maintain symmetry with
uc_init_hw.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
We should drop call to uc_fini_hw from gem_fini as part of this patch as 
GuC won't be available then.

---
  drivers/gpu/drm/i915/intel_uc.c | 14 ++
  1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2389828..9ff0c5a 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -434,19 +434,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
  }
  
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)

+void intel_uc_fini_hw(struct drm_i915_private *i915)
  {
-   struct intel_guc *guc = _priv->guc;
-
-   if (!USES_GUC(dev_priv))
-   return;
-
-   GEM_BUG_ON(!HAS_GUC(dev_priv));
-
-   if (USES_GUC_SUBMISSION(dev_priv))
-   intel_guc_submission_disable(guc);
-
-   guc_disable_communication(guc);
+   intel_uc_sanitize(i915);
  }
  
  int intel_uc_suspend(struct drm_i915_private *i915)


--
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Sagar

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Re: [Intel-gfx] [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize

[Sagar Arun Kamble]

On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:

We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Either we need now destroy the doorbells cleanly or remove the below 
comment from clients_doorbell_fini:

    /*
 * By the time we're here, GuC has already been reset.
 * Instead of trying (in vain) to communicate with it, let's just
 * cleanup the doorbell HW and our internal state.
 */

One additional thing I feel we should do now is remove uc_suspend|resume 
from gem_suspend|resume

because we don't want to do any GuC actions once we suspend it.

---
  drivers/gpu/drm/i915/intel_uc.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 34f8a2c..2389828 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -331,6 +331,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
  
  	GEM_BUG_ON(!HAS_GUC(i915));
  
+	if (USES_GUC_SUBMISSION(dev_priv))

+   intel_guc_submission_disable(guc);
+
guc_disable_communication(guc);
  
  	intel_huc_sanitize(huc);


--
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Re: [Intel-gfx] [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw

[Sagar Arun Kamble]

On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:

In function gem_init_hw() we are calling uc_init_hw() but in case
of error later in function, we missed to call matching uc_fini_hw()

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Looks good.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 802df8e..7fad180 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5171,9 +5171,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
  
  	/* Only when the HW is re-initialised, can we replay the requests */

ret = __i915_gem_restart_engines(dev_priv);
+   if (ret)
+   goto cleanup_uc;
  out:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return ret;
+
+cleanup_uc:
+   intel_uc_fini_hw(dev_priv);
+   goto out;
  }
  
  static int __intel_engines_record_defaults(struct drm_i915_private *i915)


--
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Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

[Sagar Arun Kamble]

On 3/23/2018 4:53 PM, Piotr Piórkowski wrote:

If GuC firmware is not available on the system and we load i915 with enable
GuC, then we hit this null pointer dereference issue:

Patch looks good but I have query on usage of enable_guc modparam.
enable_guc modparam will enable GuC/HuC only if firmware is available.
If user sets to forcefully enable GuC/HuC on systems that don't have 
firmware then it is user's fault.

Michal, could you please clarify.

Thanks,
Sagar


[   71.098873] BUG: unable to handle kernel NULL pointer dereference at 
0008
[   71.098938] IP: intel_uc_fw_upload+0x1f/0x360 [i915]
[   71.098947] PGD 0 P4D 0
[   71.098956] Oops:  [#1] PREEMPT SMP PTI
[   71.098965] Modules linked in: i915(O+) netconsole x86_pkg_temp_thermal 
intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel 
mei_me i2c_i801 prime_numbers mei [last unloaded: i915]
[   71.099005] CPU: 2 PID: 1167 Comm: insmod Tainted: G U  W  O 
4.16.0-rc1+ #337
[   71.099018] Hardware name: /NUC6i5SYB, BIOS SYSKLi35.86A.0065.2018.0103.1000 
01/03/2018
[   71.099077] RIP: 0010:intel_uc_fw_upload+0x1f/0x360 [i915]
[   71.099087] RSP: 0018:c9417aa0 EFLAGS: 00010282
[   71.099097] RAX:  RBX: 88084cad12f8 RCX: a03e9357
[   71.099108] RDX: 0002 RSI: a034dba0 RDI: 88084cad12f8
[   71.099118] RBP: 0002 R08: 88085344ca90 R09: 0001
[   71.099128] R10:  R11:  R12: 88084cad
[   71.099139] R13: a034dba0 R14: fff5 R15: 88084cad12b0
[   71.099151] FS:  7f7f24ae2740() GS:88085e20() 
knlGS:
[   71.099162] CS:  0010 DS:  ES:  CR0: 80050033
[   71.099171] CR2: 0008 CR3: 000855f48001 CR4: 003606e0
[   71.099182] Call Trace:
[   71.099246]  intel_uc_init_hw+0xc8/0x520 [i915]
[   71.099303]  i915_gem_init_hw+0x11f/0x2d0 [i915]
[   71.099364]  i915_gem_init+0x2b9/0x640 [i915]
[   71.099413]  i915_driver_load+0xb74/0x1110 [i915]
[   71.099462]  i915_pci_probe+0x2e/0x90 [i915]
[   71.099476]  pci_device_probe+0xa1/0x130
[   71.099488]  driver_probe_device+0x302/0x470
[   71.099502]  __driver_attach+0xb9/0xe0
[   71.099513]  ? driver_probe_device+0x470/0x470
[   71.099525]  ? driver_probe_device+0x470/0x470
[   71.099538]  bus_for_each_dev+0x64/0x90
[   71.099550]  bus_add_driver+0x164/0x260
[   71.099561]  ? 0xa04d6000
[   71.099572]  driver_register+0x57/0xc0
[   71.099582]  ? 0xa04d6000
[   71.099593]  do_one_initcall+0x3b/0x160
[   71.099606]  ? kmem_cache_alloc_trace+0x1c3/0x2a0
[   71.099621]  do_init_module+0x5b/0x1f9
[   71.099635]  load_module+0x2467/0x2a70
[   71.099654]  ? SyS_finit_module+0xbd/0xe0
[   71.099668]  SyS_finit_module+0xbd/0xe0
[   71.099682]  do_syscall_64+0x73/0x1c0
[   71.099694]  entry_SYSCALL_64_after_hwframe+0x26/0x9b
[   71.099706] RIP: 0033:0x7f7f23fb40d9
[   71.099717] RSP: 002b:7ffda7d67ed8 EFLAGS: 0246 ORIG_RAX: 
0139
[   71.099734] RAX: ffda RBX: 55f96e2a8870 RCX: 7f7f23fb40d9
[   71.099748] RDX:  RSI: 55f96e2a8260 RDI: 0003
[   71.099763] RBP: 55f96e2a8260 R08:  R09: 7ffda7d68088
[   71.099777] R10: 0003 R11: 0246 R12: 
[   71.099791] R13: 55f96e2a8830 R14:  R15: 55f96e2a8260
[   71.099810] Code: 00 00 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 55 41 54 
49 89 f5 55 53 48 c7 c1 57 93 3e a0 48 8b 47 10 48 89 fb 4c 8b 07 <48> 8b 68 08 
8b 47 28 85 c0 74 15 83 f8 01 48 c7 c1 5b 93 3e a0
[   71.14] RIP: intel_uc_fw_upload+0x1f/0x360 [i915] RSP: c9417aa0
[   71.100020] CR2: 0008
[   71.100031] ---[ end trace d8ac93c30ceff5b2 ]--

Fixes: 6b0478fb722a ("drm/i915: Implement dynamic GuC WOPCM offset and size 
calculation")

v2: don't assume it is always GuC FW (Michal)
v3: added a new variable to avoid exceeding the number of characters in the
line (Michal)

Signed-off-by: Piotr Piórkowski <piotr.piorkow...@intel.com>
Reported-by: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Cc: Michał Winiarski <michal.winiar...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Jackie Li <yaodong...@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Reviewed-by: Jackie Li <yaodong...@intel.com>

---
  drivers/gpu/drm/i915/intel_uc_fw.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c 
b/drivers/gpu/drm/i915/intel_uc_fw.c
index 30c73243f54d..93b0fc661b3a 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH v3] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

[Sagar Arun Kamble]

Joonas suggests to include these files guc.c and wopcm.c in i915.rst 
with WOPCM being separate section from GuC.

Also ensure make htmldocs generates proper/expected documentation.

Thanks,
Sagar

On 3/15/2018 10:24 PM, Jackie Li wrote:

GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
sphinx build if not using proper reST syntax.

This patch uses reST literal blocks to make sure GuC Address Space and
WOPCM Layout diagrams to be generated correctly, and it also corrects some
errors in the diagram description.

v2:
  - Fixed errors in diagram description

v3:
  - Updated GuC Address Space kernel-doc based on Michal's suggestion

Signed-off-by: Jackie Li <yaodong...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
---
  drivers/gpu/drm/i915/intel_guc.c   | 56 --
  drivers/gpu/drm/i915/intel_wopcm.c | 44 --
  2 files changed, 52 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3eb516e..bcbdf15 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -495,35 +495,37 @@ int intel_guc_resume(struct intel_guc *guc)
  /**
   * DOC: GuC Address Space
   *
- * The layout of GuC address space is shown as below:
+ * The layout of GuC address space is shown below:
   *
- *+==> ++ <== GUC_GGTT_TOP
- *^||
- *|||
- *||DRAM|
- *||   Memory   |
- *|||
- *   GuC   ||
- * Address  +> ++ <== WOPCM Top
- *  Space   ^  |   HW contexts RSVD |
- *| |  |WOPCM   |
- *| | +==> ++ <== GuC WOPCM Top
- *|GuC^||
- *|GGTT   |||
- *|Pin   GuC   |GuC |
- *|Bias WOPCM  |   WOPCM|
- *| |Size  ||
- *| | |||
- *v v v||
- *+=+=+==> ++ <== GuC WOPCM Base
- * |   Non-GuC WOPCM|
- * |   (HuC/Reserved)   |
- * ++ <== WOPCM Base
+ * ::
   *
- * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of
- * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of
- * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is
- * set in GUC_WOPCM_SIZE register.
+ * +==> ++ <== GUC_GGTT_TOP
+ * ^||
+ * |||
+ * ||DRAM|
+ * ||   Memory   |
+ * |||
+ *GuC   ||
+ *  Address  +> ++ <== WOPCM Top
+ *   Space   ^  |   HW contexts RSVD |
+ * | |  |WOPCM   |
+ * | | +==> ++ <== GuC WOPCM Top
+ * |GuC^||
+ * |GGTT   |||
+ * |Pin   GuC   |GuC |
+ * |Bias WOPCM  |   WOPCM|
+ * | |Size  ||
+ * | | |||
+ * v v v||
+ * +=+=+==> ++ <== GuC WOPCM Base
+ *  |   Non-GuC WOPCM|
+ *  |   (HuC/Reserved)   |
+ *  ++ <== WOPCM Base
+ *
+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
+ * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is 
mapped
+ * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
+ * actual GuC WOPCM size.
   */
  
  /**

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/intel_wopcm.c
index 4117886..74bf76f 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -11,28 +11,30 @@
   * DOC: WOPCM Layout
   *
   * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
- * offset registers whose are calculated are determined by size of HuC/GuC
- * firmware size and set of hw requirements/restrictions as shown below:
+ * offset registers whose values are calculated and determined by HuC/GuC

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify parameters of public CT functions

[Sagar Arun Kamble]

On 3/20/2018 6:30 PM, Michal Wajdeczko wrote:
On Tue, 20 Mar 2018 08:24:14 +0100, Sagar Arun Kamble 
<sagar.a.kam...@intel.com> wrote:





On 3/19/2018 8:58 PM, Michal Wajdeczko wrote:

There is no need to mix parameter types in public CT functions
as we can always accept intel_guc_ct.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>



    /**
- * Enable buffer based command transport
+ * intel_guc_ct_enable - Enable buffer based command transport.
+ * @ct: pointer to CT struct
+ *
   * Shall only be called for platforms with HAS_GUC_CT.
- * @guc:    the guc
- * return:    0 on success
- *    non-zero on failure
+ *
+ * Returns:
+ * 0 on success, a negative errno code on failure.

Should be
  * Return: 0 on sucess ...


hmm, I'm not so sure:

$ grep -r "\* Return: .*" drivers/gpu/drm/* | wc -l
153

$ grep -r "\* Returns:$" drivers/gpu/drm/* | wc -l
344


Hi Michal,

kernel-doc rules recommend "Return:".

Thanks,
Sagar

   */
-int intel_guc_enable_ct(struct intel_guc *guc)
+int intel_guc_ct_enable(struct intel_guc_ct *ct)
  {
+    struct intel_guc *guc = ct_to_guc(ct);
  struct drm_i915_private *dev_priv = guc_to_i915(guc);

change to *i915 as part of this patch itself? :) similar for disable.


sure


Otherwise LGTM
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>


thanks
/m



--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify parameters of public CT functions

[Sagar Arun Kamble]

On 3/19/2018 8:58 PM, Michal Wajdeczko wrote:

There is no need to mix parameter types in public CT functions
as we can always accept intel_guc_ct.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
---
  drivers/gpu/drm/i915/intel_guc_ct.c | 34 --
  drivers/gpu/drm/i915/intel_guc_ct.h |  6 ++
  drivers/gpu/drm/i915/intel_uc.c |  4 ++--
  3 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c 
b/drivers/gpu/drm/i915/intel_guc_ct.c
index 0a0d3d5..7dd7de0 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -28,12 +28,21 @@
  
  enum { CTB_OWNER_HOST = 0 };
  
+/**

+ * intel_guc_ct_init_early - Initialize CT state without requiring device 
access
+ * @ct: pointer to CT struct
+ */
  void intel_guc_ct_init_early(struct intel_guc_ct *ct)
  {
/* we're using static channel owners */
ct->host_channel.owner = CTB_OWNER_HOST;
  }
  
+static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)

+{
+   return container_of(ct, struct intel_guc, ct);
+}
+
  static inline const char *guc_ct_buffer_type_to_str(u32 type)
  {
switch (type) {
@@ -416,16 +425,19 @@ static int intel_guc_send_ct(struct intel_guc *guc, const 
u32 *action, u32 len)
  }
  
  /**

- * Enable buffer based command transport
+ * intel_guc_ct_enable - Enable buffer based command transport.
+ * @ct: pointer to CT struct
+ *
   * Shall only be called for platforms with HAS_GUC_CT.
- * @guc:   the guc
- * return: 0 on success
- * non-zero on failure
+ *
+ * Returns:
+ * 0 on success, a negative errno code on failure.

Should be
 * Return: 0 on sucess ...

   */
-int intel_guc_enable_ct(struct intel_guc *guc)
+int intel_guc_ct_enable(struct intel_guc_ct *ct)
  {
+   struct intel_guc *guc = ct_to_guc(ct);
struct drm_i915_private *dev_priv = guc_to_i915(guc);

change to *i915 as part of this patch itself? :) similar for disable.
Otherwise LGTM
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

-   struct intel_guc_ct_channel *ctch = >ct.host_channel;
+   struct intel_guc_ct_channel *ctch = >host_channel;
int err;
  
  	GEM_BUG_ON(!HAS_GUC_CT(dev_priv));

@@ -441,14 +453,16 @@ int intel_guc_enable_ct(struct intel_guc *guc)
  }
  
  /**

- * Disable buffer based command transport.
+ * intel_guc_ct_disable - Disable buffer based command transport.
+ * @ct: pointer to CT struct
+ *
   * Shall only be called for platforms with HAS_GUC_CT.
- * @guc: the guc
   */
-void intel_guc_disable_ct(struct intel_guc *guc)
+void intel_guc_ct_disable(struct intel_guc_ct *ct)
  {
+   struct intel_guc *guc = ct_to_guc(ct);
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   struct intel_guc_ct_channel *ctch = >ct.host_channel;
+   struct intel_guc_ct_channel *ctch = >host_channel;
  
  	GEM_BUG_ON(!HAS_GUC_CT(dev_priv));
  
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h b/drivers/gpu/drm/i915/intel_guc_ct.h

index 6d97f36..595c8ad 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/intel_guc_ct.h
@@ -78,9 +78,7 @@ struct intel_guc_ct {
  };
  
  void intel_guc_ct_init_early(struct intel_guc_ct *ct);

-
-/* XXX: move to intel_uc.h ? don't fit there either */
-int intel_guc_enable_ct(struct intel_guc *guc);
-void intel_guc_disable_ct(struct intel_guc *guc);
+int intel_guc_ct_enable(struct intel_guc_ct *ct);
+void intel_guc_ct_disable(struct intel_guc_ct *ct);
  
  #endif /* _INTEL_GUC_CT_H_ */

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 34e847d..a45c2ce 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -232,7 +232,7 @@ static int guc_enable_communication(struct intel_guc *guc)
gen9_enable_guc_interrupts(dev_priv);
  
  	if (HAS_GUC_CT(dev_priv))

-   return intel_guc_enable_ct(guc);
+   return intel_guc_ct_enable(>ct);
  
  	guc->send = intel_guc_send_mmio;

return 0;
@@ -243,7 +243,7 @@ static void guc_disable_communication(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
  
  	if (HAS_GUC_CT(dev_priv))

-   intel_guc_disable_ct(guc);
+   intel_guc_ct_disable(>ct);
  
  	gen9_disable_guc_interrupts(dev_priv);
  


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 3/16/2018 5:44 PM, Mika Kuoppala wrote:

From: Oscar Mateo <oscar.ma...@intel.com>

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.

Unfortunately, we have a Catch-22 situation going on: we need the blitter
forcewake to read the register with the fuse info, but we cannot initialize
the forcewake domains without knowin about the engines present in the HW.
We workaround this problem by allowing the initialization of all forcewake
domains and then pruning the fused off ones, as per the fuse information.

Bspec: 20680

v2: We were shifting incorrectly for vebox disable (Vinay)

v3: Assert mmio is ready and warn if we have attempted to initialize
 forcewake for fused-off engines (Paulo)

v4:
   - Use INTEL_GEN in new code (Tvrtko)
   - Shorter local variable (Tvrtko, Michal)
   - Keep "if (!...) continue" style (Tvrtko)
   - No unnecessary BUG_ON (Tvrtko)
   - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
   - Use I915_READ_FW (Michal)
   - Use I915_MAX_VCS/VECS macros (Michal)

v5: Rebased by Rodrigo fixing conflicts on top of:
 commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

v6: Fix v5. Remove info->num_rings. (by Oscar)

v7: Rebase (Rodrigo).

v8:
   - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
   - Make vdbox_disable & vebox_disable local variables (Chris)

v9:
   - Move function declaration to intel_device_info.h (Michal)
   - Missing indent in bit fields definitions (Michal)
   - When RC6 is enabled by BIOS, the fuse register cannot be read until
 the blitter powerwell is awake. Shuffle where the fuse is read, prune
 the forcewake domains after the fact and change the commit message
 accordingly (Vinay, Sagar, Chris).

v10:
   - Improved commit message (Sagar)
   - New line in header file (Sagar)
   - Specify the message in fw_domain_reset applies to ICL+ (Sagar)

Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaum...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.c  |  4 +++
  drivers/gpu/drm/i915/i915_reg.h  |  5 +++
  drivers/gpu/drm/i915/intel_device_info.c | 47 +++
  drivers/gpu/drm/i915/intel_device_info.h |  2 ++
  drivers/gpu/drm/i915/intel_uncore.c  | 56 
  drivers/gpu/drm/i915/intel_uncore.h  |  1 +
  6 files changed, 115 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3df5193487f3..83df8e21cec0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1033,6 +1033,10 @@ static int i915_driver_init_mmio(struct drm_i915_private 
*dev_priv)
  
  	intel_uncore_init(dev_priv);
  
+	intel_device_info_init_mmio(dev_priv);

+
+   intel_uncore_prune(dev_priv);
+
intel_uc_init_mmio(dev_priv);
  
  	ret = intel_engines_init_mmio(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf7c837d6a09..982e72e73e99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2545,6 +2545,11 @@ enum i915_power_well_id {
  #define GEN10_EU_DISABLE3 _MMIO(0x9140)
  #define   GEN10_EU_DIS_SS_MASK0xff
  
+#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)

+#define   GEN11_GT_VDBOX_DISABLE_MASK  0xff
+#define   GEN11_GT_VEBOX_DISABLE_SHIFT 16
+#define   GEN11_GT_VEBOX_DISABLE_MASK  (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
  #define GEN6_BSD_SLEEP_PSMI_CONTROL   _MMIO(0x12050)
  #define   GEN6_BSD_SLEEP_MSG_DISABLE  (1 << 0)
  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 3dd350f7b8e6..4babfc6ee45b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -780,3 +780,50 @@ void intel_driver_caps_print(const struct 
intel_driver_caps *caps,
  {
drm_printf(p, "scheduler: %x\n", caps->scheduler);
  }
+
+/*
+ * Determine which engines are fused off in our particular hardware. Since the
+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
+ * this point (but later we need to prune the forcewake domains for engines 
that
+ * are indeed fus

Re: [Intel-gfx] [PATCH v3 10/13] drm/i915/guc: Allow user to control default GuC logging

[Sagar Arun Kamble]

On 3/19/2018 3:23 PM, Michał Winiarski wrote:

While both naming and actual log enable logic in GuC interface are
confusing, we can simply expose the default log as yet another log
level.
GuC logic aside, from i915 point of view we now have the following GuC
log levels:
0 Log disabled
1 Non-verbose log
2-5 Verbose log

v2: Adjust naming after rebase.
v3: Fixed the log_level logic error introduced on rebase.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v2)
---
  drivers/gpu/drm/i915/intel_guc.c  | 24 +++-
  drivers/gpu/drm/i915/intel_guc_fwif.h |  5 +++--
  drivers/gpu/drm/i915/intel_guc_log.c  | 18 +++---
  drivers/gpu/drm/i915/intel_guc_log.h  | 15 +++
  drivers/gpu/drm/i915/intel_uc.c   | 14 +-
  5 files changed, 49 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index d4c2524012fa..05c3484d02a3 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -221,17 +221,23 @@ static u32 get_core_family(struct drm_i915_private 
*dev_priv)
}
  }
  
-static u32 get_log_verbosity_flags(void)

+static u32 get_log_control_flags(void)
  {
-   if (i915_modparams.guc_log_level > 0) {
-   u32 verbosity = i915_modparams.guc_log_level - 1;
+   u32 level = i915_modparams.guc_log_level;
+   u32 flags = 0;
  
-		GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);

-   return verbosity << GUC_LOG_VERBOSITY_SHIFT;
-   }
+   GEM_BUG_ON(level < 0);
+
+   if (!GUC_LOG_LEVEL_TO_ENABLED(level))
+   flags |= GUC_LOG_DEFAULT_DISABLED;
+
+   if (!GUC_LOG_LEVEL_TO_VERBOSE(level))
+   flags |= GUC_LOG_DISABLED;
+   else
+   flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
+GUC_LOG_VERBOSITY_SHIFT;
  
-	GEM_BUG_ON(i915_modparams.enable_guc < 0);

-   return GUC_LOG_DISABLED;
+   return flags;
  }
  
  /*

@@ -266,7 +272,7 @@ void intel_guc_init_params(struct intel_guc *guc)
  
  	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
  
-	params[GUC_CTL_DEBUG] = get_log_verbosity_flags();

+   params[GUC_CTL_DEBUG] = get_log_control_flags();
  
  	/* If GuC submission is enabled, set up additional parameters here */

if (USES_GUC_SUBMISSION(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 6a10aa6f04d3..4971685a2ea8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -127,7 +127,7 @@
  #define   GUC_PROFILE_ENABLED (1 << 7)
  #define   GUC_WQ_TRACK_ENABLED(1 << 8)
  #define   GUC_ADS_ENABLED (1 << 9)
-#define   GUC_DEBUG_RESERVED   (1 << 10)
+#define   GUC_LOG_DEFAULT_DISABLED (1 << 10)
  #define   GUC_ADS_ADDR_SHIFT  11
  #define   GUC_ADS_ADDR_MASK   0xf800
  
@@ -539,7 +539,8 @@ union guc_log_control {

u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
-   u32 reserved2:24;
+   u32 default_logging:1;
+   u32 reserved2:23;
};
u32 value;
  } __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 1e671f2b2f64..068f5e7f7594 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -57,12 +57,14 @@ static int guc_log_flush(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
  }
  
-static int guc_log_control(struct intel_guc *guc, bool enable, u32 verbosity)

+static int guc_log_control(struct intel_guc *guc, bool enable,
+  bool default_logging, u32 verbosity)

Can we change the order of parameters as:
struct intel_guc *guc, bool default_logging, bool enable, u32 verbosity

That way I can see that param 3 and param 4 are related.
But this change can be done at your discretion.

Updated logic to handle default logging looks fine.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

  {
union guc_log_control control_val = {
{
.logging_enabled = enable,
.verbosity = verbosity,
+   .default_logging = default_logging,
},
};
u32 action[] = {
@@ -499,13 +501,6 @@ int intel_guc_log_level_get(struct intel_guc_log *log)
return i915_modparams.guc_log_level;
  }
  
-#define GUC_LOG_LEVEL_DISAB

Re: [Intel-gfx] [PATCH v3 01/13] drm/i915/guc: Keep GuC interrupts enabled when using GuC

[Sagar Arun Kamble]

On 3/19/2018 3:23 PM, Michał Winiarski wrote:

The GuC log contains a separate space used for crash dump.
We even get a separate notification for it. While we're not handling
crash differently yet, it makes sense to decouple the two right now to
simplify the following patches.

v2: Move guc_log_flush_irq_disable up to avoid movement in following
 patches (Sagar).
v3: s/guc_log_flush_irq_*/guc_flush_log_msg_*, rebase after mass rename

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v2)

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_guc.c | 25 ++---
  drivers/gpu/drm/i915/intel_guc.h |  2 ++
  drivers/gpu/drm/i915/intel_guc_log.c | 31 +++
  drivers/gpu/drm/i915/intel_uc.c  | 14 +-
  4 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e70bf654d21e..3af603536b1b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -67,6 +67,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_log_init_early(>log);
  
  	mutex_init(>send_mutex);

+   spin_lock_init(>irq_lock);
guc->send = intel_guc_send_nop;
guc->notify = gen8_guc_raise_irq;
  }
@@ -368,7 +369,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
  void intel_guc_to_host_event_handler(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   u32 msg, flush;
+   u32 msg, val;
  
  	/*

 * Sample the log buffer flush related bits & clear them out now
@@ -381,24 +382,18 @@ void intel_guc_to_host_event_handler(struct intel_guc 
*guc)
 * could happen that GuC sets the bit for 2nd interrupt but Host
 * clears out the bit on handling the 1st interrupt.
 */
-
-   msg = I915_READ(SOFT_SCRATCH(15));
-   flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
-  INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
-   if (flush) {
-   /* Clear the message bits that are handled */
-   I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
-   /* Handle flush interrupt in bottom half */
+   spin_lock(>irq_lock);
+   val = I915_READ(SOFT_SCRATCH(15));
+   msg = val & guc->msg_enabled_mask;
+   I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
+   spin_unlock(>irq_lock);
+
+   if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
+  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
queue_work(guc->log.runtime.flush_wq,
   >log.runtime.flush_work);
  
  		guc->log.flush_interrupt_count++;

-   } else {
-   /*
-* Not clearing of unhandled event bits won't result in
-* re-triggering of the interrupt.
-*/
}
  }
  
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h

index cdb649a9a4cf..9a95d1518aa9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -56,7 +56,9 @@ struct intel_guc {
struct drm_i915_gem_object *load_err_log;
  
  	/* intel_guc_recv interrupt related state */

+   spinlock_t irq_lock;
bool interrupts_enabled;
+   unsigned int msg_enabled_mask;
  
  	struct i915_vma *ads_vma;

struct i915_vma *stage_desc_pool;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 1c2127bc3878..1e209fcf90e1 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -73,6 +73,22 @@ static int guc_log_control(struct intel_guc *guc, bool 
enable, u32 verbosity)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
  }
  
+static void guc_flush_log_msg_enable(struct intel_guc *guc)

+{
+   spin_lock_irq(>irq_lock);
+   guc->msg_enabled_mask |= INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
+INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED;
+   spin_unlock_irq(>irq_lock);
+}
+
+static void guc_flush_log_msg_disable(struct intel_guc *guc)
+{
+   spin_lock_irq(>irq_lock);
+   guc->msg_enabled_mask &= ~(INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
+  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
+   spin_unlock_irq(>irq_lock);
+}
+
  static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
  {
return container_of(log, struct intel_guc, log);
@@ -709,12 +725,7 @@ int intel_guc_log_register(str

Re: [Intel-gfx] [PATCH 36/36] drm/i915: Support per-context user requests for GPU frequency control

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Often, we find ourselves facing a workload where the user knows in
advance what GPU frequency they require for it to complete in a timely
manner, and using past experience they can outperform the HW assisted
RPS autotuning. An example might be kodi (HTPC) where they know that
video decoding and compositing require a minimum frequency to avoid ever
dropping a frame, or conversely know when they are in a powersaving mode
and would rather have slower updates than ramp up the GPU frequency and
power consumption. Other workloads may defeat the autotuning entirely
and need manual control to meet their performance goals, e.g. bursty
applications which require low latency.

To accommodate the varying needs of different applications, that may be
running concurrently, we want a more flexible system than a global limit
supplied by sysfs. To this end, we offer the application the option to
set their desired frequency bounds on the context itself, and apply those
bounds when we execute commands from the application, switching between
bounds just as easily as we switch between the clients themselves.

The clients can query the range supported by the HW, or at least the
range they are restricted to, and then freely select frequencies within
that range that they want to run at. (They can select just a single
frequency if they so choose.) As this is subject to the global limit
supplied by the user in sysfs, and a client can only reduce the range of
frequencies they allow the HW to run at, we allow all clients to adjust
their request (and not restrict raising the minimum to privileged
CAP_SYS_NICE clients).

Testcase: igt/gem_ctx_freq
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Praveen Paneri 
Cc: Sagar A Kamble 

Change looks good to me. I have one query below.


diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8a8ad2fe158d..d8eaae683186 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -26,9 +26,12 @@
  #include 
  
  #include "intel_guc_submission.h"

-#include "intel_lrc_reg.h"
+
  #include "i915_drv.h"
  
+#include "intel_gt_pm.h"

+#include "intel_lrc_reg.h"
+
  #define GUC_PREEMPT_FINISHED  0x1
  #define GUC_PREEMPT_BREADCRUMB_DWORDS 0x8
  #define GUC_PREEMPT_BREADCRUMB_BYTES  \
@@ -650,6 +653,12 @@ static void guc_submit(struct intel_engine_cs *engine)
}
  }
  
+static void update_rps(struct intel_engine_cs *engine)

+{
+   intel_rps_update_engine(engine,
+   port_request(engine->execlists.port)->ctx);
+}
+
  static void port_assign(struct execlist_port *port, struct i915_request *rq)
  {
GEM_BUG_ON(port_isset(port));
@@ -728,6 +737,7 @@ static void guc_dequeue(struct intel_engine_cs *engine)
execlists->first = rb;
if (submit) {
port_assign(port, last);
+   update_rps(engine);
execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
guc_submit(engine);
}
@@ -757,8 +767,10 @@ static void guc_submission_tasklet(unsigned long data)
  
  		rq = port_request([0]);

}
-   if (!rq)
+   if (!rq) {
execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
+   intel_rps_update_engine(engine, NULL);
I think we also need to do this (update_engine(NULL)) while handling 
preemption completion for both GuC and execlists also.
Doing it as part of execlists_cancel_port_requests will cover all those 
cases including reset.

Am I right?

+   }
  
  	if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) &&

intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) ==
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3a69b367e565..518f7b3db857 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -138,6 +138,7 @@
  #include "i915_drv.h"
  #include "i915_gem_render_state.h"
  #include "intel_lrc_reg.h"
+#include "intel_gt_pm.h"
  #include "intel_mocs.h"
  
  #define RING_EXECLIST_QFULL		(1 << 0x2)

@@ -535,6 +536,12 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
execlists_set_active(>execlists, EXECLISTS_ACTIVE_PREEMPT);
  }
  
+static void update_rps(struct intel_engine_cs *engine)

+{
+   intel_rps_update_engine(engine,
+   port_request(engine->execlists.port)->ctx);
+}
+
  static void execlists_dequeue(struct intel_engine_cs *engine)
  {
struct intel_engine_execlists * const execlists = >execlists;
@@ -708,6 +715,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
spin_unlock_irq(>timeline->lock);
  
  	if (submit) {

+   

Re: [Intel-gfx] [PATCH 35/36] drm/i915: Remove unwarranted clamping for hsw/bdw

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

We always start off at an "efficient frequency" and can let the system
autotune from there, eliminating the need to clamp the available range.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_gt_pm.c | 9 +
  1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c 
b/drivers/gpu/drm/i915/intel_gt_pm.c
index 6f5c14421c90..9705205a26b5 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2432,17 +2432,9 @@ void intel_gt_pm_init(struct drm_i915_private *dev_priv)
gen5_init_gt_powersave(dev_priv);
  
  	/* Derive initial user preferences/limits from the hardware limits */

-   rps->idle_freq = rps->min_freq_hw;
-
rps->max_freq_user = rps->max_freq_hw;
rps->min_freq_user = rps->min_freq_hw;
  
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

-   rps->min_freq_user =
-   max_t(int,
- rps->efficient_freq,
- intel_freq_opcode(dev_priv, 450));
-
/* After setting max-softlimit, find the overclock max freq */
if (IS_GEN6(dev_priv) ||
IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
@@ -2462,6 +2454,7 @@ void intel_gt_pm_init(struct drm_i915_private *dev_priv)
  
  	/* Finally allow us to boost to max by default */

rps->boost_freq = rps->max_freq_hw;
+   rps->idle_freq = rps->min_freq_hw;
  
  	rps->freq = rps->idle_freq;

rps->min = rps->min_freq_hw;


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH 33/36] drm/i915: Pull IPS into RPS

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

IPS was the precursor to RPS on Ironlake. It serves the same function,
and so should be pulled under the intel_gt_pm umbrella.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Looks good except subject should be "Pull IPS into GT PM". It seems IPS 
and RPS merge is happening in next patch.

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.h| 37 -
  drivers/gpu/drm/i915/i915_irq.c| 21 +-
  drivers/gpu/drm/i915/intel_gt_pm.c | 83 +-
  drivers/gpu/drm/i915/intel_pm.c|  8 ++--
  4 files changed, 80 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd92d0295b63..cfbcaa8556e0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -784,23 +784,10 @@ struct intel_rps {
struct intel_rps_ei ei;
  };
  
-struct intel_rc6 {

-   u64 prev_hw_residency[4];
-   u64 cur_residency[4];
-};
-
-struct intel_gt_pm {
-   struct intel_rc6 rc6;
-   struct intel_rps rps;
-
-   u32 imr;
-   u32 ier;
-};
-
  /* defined intel_pm.c */
  extern spinlock_t mchdev_lock;
  
-struct intel_ilk_power_mgmt {

+struct intel_ips {
u8 cur_delay;
u8 min_delay;
u8 max_delay;
@@ -819,6 +806,24 @@ struct intel_ilk_power_mgmt {
int r_t;
  };
  
+struct intel_rc6 {

+   u64 prev_hw_residency[4];
+   u64 cur_residency[4];
+};
+
+struct intel_gt_pm {
+   struct intel_rc6 rc6;
+   struct intel_rps rps;
+   /*
+* ilk-only ips/rps state. Everything in here is protected by the
+* global mchdev_lock in intel_gt_pm.c
+*/
+   struct intel_ips ips;
+
+   u32 imr;
+   u32 ier;
+};
+
  struct drm_i915_private;
  struct i915_power_well;
  
@@ -1780,10 +1785,6 @@ struct drm_i915_private {
  
  	struct intel_gt_pm gt_pm;
  
-	/* ilk-only ips/rps state. Everything in here is protected by the global

-* mchdev_lock in intel_pm.c */
-   struct intel_ilk_power_mgmt ips;
-
struct i915_power_domains power_domains;
  
  	struct i915_psr psr;

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dfb711ca4d27..9a52692395f2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -852,6 +852,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
  
  static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)

  {
+   struct intel_ips *ips = _priv->gt_pm.ips;
u32 busy_up, busy_down, max_avg, min_avg;
u8 new_delay;
  
@@ -859,7 +860,7 @@ static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
  
  	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  
-	new_delay = dev_priv->ips.cur_delay;

+   new_delay = ips->cur_delay;
  
  	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);

busy_up = I915_READ(RCPREVBSYTUPAVG);
@@ -869,19 +870,19 @@ static void ironlake_rps_change_irq_handler(struct 
drm_i915_private *dev_priv)
  
  	/* Handle RCS change request from hw */

if (busy_up > max_avg) {
-   if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
-   new_delay = dev_priv->ips.cur_delay - 1;
-   if (new_delay < dev_priv->ips.max_delay)
-   new_delay = dev_priv->ips.max_delay;
+   if (ips->cur_delay != ips->max_delay)
+   new_delay = ips->cur_delay - 1;
+   if (new_delay < ips->max_delay)
+   new_delay = ips->max_delay;
} else if (busy_down < min_avg) {
-   if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
-   new_delay = dev_priv->ips.cur_delay + 1;
-   if (new_delay > dev_priv->ips.min_delay)
-   new_delay = dev_priv->ips.min_delay;
+   if (ips->cur_delay != ips->min_delay)
+   new_delay = ips->cur_delay + 1;
+   if (new_delay > ips->min_delay)
+   new_delay = ips->min_delay;
}
  
  	if (ironlake_set_drps(dev_priv, new_delay))

-   dev_priv->ips.cur_delay = new_delay;
+   ips->cur_delay = new_delay;
  
  	spin_unlock(_lock);
  
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c

index 18ab1b3a2945..def292cfd181 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -65,6 +65,7 @@ bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 
val)
  
  static void ironlake_enable_drps(struct drm_i915_private *dev_priv)

  {
+   struct intel_ips *ips = _priv->gt_pm.ips;
u32 rgvmodectl;
u8 fmax, fmin, fstart, vstart;
  
@@ -95,12 +96

Re: [Intel-gfx] [PATCH 32/36] drm/i915: Rename rps min/max frequencies

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

In preparation for more layers of limits, rename the existing limits to
hw and user.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_debugfs.c |  34 
  drivers/gpu/drm/i915/i915_drv.h |  21 +++--
  drivers/gpu/drm/i915/i915_pmu.c |   4 +-
  drivers/gpu/drm/i915/i915_sysfs.c   |  23 +++---
  drivers/gpu/drm/i915/intel_gt_pm.c  | 149 ++--
  5 files changed, 119 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index cfecc2509224..ccb01244e616 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1097,13 +1097,13 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
  
  		seq_printf(m, "current GPU freq: %d MHz\n",

-  intel_gpu_freq(dev_priv, rps->cur_freq));
+  intel_gpu_freq(dev_priv, rps->freq));
  
  		seq_printf(m, "max GPU freq: %d MHz\n",

-  intel_gpu_freq(dev_priv, rps->max_freq));
+  intel_gpu_freq(dev_priv, rps->max_freq_hw));
  
  		seq_printf(m, "min GPU freq: %d MHz\n",

-  intel_gpu_freq(dev_priv, rps->min_freq));
+  intel_gpu_freq(dev_priv, rps->min_freq_hw));
  
  		seq_printf(m, "idle GPU freq: %d MHz\n",

   intel_gpu_freq(dev_priv, rps->idle_freq));
@@ -1235,19 +1235,19 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
   intel_gpu_freq(dev_priv, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
-  intel_gpu_freq(dev_priv, rps->max_freq));
+  intel_gpu_freq(dev_priv, rps->max_freq_hw));
  
  		seq_printf(m, "Current freq: %d MHz\n",

-  intel_gpu_freq(dev_priv, rps->cur_freq));
+  intel_gpu_freq(dev_priv, rps->freq));
seq_printf(m, "Actual freq: %d MHz\n", cagf);
seq_printf(m, "Idle freq: %d MHz\n",
   intel_gpu_freq(dev_priv, rps->idle_freq));
seq_printf(m, "Min freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, rps->min_freq));
+  intel_gpu_freq(dev_priv, rps->min_freq_hw));
seq_printf(m, "Boost freq: %d MHz\n",
   intel_gpu_freq(dev_priv, rps->boost_freq));
seq_printf(m, "Max freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, rps->max_freq));
+  intel_gpu_freq(dev_priv, rps->max_freq_hw));
seq_printf(m,
   "efficient (RPe) frequency: %d MHz\n",
   intel_gpu_freq(dev_priv, rps->efficient_freq));
@@ -1802,8 +1802,8 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
if (!HAS_LLC(dev_priv))
return -ENODEV;
  
-	min_gpu_freq = rps->min_freq;

-   max_gpu_freq = rps->max_freq;
+   min_gpu_freq = rps->min_freq_hw;
+   max_gpu_freq = rps->max_freq_hw;
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq /= GEN9_FREQ_SCALER;
@@ -2197,13 +2197,15 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
seq_printf(m, "Boosts outstanding? %d\n",
   atomic_read(>num_waiters));
-   seq_printf(m, "Frequency requested %d\n",
-  intel_gpu_freq(dev_priv, rps->cur_freq));
-   seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
-  intel_gpu_freq(dev_priv, rps->min_freq),
-  intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
-  intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
-  intel_gpu_freq(dev_priv, rps->max_freq));
+   seq_printf(m, "Frequency requested %d [%d, %d]\n",
+  intel_gpu_freq(dev_priv, rps->freq),
+  intel_gpu_freq(dev_priv, rps->min),
+  intel_gpu_freq(dev_priv, rps->max));
+   seq_printf(m, "  min hard:%d, user:%d; max user:%d, hard:%d\n",
+  intel_gpu_freq(dev_priv, rps->min_freq_hw),
+

Re: [Intel-gfx] [PATCH 31/36] drm/i915: Don't fiddle with rps/rc6 across GPU reset

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Resetting the GPU doesn't affect the RPS/RC6 state, so we can stop
forcibly reloading the registers.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>

Changes look good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c | 4 
  1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9f5b3a2a8b61..9443464cebbb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3162,10 +3162,6 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
}
  
  	i915_gem_restore_fences(dev_priv);

-
-   intel_gt_pm_enable_rc6(dev_priv);
-   if (dev_priv->gt.awake)
-   intel_gt_pm_busy(dev_priv);
  }
  
  void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Handle GuC log flush event in dedicated function

[Sagar Arun Kamble]

On 3/17/2018 8:36 PM, Michal Wajdeczko wrote:

We already try to keep all GuC log related code in separate file,
handling flush event should be placed there too. This will also
allow future code reuse.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Michal Winiarski <michal.winiar...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.ma...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Ordering of the declarations is an issue but not critical.

---
  drivers/gpu/drm/i915/intel_guc.c | 6 +-
  drivers/gpu/drm/i915/intel_guc_log.c | 8 
  drivers/gpu/drm/i915/intel_guc_log.h | 1 +
  3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e70bf65..36c8846 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -389,11 +389,7 @@ void intel_guc_to_host_event_handler(struct intel_guc *guc)
/* Clear the message bits that are handled */
I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
  
-		/* Handle flush interrupt in bottom half */

-   queue_work(guc->log.runtime.flush_wq,
-  >log.runtime.flush_work);
-
-   guc->log.flush_interrupt_count++;
+   intel_guc_log_handle_flush_event(>log);
} else {
/*
 * Not clearing of unhandled event bits won't result in
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 1c2127b..394f295 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -558,6 +558,14 @@ static void guc_flush_logs(struct intel_guc_log *log)
guc_log_capture_logs(log);
  }
  
+void intel_guc_log_handle_flush_event(struct intel_guc_log *log)

+{
+   /* Handle flush event in bottom half */
+   queue_work(log->runtime.flush_wq, >runtime.flush_work);
+
+   log->flush_interrupt_count++;
+}
+
  int intel_guc_log_create(struct intel_guc_log *log)
  {
struct intel_guc *guc = log_to_guc(log);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h 
b/drivers/gpu/drm/i915/intel_guc_log.h
index 6264bd5..fc3d58d 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -63,6 +63,7 @@ struct intel_guc_log {
  void intel_guc_log_init_early(struct intel_guc_log *log);
  int intel_guc_log_create(struct intel_guc_log *log);
  int intel_guc_log_register(struct intel_guc_log *log);
+void intel_guc_log_handle_flush_event(struct intel_guc_log *log);
  void intel_guc_log_unregister(struct intel_guc_log *log);
  void intel_guc_log_destroy(struct intel_guc_log *log);
  


--
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Sagar

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Re: [Intel-gfx] [PATCH 30/36] drm/i915: Refactor frequency bounds computation

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

When choosing the initial frequency in intel_gt_pm_busy() we also need
to calculate the current min/max bounds. As this calculation is going to
become more complex with the intersection of several different limits,
refactor it to a common function. The alternative wold be to feed the

typo

initial reclocking through the RPS worker, but the latency in this case
is undesirable.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/intel_gt_pm.c | 58 +++---
  1 file changed, 22 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c 
b/drivers/gpu/drm/i915/intel_gt_pm.c
index 8630c30a7e48..f8e029b4a8a7 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -382,15 +382,25 @@ static int __intel_set_rps(struct drm_i915_private 
*dev_priv, u8 val)
return 0;
  }
  
-static int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)

+static int adjust_rps(struct drm_i915_private *dev_priv, int freq, int adj)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
+   int min, max, val;

Can we move to u8 type in this patch itself

int err;
  
  	lockdep_assert_held(>lock);

GEM_BUG_ON(!rps->active);
-   GEM_BUG_ON(val > rps->max_freq);
-   GEM_BUG_ON(val < rps->min_freq);
+
+   min = rps->min_freq_softlimit;
+   max = rps->max_freq_softlimit;
+   if (atomic_read(>num_waiters) && max < rps->boost_freq)
+   max = rps->boost_freq;
+
+   GEM_BUG_ON(min < rps->min_freq);
+   GEM_BUG_ON(max > rps->max_freq);
+   GEM_BUG_ON(max < min);
+
+   val = clamp(freq + adj, min, max);
  
  	err = __intel_set_rps(dev_priv, val);

if (err)
@@ -401,6 +411,8 @@ static int intel_set_rps(struct drm_i915_private *dev_priv, 
u8 val)
rps->cur_freq = val;
}
  
+	rps->last_adj = val == freq ? adj : 0;

+

I think this should be:
rps->last_adj = val == freq ? 0 : adj;
and this update can be done in previous if/(else) condition.

return 0;
  }
  
@@ -562,8 +574,8 @@ static void intel_rps_work(struct work_struct *work)

struct drm_i915_private *i915 =
container_of(work, struct drm_i915_private, gt_pm.rps.work);
struct intel_rps *rps = >gt_pm.rps;
-   int freq, adj, min, max;
bool client_boost;
+   int freq, adj;
u32 pm_iir;
  
  	pm_iir = xchg(>pm_iir, 0) & ~rps->pm_events;

@@ -576,15 +588,6 @@ static void intel_rps_work(struct work_struct *work)
if (!rps->active)
goto unlock;
  
-	min = rps->min_freq_softlimit;

-   max = rps->max_freq_softlimit;
-   if (client_boost && max < rps->boost_freq)
-   max = rps->boost_freq;
-
-   GEM_BUG_ON(min < rps->min_freq);
-   GEM_BUG_ON(max > rps->max_freq);
-   GEM_BUG_ON(max < min);
-
adj = rps->last_adj;
freq = rps->cur_freq;
if (client_boost && freq < rps->boost_freq) {
@@ -595,16 +598,13 @@ static void intel_rps_work(struct work_struct *work)
adj *= 2;
else /* CHV needs even encode values */
adj = IS_CHERRYVIEW(i915) ? 2 : 1;
-
-   if (freq >= max)
-   adj = 0;
} else if (client_boost) {
adj = 0;
} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
-   if (freq > max_t(int, rps->efficient_freq, min))
-   freq = max_t(int, rps->efficient_freq, min);
-   else if (freq > min_t(int, rps->efficient_freq, min))
-   freq = min_t(int, rps->efficient_freq, min);
+   if (freq > rps->efficient_freq)
+   freq = rps->efficient_freq;
+   else if (freq > rps->idle_freq)
+   freq = rps->idle_freq;
  
  		 adj = 0;

} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
@@ -612,23 +612,17 @@ static void intel_rps_work(struct work_struct *work)
adj *= 2;
else /* CHV needs even encode values */
adj = IS_CHERRYVIEW(i915) ? -2 : -1;
-
-   if (freq <= min)
-   adj = 0;
} else { /* unknown/external event */
adj = 0;
}
  
-	if (intel_set_rps(i915, clamp_t(int, freq + adj, min, max))) {

+   if (adjust_rps(i915, freq, adj))
DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
-   adj = 0;
-   }
  
  	if (pm_iir) {

spin_lock_irq(>irq_lock);
gen6_unmask_pm_irq(i915, rps->pm_events);
spin_unlock_irq(>irq_lock);
-   rps->last_adj = adj;
}
  
  unlock:

@@ -652,7 +646,6 @@ void intel_gt_pm_irq_handler(struct drm_i915_private 
*dev_priv, u32 pm_iir)
  void intel_gt_pm_busy(struct drm_i915_private *dev_priv)
  {
struct 

Re: [Intel-gfx] [PATCH 29/36] drm/i915: Simplify rc6/rps enabling

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

As we know that whenever the GT is awake, rc6 and rps are enabled (if
available), then we can remove the individual tracking and enabling to
the gen6_rps_busy/gen6_rps_idle() (now called intel_gt_pm_busy and
intel_gt_pm_idle) entry points.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |   6 +-
  drivers/gpu/drm/i915/i915_drv.c  |   3 -
  drivers/gpu/drm/i915/i915_drv.h  |  19 +--
  drivers/gpu/drm/i915/i915_gem.c  |  23 +--
  drivers/gpu/drm/i915/i915_request.c  |   4 +-
  drivers/gpu/drm/i915/i915_sysfs.c|   6 +-
  drivers/gpu/drm/i915/intel_display.c |   4 +-
  drivers/gpu/drm/i915/intel_gt_pm.c   | 273 +--
  drivers/gpu/drm/i915/intel_gt_pm.h   |   7 +-
  9 files changed, 125 insertions(+), 220 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ea7a30ce53e0..cfecc2509224 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2191,9 +2191,9 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
struct intel_rps *rps = _priv->gt_pm.rps;
struct drm_file *file;
  
-	seq_printf(m, "RPS enabled? %d\n", rps->enabled);

seq_printf(m, "GPU busy? %s [%d requests]\n",
   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
+   seq_printf(m, "RPS active? %s\n", yesno(rps->active));
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
seq_printf(m, "Boosts outstanding? %d\n",
   atomic_read(>num_waiters));
@@ -2226,9 +2226,7 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
   atomic_read(>boosts));
mutex_unlock(>filelist_mutex);
  
-	if (INTEL_GEN(dev_priv) >= 6 &&

-   rps->enabled &&
-   dev_priv->gt.active_requests) {
+   if (INTEL_GEN(dev_priv) >= 6 && dev_priv->gt.awake) {
u32 rpup, rpupei;
u32 rpdown, rpdownei;
  
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c

index 11eaaf679450..80acd0a06786 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2575,9 +2575,6 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
  
-	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv

-   return -ENODEV;
-
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
  
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h

index 0acabfd1e3e7..0973622431bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -731,14 +731,10 @@ struct intel_rps_ei {
  
  struct intel_rps {

struct mutex lock;
-
-   /*
-* work, interrupts_enabled and pm_iir are protected by
-* dev_priv->irq_lock
-*/
struct work_struct work;
-   bool interrupts_enabled;
-   u32 pm_iir;
+
+   bool active;
+   u32 pm_iir; /* protected by dev_priv->irq_lock */
  
  	/* PM interrupt bits that should never be masked */

u32 pm_intrmsk_mbz;
@@ -774,7 +770,6 @@ struct intel_rps {
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
  
-	bool enabled;

atomic_t num_waiters;
atomic_t boosts;
  
@@ -783,14 +778,13 @@ struct intel_rps {

  };
  
  struct intel_rc6 {

-   bool enabled;
u64 prev_hw_residency[4];
u64 cur_residency[4];
  };
  
-struct intel_gen6_power_mgmt {

-   struct intel_rps rps;
+struct intel_gt_pm {
struct intel_rc6 rc6;
+   struct intel_rps rps;
  
  	u32 imr;

u32 ier;
@@ -1777,8 +1771,7 @@ struct drm_i915_private {
/* Cannot be determined by PCIID. You must always read a register. */
u32 edram_cap;
  
-	/* gen6+ GT PM state */

-   struct intel_gen6_power_mgmt gt_pm;
+   struct intel_gt_pm gt_pm;
  
  	/* ilk-only ips/rps state. Everything in here is protected by the global

 * mchdev_lock in intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8a5bf1e26515..9f5b3a2a8b61 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -388,10 +388,8 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
 * forcing the clocks too high for the whole system, we only allow
 * each client to waitboost once in a busy period.
 */
-   if (rps_client && !i915_request_started(rq)) {
-   if (INTEL_GEN(rq->i915) >= 6)
-   gen6_rps_boost(rq, rps_client);
-   }
+   if (rps_client && !i915_request_started(rq))
+   intel_rps_boost(rq, rps_client);
  
  	timeout = i915_request_wait(rq, flags, timeout);
  
@@ -3165,15 +3163,9 @@ void i915_gem_reset(struct 

Re: [Intel-gfx] [PATCH 28/36] drm/i915: Enabling rc6 and rps have different requirements, so separate them

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

On Ironlake, we are required to not enable rc6 until the GPU is loaded
with a valid context; after that point it can start to use a powersaving
context for rc6. This seems a reasonable requirement to impose on all
generations as we are already priming the system by loading a context on
resume. We can simply then delay enabling rc6 until we know the GPU is
awake.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_drv.c  |  1 +
  drivers/gpu/drm/i915/i915_gem.c  | 43 
  drivers/gpu/drm/i915/i915_request.c  |  3 ---
  drivers/gpu/drm/i915/intel_display.c |  5 -
  drivers/gpu/drm/i915/intel_gt_pm.c   |  2 ++
  5 files changed, 37 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index db88b8c3c4ae..11eaaf679450 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -632,6 +632,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
  
  	mutex_lock(_priv->drm.struct_mutex);

+   intel_gt_pm_fini(dev_priv);

going by the init order, it should happen after gem_contexts_fini

intel_uc_fini_hw(dev_priv);
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b9c7b21e5cc8..8a5bf1e26515 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3165,10 +3165,12 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
  
  	i915_gem_restore_fences(dev_priv);
  
-	if (dev_priv->gt.awake) {

-   intel_gt_pm_sanitize(dev_priv);
-   intel_gt_pm_enable_rps(dev_priv);
+   if (dev_priv->gt_pm.rc6.enabled) {
+   dev_priv->gt_pm.rc6.enabled = false;
intel_gt_pm_enable_rc6(dev_priv);
+   }
+

I think  patch 31 should precede this one to avoid above changes.

+   if (dev_priv->gt.awake) {
if (INTEL_GEN(dev_priv) >= 6)
gen6_rps_busy(dev_priv);
}
@@ -3283,9 +3285,35 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
i915_gem_reset_finish_engine(engine);
}
  
+	intel_gt_pm_sanitize(i915);

+
wake_up_all(>gpu_error.reset_queue);
  }
  
+static int load_power_context(struct drm_i915_private *i915)

+{
+   int err;
+
+   intel_gt_pm_sanitize(i915);
+   intel_gt_pm_enable_rps(i915);
+
+   err = i915_gem_switch_to_kernel_context(i915);
+   if (err)
+   goto err;
+
+   err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
+   if (err)
+   goto err;
+
+   intel_gt_pm_enable_rc6(i915);
+
+   return 0;
+
+err:
+   intel_gt_pm_sanitize(i915);
+   return err;
+}
+
  bool i915_gem_unset_wedged(struct drm_i915_private *i915)
  {
struct i915_gem_timeline *tl;
@@ -5007,7 +5035,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
intel_uc_resume(i915);
  
  	/* Always reload a context for powersaving. */

-   if (i915_gem_switch_to_kernel_context(i915))
+   if (load_power_context(i915))
goto err_wedged;
  
  out_unlock:

@@ -5194,11 +5222,8 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
goto err_active;
}
  
-	err = i915_gem_switch_to_kernel_context(i915);

-   if (err)
-   goto err_active;
-
-   err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
+   /* Flush the default context image to memory, and enable powersaving. */
+   err = load_power_context(i915);
if (err)
goto err_active;
  
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c

index 624c7cd207d2..6b589cffd00e 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -274,9 +274,6 @@ static void mark_busy(struct drm_i915_private *i915)
if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
i915->gt.epoch = 1;
  
-	intel_gt_pm_enable_rps(i915);

-   intel_gt_pm_enable_rc6(i915);
-
i915_update_gfx_val(i915);
if (INTEL_GEN(i915) >= 6)
gen6_rps_busy(i915);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 892c274eb47b..00e7f61fa8df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15426,9 +15426,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
flush_work(_priv->atomic_helper.free_work);
WARN_ON(!llist_empty(_priv->atomic_helper.free_list));
  
-	intel_gt_pm_disable_rps(dev_priv);

-   intel_gt_pm_disable_rc6(dev_priv);
-
/*
 * Interrupts and polling as the first thing to avoid creating havoc.
 * Too much stuff here 

Re: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6

[Sagar Arun Kamble]

On 3/16/2018 2:22 PM, Sagar Arun Kamble wrote:



On 3/14/2018 3:07 PM, Chris Wilson wrote:

Allow ourselves to individually toggle rps or rc6. This will be used
later when we want to enable rps/rc6 at different phases during the
device bring up.

Whilst here, convert the intel_$verb_gt_powersave over to
intel_gt_pm_$verb scheme.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>



+void intel_gt_pm_init(struct drm_i915_private *dev_priv)
  {
  struct intel_rps *rps = _priv->gt_pm.rps;
  @@ -2475,22 +2477,13 @@ void intel_init_gt_powersave(struct 
drm_i915_private *dev_priv)

  /* Finally allow us to boost to max by default */
  rps->boost_freq = rps->max_freq;
  -    mutex_unlock(>lock);
-}
-
-static inline void intel_enable_llc_pstate(struct drm_i915_private 
*i915)

-{
-    lockdep_assert_held(>gt_pm.rps.lock);
-
-    if (i915->gt_pm.llc_pstate.enabled)
-    return;
-
-    gen6_update_ring_freq(i915);
+    if (HAS_LLC(dev_priv))
+    gen6_update_ring_freq(dev_priv);
Ring frequency table update has to be done on resuming from sleep or 
reset as well hence we will

not required on resume from reset :)
need to possibly move it either __enable_rps or 
gt_pm_sanitize(provided we guard against "rps initialized")

Verified on my SKL system. Otherwise, patch looks good to me.

Thanks,
Sagar

  -    i915->gt_pm.llc_pstate.enabled = true;
+    mutex_unlock(>lock);
  }
  -static void intel_enable_rc6(struct drm_i915_private *dev_priv)
+static void __enable_rc6(struct drm_i915_private *dev_priv)
  {
  lockdep_assert_held(_priv->gt_pm.rps.lock);
  @@ -2511,7 +2504,7 @@ static void intel_enable_rc6(struct 
drm_i915_private *dev_priv)

  dev_priv->gt_pm.rc6.enabled = true;
  }
  -static void intel_enable_rps(struct drm_i915_private *dev_priv)
+static void __enable_rps(struct drm_i915_private *dev_priv)
  {
  struct intel_rps *rps = _priv->gt_pm.rps;
  @@ -2546,37 +2539,27 @@ static void intel_enable_rps(struct 
drm_i915_private *dev_priv)

  rps->enabled = true;
  }
  -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
  {
-    /* Powersaving is controlled by the host when inside a VM */
-    if (intel_vgpu_active(dev_priv))
+    if (!HAS_RC6(dev_priv))
  return;
    mutex_lock(_priv->gt_pm.rps.lock);
-
-    if (HAS_RC6(dev_priv))
-    intel_enable_rc6(dev_priv);
-    if (HAS_RPS(dev_priv))
-    intel_enable_rps(dev_priv);
-    if (HAS_LLC(dev_priv))
-    intel_enable_llc_pstate(dev_priv);
-
+    __enable_rc6(dev_priv);
  mutex_unlock(_priv->gt_pm.rps.lock);
  }
  -static inline void intel_disable_llc_pstate(struct 
drm_i915_private *i915)

+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
  {
-    lockdep_assert_held(>gt_pm.rps.lock);
-
-    if (!i915->gt_pm.llc_pstate.enabled)
+    if (!HAS_RPS(dev_priv))
  return;
  -    /* Currently there is no HW configuration to be done to 
disable. */

-
-    i915->gt_pm.llc_pstate.enabled = false;
+    mutex_lock(_priv->gt_pm.rps.lock);
+    __enable_rps(dev_priv);
+    mutex_unlock(_priv->gt_pm.rps.lock);
  }
  -static void intel_disable_rc6(struct drm_i915_private *dev_priv)
+static void __disable_rc6(struct drm_i915_private *dev_priv)
  {
  lockdep_assert_held(_priv->gt_pm.rps.lock);
  @@ -2595,7 +2578,14 @@ static void intel_disable_rc6(struct 
drm_i915_private *dev_priv)

  dev_priv->gt_pm.rc6.enabled = false;
  }
  -static void intel_disable_rps(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
+{
+    mutex_lock(_priv->gt_pm.rps.lock);
+    __disable_rc6(dev_priv);
+    mutex_unlock(_priv->gt_pm.rps.lock);
+}
+
+static void __disable_rps(struct drm_i915_private *dev_priv)
  {
  lockdep_assert_held(_priv->gt_pm.rps.lock);
  @@ -2616,19 +2606,14 @@ static void intel_disable_rps(struct 
drm_i915_private *dev_priv)

  dev_priv->gt_pm.rps.enabled = false;
  }
  -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
  {
  mutex_lock(_priv->gt_pm.rps.lock);
-
-    intel_disable_rc6(dev_priv);
-    intel_disable_rps(dev_priv);
-    if (HAS_LLC(dev_priv))
-    intel_disable_llc_pstate(dev_priv);
-
+    __disable_rps(dev_priv);
  mutex_unlock(_priv->gt_pm.rps.lock);
  }
  -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
  {
  if (IS_VALLEYVIEW(dev_priv))
  valleyview_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h 
b/drivers/gpu/drm/i915/intel_gt_pm.h

index 722325bbb6cc..5975c63f46bf 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -31,12 +31,16 @@ struct intel_rps_client;
  void in

Re: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Allow ourselves to individually toggle rps or rc6. This will be used
later when we want to enable rps/rc6 at different phases during the
device bring up.

Whilst here, convert the intel_$verb_gt_powersave over to
intel_gt_pm_$verb scheme.

Signed-off-by: Chris Wilson 



+void intel_gt_pm_init(struct drm_i915_private *dev_priv)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
  
@@ -2475,22 +2477,13 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)

/* Finally allow us to boost to max by default */
rps->boost_freq = rps->max_freq;
  
-	mutex_unlock(>lock);

-}
-
-static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
-{
-   lockdep_assert_held(>gt_pm.rps.lock);
-
-   if (i915->gt_pm.llc_pstate.enabled)
-   return;
-
-   gen6_update_ring_freq(i915);
+   if (HAS_LLC(dev_priv))
+   gen6_update_ring_freq(dev_priv);
Ring frequency table update has to be done on resuming from sleep or 
reset as well hence we will
need to possibly move it either __enable_rps or gt_pm_sanitize(provided 
we guard against "rps initialized")

Verified on my SKL system. Otherwise, patch looks good to me.

Thanks,
Sagar
  
-	i915->gt_pm.llc_pstate.enabled = true;

+   mutex_unlock(>lock);
  }
  
-static void intel_enable_rc6(struct drm_i915_private *dev_priv)

+static void __enable_rc6(struct drm_i915_private *dev_priv)
  {
lockdep_assert_held(_priv->gt_pm.rps.lock);
  
@@ -2511,7 +2504,7 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)

dev_priv->gt_pm.rc6.enabled = true;
  }
  
-static void intel_enable_rps(struct drm_i915_private *dev_priv)

+static void __enable_rps(struct drm_i915_private *dev_priv)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
  
@@ -2546,37 +2539,27 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)

rps->enabled = true;
  }
  
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)

+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
  {
-   /* Powersaving is controlled by the host when inside a VM */
-   if (intel_vgpu_active(dev_priv))
+   if (!HAS_RC6(dev_priv))
return;
  
  	mutex_lock(_priv->gt_pm.rps.lock);

-
-   if (HAS_RC6(dev_priv))
-   intel_enable_rc6(dev_priv);
-   if (HAS_RPS(dev_priv))
-   intel_enable_rps(dev_priv);
-   if (HAS_LLC(dev_priv))
-   intel_enable_llc_pstate(dev_priv);
-
+   __enable_rc6(dev_priv);
mutex_unlock(_priv->gt_pm.rps.lock);
  }
  
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)

+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
  {
-   lockdep_assert_held(>gt_pm.rps.lock);
-
-   if (!i915->gt_pm.llc_pstate.enabled)
+   if (!HAS_RPS(dev_priv))
return;
  
-	/* Currently there is no HW configuration to be done to disable. */

-
-   i915->gt_pm.llc_pstate.enabled = false;
+   mutex_lock(_priv->gt_pm.rps.lock);
+   __enable_rps(dev_priv);
+   mutex_unlock(_priv->gt_pm.rps.lock);
  }
  
-static void intel_disable_rc6(struct drm_i915_private *dev_priv)

+static void __disable_rc6(struct drm_i915_private *dev_priv)
  {
lockdep_assert_held(_priv->gt_pm.rps.lock);
  
@@ -2595,7 +2578,14 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)

dev_priv->gt_pm.rc6.enabled = false;
  }
  
-static void intel_disable_rps(struct drm_i915_private *dev_priv)

+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
+{
+   mutex_lock(_priv->gt_pm.rps.lock);
+   __disable_rc6(dev_priv);
+   mutex_unlock(_priv->gt_pm.rps.lock);
+}
+
+static void __disable_rps(struct drm_i915_private *dev_priv)
  {
lockdep_assert_held(_priv->gt_pm.rps.lock);
  
@@ -2616,19 +2606,14 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)

dev_priv->gt_pm.rps.enabled = false;
  }
  
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)

+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
  {
mutex_lock(_priv->gt_pm.rps.lock);
-
-   intel_disable_rc6(dev_priv);
-   intel_disable_rps(dev_priv);
-   if (HAS_LLC(dev_priv))
-   intel_disable_llc_pstate(dev_priv);
-
+   __disable_rps(dev_priv);
mutex_unlock(_priv->gt_pm.rps.lock);
  }
  
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)

+void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
  {
if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h 
b/drivers/gpu/drm/i915/intel_gt_pm.h
index 722325bbb6cc..5975c63f46bf 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -31,12 +31,16 @@ struct intel_rps_client;
  void intel_gpu_ips_init(struct 

Re: [Intel-gfx] [PATCH 26/36] drm/i915: Reorder GT interface code

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Try to order the intel_gt_pm code to match the order it is used:
init
enable
disable
cleanup

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_gt_pm.c | 170 ++---
  drivers/gpu/drm/i915/intel_gt_pm.h |   5 +-
  2 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c 
b/drivers/gpu/drm/i915/intel_gt_pm.c
index 42a048dca5bf..feb3bf060f78 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2383,6 +2383,18 @@ static void intel_init_emon(struct drm_i915_private 
*dev_priv)
dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
  }
  
+void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)

+{
+   dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+   dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
+   intel_disable_gt_powersave(dev_priv);
+
+   if (INTEL_GEN(dev_priv) < 11)
+   gen6_reset_rps_interrupts(dev_priv);
+   else
+   WARN_ON_ONCE(1);
+}
+
  void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
@@ -2466,91 +2478,6 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
mutex_unlock(>lock);
  }
  
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)

-{
-   if (IS_VALLEYVIEW(dev_priv))
-   valleyview_cleanup_gt_powersave(dev_priv);
-
-   if (!HAS_RC6(dev_priv))
-   intel_runtime_pm_put(dev_priv);
-}
-
-void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
-{
-   dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
-   dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
-   intel_disable_gt_powersave(dev_priv);
-
-   if (INTEL_GEN(dev_priv) < 11)
-   gen6_reset_rps_interrupts(dev_priv);
-   else
-   WARN_ON_ONCE(1);
-}
-
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
-{
-   lockdep_assert_held(>gt_pm.rps.lock);
-
-   if (!i915->gt_pm.llc_pstate.enabled)
-   return;
-
-   /* Currently there is no HW configuration to be done to disable. */
-
-   i915->gt_pm.llc_pstate.enabled = false;
-}
-
-static void intel_disable_rc6(struct drm_i915_private *dev_priv)
-{
-   lockdep_assert_held(_priv->gt_pm.rps.lock);
-
-   if (!dev_priv->gt_pm.rc6.enabled)
-   return;
-
-   if (INTEL_GEN(dev_priv) >= 9)
-   gen9_disable_rc6(dev_priv);
-   else if (IS_CHERRYVIEW(dev_priv))
-   cherryview_disable_rc6(dev_priv);
-   else if (IS_VALLEYVIEW(dev_priv))
-   valleyview_disable_rc6(dev_priv);
-   else if (INTEL_GEN(dev_priv) >= 6)
-   gen6_disable_rc6(dev_priv);
-
-   dev_priv->gt_pm.rc6.enabled = false;
-}
-
-static void intel_disable_rps(struct drm_i915_private *dev_priv)
-{
-   lockdep_assert_held(_priv->gt_pm.rps.lock);
-
-   if (!dev_priv->gt_pm.rps.enabled)
-   return;
-
-   if (INTEL_GEN(dev_priv) >= 9)
-   gen9_disable_rps(dev_priv);
-   else if (IS_CHERRYVIEW(dev_priv))
-   cherryview_disable_rps(dev_priv);
-   else if (IS_VALLEYVIEW(dev_priv))
-   valleyview_disable_rps(dev_priv);
-   else if (INTEL_GEN(dev_priv) >= 6)
-   gen6_disable_rps(dev_priv);
-   else if (INTEL_GEN(dev_priv) >= 5)
-   ironlake_disable_drps(dev_priv);
-
-   dev_priv->gt_pm.rps.enabled = false;
-}
-
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
-{
-   mutex_lock(_priv->gt_pm.rps.lock);
-
-   intel_disable_rc6(dev_priv);
-   intel_disable_rps(dev_priv);
-   if (HAS_LLC(dev_priv))
-   intel_disable_llc_pstate(dev_priv);
-
-   mutex_unlock(_priv->gt_pm.rps.lock);
-}
-
  static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
  {
lockdep_assert_held(>gt_pm.rps.lock);
@@ -2637,6 +2564,79 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
mutex_unlock(_priv->gt_pm.rps.lock);
  }
  
+static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)

+{
+   lockdep_assert_held(>gt_pm.rps.lock);
+
+   if (!i915->gt_pm.llc_pstate.enabled)
+   return;
+
+   /* Currently there is no HW configuration to be done to disable. */
+
+   i915->gt_pm.llc_pstate.enabled = false;
+}
+
+static void intel_disable_rc6(struct drm_i915_private *dev_priv)
+{
+   lockdep_assert_held(_priv->gt_pm.rps.lock);
+
+   if (!dev_priv->gt_pm.rc6.enabled)
+   return;
+
+   i

Re: [Intel-gfx] [PATCH 25/36] drm/i915: Remove defunct intel_suspend_gt_powersave()

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Since commit b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we
submit the first batch/context"), intel_suspend_gt_powersave() has been
a no-op. As we still do not need to do anything explicitly on suspend
(we do everything required on idling), remove the defunct function.

References: b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we submit the 
first batch/context")
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_gem.c|  1 -
  drivers/gpu/drm/i915/intel_gt_pm.c | 16 
  drivers/gpu/drm/i915/intel_gt_pm.h |  1 -
  3 files changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fbf8ccf57229..8112cbd6e0af 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4908,7 +4908,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
int ret;
  
  	intel_runtime_pm_get(dev_priv);

-   intel_suspend_gt_powersave(dev_priv);
  
  	mutex_lock(>struct_mutex);
  
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c

index 21217a5c585a..42a048dca5bf 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2475,22 +2475,6 @@ void intel_cleanup_gt_powersave(struct drm_i915_private 
*dev_priv)
intel_runtime_pm_put(dev_priv);
  }
  
-/**

- * intel_suspend_gt_powersave - suspend PM work and helper threads
- * @dev_priv: i915 device
- *
- * We don't want to disable RC6 or other features here, we just want
- * to make sure any work we've queued has finished and won't bother
- * us while we're suspended.
- */
-void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
-{
-   if (INTEL_GEN(dev_priv) < 6)
-   return;
-
-   /* gen6_rps_idle() will be called later to disable interrupts */
-}
-
  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
  {
dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h 
b/drivers/gpu/drm/i915/intel_gt_pm.h
index 5ac16b614f8b..c0b3ab5e4046 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -36,7 +36,6 @@ void intel_cleanup_gt_powersave(struct drm_i915_private 
*dev_priv);
  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
  void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
  void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
  
  void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
  


--
Thanks,
Sagar

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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 24/36] drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

For consistency (and elegance!), add intel_device_info.has_rps.
The immediate boon is that RPS support is now emitted along the other
capabilities in the debug log and after errors.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
  drivers/gpu/drm/i915/i915_pci.c  |  6 ++
  drivers/gpu/drm/i915/intel_device_info.h |  1 +
  drivers/gpu/drm/i915/intel_gt_pm.c   | 20 
  4 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c9cb2f9188b..825a6fd8423b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2559,6 +2559,8 @@ intel_info(const struct drm_i915_private *dev_priv)
  #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
  #define HAS_RC6pp(dev_priv)(false) /* HW was never validated */
  
+#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)

+
  #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
  
  #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 062e91b39085..b2f4c783d8e9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -235,6 +235,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
.is_mobile = 1, .has_fbc = 1,
+   .has_rps = true,
  };
  
  #define GEN6_FEATURES \

@@ -246,6 +247,7 @@ static const struct intel_device_info intel_ironlake_m_info 
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+   .has_rps = true, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -290,6 +292,7 @@ static const struct intel_device_info 
intel_sandybridge_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+   .has_rps = true, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -343,6 +346,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
.has_psr = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
+   .has_rps = true,
.has_gmch_display = 1,
.has_hotplug = 1,
.has_aliasing_ppgtt = 1,
@@ -437,6 +441,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.has_runtime_pm = 1,
.has_resource_streamer = 1,
.has_rc6 = 1,
+   .has_rps = true,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
.has_aliasing_ppgtt = 1,
@@ -510,6 +515,7 @@ static const struct intel_device_info 
intel_skylake_gt4_info = {
.has_csr = 1, \
.has_resource_streamer = 1, \
.has_rc6 = 1, \
+   .has_rps = true, \
.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index df014ade1847..9704f4c6cdeb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -103,6 +103,7 @@ enum intel_platform {
func(has_psr); \
func(has_rc6); \
func(has_rc6p); \
+   func(has_rps); \
func(has_resource_streamer); \
func(has_runtime_pm); \
func(has_snoop); \
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c 
b/drivers/gpu/drm/i915/intel_gt_pm.c
index 0cf13e786fe6..21217a5c585a 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -710,6 +710,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
  
+	if (!HAS_RPS(dev_priv))

+   return;
+
mutex_lock(>lock);
if (rps->enabled) {
u8 freq;
@@ -740,6 +743,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
  {
struct intel_rps *rps = _priv->gt_pm.rps;
  
+	if (!HAS_RPS(dev_priv))

+   return;
+
/*
 * Flush our bottom-half so that it does not race with us
 * setting the idle frequency and so that it is bounded by
@@ -767,6 +773,9 @@ void gen6_rps_boost(struct i915_request *rq, struct 
intel_rps_client *client)
unsigned long flags;
bool boost;
  
+	if (!HAS_RPS(rq->i915))

+   return;
+
/*
 * This is intentionally racy! We peek at the state here, then
 * validate inside the RPS worker.
@@ -909,8 +918,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
struct intel_device_info *info = mkwrite_device_info(i915);
  
  	/* Powersaving is controlled by the host when inside a VM

Re: [Intel-gfx] [PATCH 23/36] drm/i915: Move all the RPS irq handlers to intel_gt_pm

[Sagar Arun Kamble]

As per discussion with Michal w.r.t moving GuC interrupt handling 
functions to intel_guc|_interrupt.c, I agreed that
since most functions (gen9_*_guc_interrupts) are touching dev_priv level 
interrupt registers we should keep them  in i915_irq.c
Handler for rps can be created and be in gt_pm.c like in this patch but 
gen*_*_rps|guc_interrupts need to be in i915_irq.c.


And if we want to move them below change is needed:
gen9_guc_irq_handler is left in i915_irq.c and gen9_*_guc_interrupts 
declarations are in i915_drv.h.


Thanks,
Sagar

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Since all the RPS handling code is in intel_gt_pm, move the irq handlers
there as well so that it all contained within one file.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_drv.h |  10 +-
  drivers/gpu/drm/i915/i915_irq.c | 287 
  drivers/gpu/drm/i915/intel_drv.h|   5 -
  drivers/gpu/drm/i915/intel_gt_pm.c  | 223 -
  drivers/gpu/drm/i915/intel_gt_pm.h  |   5 +
  drivers/gpu/drm/i915/intel_ringbuffer.c |   1 +
  6 files changed, 260 insertions(+), 271 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a57b20f95cdc..7c9cb2f9188b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -743,6 +743,9 @@ struct intel_rps {
/* PM interrupt bits that should never be masked */
u32 pm_intrmsk_mbz;
  
+	u32 pm_events;

+   u32 guc_events;
+
/* Frequencies are stored in potentially platform dependent multiples.
 * In other words, *_freq needs to be multiplied by X to be interesting.
 * Soft limits are those which are used for the dynamic reclocking done
@@ -793,6 +796,9 @@ struct intel_gen6_power_mgmt {
struct intel_rps rps;
struct intel_rc6 rc6;
struct intel_llc_pstate llc_pstate;
+
+   u32 imr;
+   u32 ier;
  };
  
  /* defined intel_pm.c */

@@ -1641,10 +1647,6 @@ struct drm_i915_private {
u32 de_irq_mask[I915_MAX_PIPES];
};
u32 gt_irq_mask;
-   u32 pm_imr;
-   u32 pm_ier;
-   u32 pm_rps_events;
-   u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
  
  	struct i915_hotplug hotplug;

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d9cf4f81979e..dfb711ca4d27 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -33,9 +33,11 @@
  #include 
  #include 
  #include 
+
  #include "i915_drv.h"
  #include "i915_trace.h"
  #include "intel_drv.h"
+#include "intel_gt_pm.h"
  
  /**

   * DOC: interrupt handling
@@ -202,7 +204,6 @@ static void gen2_assert_iir_is_zero(struct drm_i915_private 
*dev_priv,
POSTING_READ16(type##IMR); \
  } while (0)
  
-static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

  static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
  
  /* For display hotplug interrupt */

@@ -306,194 +307,6 @@ void gen5_disable_gt_irq(struct drm_i915_private 
*dev_priv, uint32_t mask)
ilk_update_gt_irq(dev_priv, mask, 0);
  }
  
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)

-{
-   return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
-}
-
-static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
-{
-   return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
-}
-
-static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
-{
-   return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
-}
-
-/**
- * snb_update_pm_irq - update GEN6_PMIMR
- * @dev_priv: driver private
- * @interrupt_mask: mask of interrupt bits to update
- * @enabled_irq_mask: mask of interrupt bits to enable
- */
-static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
- uint32_t interrupt_mask,
- uint32_t enabled_irq_mask)
-{
-   uint32_t new_val;
-
-   WARN_ON(enabled_irq_mask & ~interrupt_mask);
-
-   lockdep_assert_held(_priv->irq_lock);
-
-   new_val = dev_priv->pm_imr;
-   new_val &= ~interrupt_mask;
-   new_val |= (~enabled_irq_mask & interrupt_mask);
-
-   if (new_val != dev_priv->pm_imr) {
-   dev_priv->pm_imr = new_val;
-   I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
-   POSTING_READ(gen6_pm_imr(dev_priv));
-   }
-}
-
-void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-   if (WARN_ON(!intel_irqs_enabled(dev_priv)))
-   return;
-
-   snb_update_pm_irq(dev_priv, mask, mask);
-}
-
-static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-   snb_update_pm_irq(dev_priv, mask, 0);
-}
-
-void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-   if (WARN_ON(!intel_irqs_enabled(dev_priv)))
-  

Re: [Intel-gfx] [PATCH 22/36] drm/i915: Move rps worker to intel_gt_pm.c

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

The RPS worker exists to do the bidding of the GT powermanagement, so
move it from i915_irq to intel_gt_pm.c where it can be hidden from the
rest of the world. The goal being that the RPS worker is the one true
way though which all RPS updates are coordinated.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.h|   1 -
  drivers/gpu/drm/i915/i915_irq.c| 141 
  drivers/gpu/drm/i915/i915_sysfs.c  |  38 ++--
  drivers/gpu/drm/i915/intel_gt_pm.c | 186 ++---
  drivers/gpu/drm/i915/intel_gt_pm.h |   1 -
  5 files changed, 162 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5c10acf767a8..a57b20f95cdc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3406,7 +3406,6 @@ extern void i915_redisable_vga(struct drm_i915_private 
*dev_priv);
  extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
  extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
  extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
-extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
  extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  bool enable);
  
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c

index f815da0dd991..d9cf4f81979e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1130,145 +1130,6 @@ static void notify_ring(struct intel_engine_cs *engine)
trace_intel_engine_notify(engine, wait);
  }
  
-static void vlv_c0_read(struct drm_i915_private *dev_priv,

-   struct intel_rps_ei *ei)
-{
-   ei->ktime = ktime_get_raw();
-   ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
-   ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
-}
-
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
-{
-   memset(_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
-}
-
-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
-{
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   const struct intel_rps_ei *prev = >ei;
-   struct intel_rps_ei now;
-   u32 events = 0;
-
-   if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
-   return 0;
-
-   vlv_c0_read(dev_priv, );
-
-   if (prev->ktime) {
-   u64 time, c0;
-   u32 render, media;
-
-   time = ktime_us_delta(now.ktime, prev->ktime);
-
-   time *= dev_priv->czclk_freq;
-
-   /* Workload can be split between render + media,
-* e.g. SwapBuffers being blitted in X after being rendered in
-* mesa. To account for this we need to combine both engines
-* into our activity counter.
-*/
-   render = now.render_c0 - prev->render_c0;
-   media = now.media_c0 - prev->media_c0;
-   c0 = max(render, media);
-   c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
-
-   if (c0 > time * rps->up_threshold)
-   events = GEN6_PM_RP_UP_THRESHOLD;
-   else if (c0 < time * rps->down_threshold)
-   events = GEN6_PM_RP_DOWN_THRESHOLD;
-   }
-
-   rps->ei = now;
-   return events;
-}
-
-static void gen6_pm_rps_work(struct work_struct *work)
-{
-   struct drm_i915_private *dev_priv =
-   container_of(work, struct drm_i915_private, gt_pm.rps.work);
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   bool client_boost = false;
-   int new_delay, adj, min, max;
-   u32 pm_iir = 0;
-
-   spin_lock_irq(_priv->irq_lock);
-   if (rps->interrupts_enabled) {
-   pm_iir = fetch_and_zero(>pm_iir);
-   client_boost = atomic_read(>num_waiters);
-   }
-   spin_unlock_irq(_priv->irq_lock);
-
-   /* Make sure we didn't queue anything we're not going to process. */
-   WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
-   if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
-   goto out;
-
-   mutex_lock(>lock);
-
-   pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
-
-   adj = rps->last_adj;
-   new_delay = rps->cur_freq;
-   min = rps->min_freq_softlimit;
-   max = rps->max_freq_softlimit;
-   if (client_boost)
-   max = rps->max_freq;
-   if (client_boost && new_delay < rps->boost_freq) {
-   new_delay = rps->boost_freq;
-   adj = 0;
-   } else if (pm_iir & GEN6_PM_RP_UP_THRESHO

Re: [Intel-gfx] [PATCH 21/36] drm/i915: Split GT powermanagement functions to intel_gt_pm.c

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

intel_pm.c has grown to several thousand lines of loosely connected code
handling various powermanagement tasks. Split out the GT portion (IPS,
RPS and RC6) into its own file for easier maintenance.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>



diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c 
b/drivers/gpu/drm/i915/intel_gt_pm.c
new file mode 100644
index ..763bf9378ae8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -0,0 +1,2422 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2012-2018 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include "../../../platform/x86/intel_ips.h"
+
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_gt_pm.h"
I think intel_gt_pm.h should be the first include as we have been on GuC 
side refactoring

+#include "intel_sideband.h"
+
+/**
+ * DOC: RC6
+ *
+ * RC6 is a special power stage which allows the GPU to enter an very
+ * low-voltage mode when idle, using down to 0V while at this stage.  This
+ * stage is entered automatically when the GPU is idle when RC6 support is
+ * enabled, and as soon as new workload arises GPU wakes up automatically as
+ * well.
+ *
+ * There are different RC6 modes available in Intel GPU, which differentiate
+ * among each other with the latency required to enter and leave RC6 and
+ * voltage consumed by the GPU in different states.
+ *
+ * The combination of the following flags define which states GPU is allowed
+ * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
+ * RC6pp is deepest RC6. Their support by hardware varies according to the
+ * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
+ * which brings the most power savings; deeper states save more power, but
+ * require higher latency to switch to and wake up.
+ */
+

...

diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h 
b/drivers/gpu/drm/i915/intel_gt_pm.h
new file mode 100644
index ..ab4f73a39ce6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+

Need SPDX License identifier here.
Thanks for many checkpatch/comment fixes. Few more are still flagged.
Otherwise change looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

+#ifndef __INTEL_GT_PM_H__
+#define __INTEL_GT_PM_H__
+
+struct drm_i915_private;
+struct i915_request;
+struct intel_rps_client;
+
+void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
+void intel_gpu_ips_teardown(void);
+
+void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
+
+void gen6_rps_busy(struct drm_i915_private *dev_priv);
+void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
+void gen6_rps_idle(struct drm_i915_private *dev_priv);
+void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
+
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
+
+#endif /* __INTEL_GT_PM_H__ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a2ebf66ff9ed..0bbee12bee41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -34,27 +34,6 @@
  #include "i915_drv.h"
  #include "intel_drv.h"
  #include "intel_sideband.h"
-#include "../../../platform/x86/intel_ips.h"
-
-/**
- *

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

[Sagar Arun Kamble]

i915_mch_val() called from i915_emon_status debugfs is not protected 
under rpm_get and mchdev_lock.

Can that also be updated as part of this patch.

Thanks,
Sagar

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.

As this involved adding a potentially sleeping rpm_get, we have to
rearrange the spinlocks slightly and so switch to acquiring a device-ref
under the spinlock rather than hold the spinlock for the whole
operation. To be consistent, we make the change in pattern common to the
intel_ips interface even though this adds a few more atomic operations
than necessary in a few cases.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_drv.c |   3 +
  drivers/gpu/drm/i915/intel_pm.c | 138 
  2 files changed, 73 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3d0b7353fb09..5c28990aab7f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1440,6 +1440,9 @@ void i915_driver_unload(struct drm_device *dev)
  
  	i915_driver_unregister(dev_priv);
  
+	/* Flush any external code that still may be under the RCU lock */

+   synchronize_rcu();
+
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
  
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c

index 447811c5be35..a2ebf66ff9ed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5930,10 +5930,6 @@ void intel_init_ipc(struct drm_i915_private *dev_priv)
   */
  DEFINE_SPINLOCK(mchdev_lock);
  
-/* Global for IPS driver to get at the current i915 device. Protected by

- * mchdev_lock. */
-static struct drm_i915_private *i915_mch_dev;
-
  bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
  {
u16 rgvswctl;
@@ -7577,11 +7573,13 @@ unsigned long i915_chipset_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return 0;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	val = __i915_chipset_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  
  	return val;

  }
@@ -7661,11 +7659,13 @@ void i915_update_gfx_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	__i915_update_gfx_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  }
  
  static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)

@@ -7712,15 +7712,32 @@ unsigned long i915_gfx_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return 0;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	val = __i915_gfx_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  
  	return val;

  }
  
+static struct drm_i915_private *i915_mch_dev;

+
+static struct drm_i915_private *mchdev_get(void)
+{
+   struct drm_i915_private *i915;
+
+   rcu_read_lock();
+   i915 = i915_mch_dev;
+   if (!kref_get_unless_zero(>drm.ref))
+   i915 = NULL;
+   rcu_read_unlock();
+
+   return i915;
+}
+
  /**
   * i915_read_mch_val - return value for IPS use
   *
@@ -7729,23 +7746,22 @@ unsigned long i915_gfx_val(struct drm_i915_private 
*dev_priv)
   */
  unsigned long i915_read_mch_val(void)
  {
-   struct drm_i915_private *dev_priv;
-   unsigned long chipset_val, graphics_val, ret = 0;
-
-   spin_lock_irq(_lock);
-   if (!i915_mch_dev)
-   goto out_unlock;
-   dev_priv = i915_mch_dev;
-
-   chipset_val = __i915_chipset_val(dev_priv);
-   graphics_val = __i915_gfx_val(dev_priv);
+   struct drm_i915_private *i915;
+   unsigned long chipset_val, graphics_val;
  
-	ret = chipset_val + graphics_val;

+   i915 = mchdev_get();
+   if (!i915)
+   return 0;
  
-out_unlock:

+   intel_runtime_pm_get(i915);
+   spin_lock_irq(_lock);
+   chipset_val = __i915_chipset_val(i915);
+   graphics_val = __i915_gfx_val(i915);
spin_unlock_irq(_lock);
+   intel_runtime_pm_put(i915);
  
-	return ret;

+   drm_dev_put(>drm);
+   return chipset_val + graphics_val;
  }
  EXPORT_SYMBOL_GPL(i915_read_mch_val);
  
@@ -7756,23 +7772,19 @@ EXPORT_SYMBOL_GPL(i915_read_mch_val);

   */
  bool i915_gpu_raise(void)
  {
-   struct drm_i915_private *dev_priv;
-   bool ret = true;
-
-   spin_lock_irq(_lock);
-   if (!i915_mch_dev) {
-   ret = false;
-   goto out_unlock;
-   }
- 

Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.

As this involved adding a potentially sleeping rpm_get, we have to
rearrange the spinlocks slightly and so switch to acquiring a device-ref
under the spinlock rather than hold the spinlock for the whole
operation. To be consistent, we make the change in pattern common to the
intel_ips interface even though this adds a few more atomic operations
than necessary in a few cases.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_drv.c |   3 +
  drivers/gpu/drm/i915/intel_pm.c | 138 
  2 files changed, 73 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3d0b7353fb09..5c28990aab7f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1440,6 +1440,9 @@ void i915_driver_unload(struct drm_device *dev)
  
  	i915_driver_unregister(dev_priv);
  
+	/* Flush any external code that still may be under the RCU lock */

+   synchronize_rcu();
+

Hi Chris,

Will this rcu change be equivalent to

rcu_assign_pointer(i915_mch_dev, dev_priv) in gpu_ips_init
rcu_assign_pointer(i915_mch_dev, NULL) in gpu_ips_teardown

eliminating smp_store_mb from init/teardown and synchronize_rcu here.

Thanks,
Sagar

if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
  
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c

index 447811c5be35..a2ebf66ff9ed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5930,10 +5930,6 @@ void intel_init_ipc(struct drm_i915_private *dev_priv)
   */
  DEFINE_SPINLOCK(mchdev_lock);
  
-/* Global for IPS driver to get at the current i915 device. Protected by

- * mchdev_lock. */
-static struct drm_i915_private *i915_mch_dev;
-
  bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
  {
u16 rgvswctl;
@@ -7577,11 +7573,13 @@ unsigned long i915_chipset_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return 0;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	val = __i915_chipset_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  
  	return val;

  }
@@ -7661,11 +7659,13 @@ void i915_update_gfx_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	__i915_update_gfx_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  }
  
  static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)

@@ -7712,15 +7712,32 @@ unsigned long i915_gfx_val(struct drm_i915_private 
*dev_priv)
if (!IS_GEN5(dev_priv))
return 0;
  
+	intel_runtime_pm_get(dev_priv);

spin_lock_irq(_lock);
  
  	val = __i915_gfx_val(dev_priv);
  
  	spin_unlock_irq(_lock);

+   intel_runtime_pm_put(dev_priv);
  
  	return val;

  }
  
+static struct drm_i915_private *i915_mch_dev;

+
+static struct drm_i915_private *mchdev_get(void)
+{
+   struct drm_i915_private *i915;
+
+   rcu_read_lock();
+   i915 = i915_mch_dev;
+   if (!kref_get_unless_zero(>drm.ref))
+   i915 = NULL;
+   rcu_read_unlock();
+
+   return i915;
+}
+
  /**
   * i915_read_mch_val - return value for IPS use
   *
@@ -7729,23 +7746,22 @@ unsigned long i915_gfx_val(struct drm_i915_private 
*dev_priv)
   */
  unsigned long i915_read_mch_val(void)
  {
-   struct drm_i915_private *dev_priv;
-   unsigned long chipset_val, graphics_val, ret = 0;
-
-   spin_lock_irq(_lock);
-   if (!i915_mch_dev)
-   goto out_unlock;
-   dev_priv = i915_mch_dev;
-
-   chipset_val = __i915_chipset_val(dev_priv);
-   graphics_val = __i915_gfx_val(dev_priv);
+   struct drm_i915_private *i915;
+   unsigned long chipset_val, graphics_val;
  
-	ret = chipset_val + graphics_val;

+   i915 = mchdev_get();
+   if (!i915)
+   return 0;
  
-out_unlock:

+   intel_runtime_pm_get(i915);
+   spin_lock_irq(_lock);
+   chipset_val = __i915_chipset_val(i915);
+   graphics_val = __i915_gfx_val(i915);
spin_unlock_irq(_lock);
+   intel_runtime_pm_put(i915);
  
-	return ret;

+   drm_dev_put(>drm);
+   return chipset_val + graphics_val;
  }
  EXPORT_SYMBOL_GPL(i915_read_mch_val);
  
@@ -7756,23 +7772,19 @@ EXPORT_SYMBOL_GPL(i915_read_mch_val);

   */
  bool i915_gpu_raise(void)
  {
-   struct drm_i915_private *dev_priv;
-   bool ret = true;
-
-   spin_lock_irq(_lock);
-   

Re: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.

Signed-off-by: Chris Wilson 



-u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)

vlv_flisdsi_read declaration can be removed from sideband.h

+void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
+enum intel_sbi_destination destination)
  {
-   u32 val = 0;
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
-   reg, );
-   return val;
+   intel_sbi_rw(dev_priv, reg, destination, , false);
  }
  
  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH 10/36] drm/i915: Replace pcu_lock with sb_lock

[Sagar Arun Kamble]

if (intel_set_rps(dev_priv, val))
DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
  
-	mutex_unlock(_priv->pcu_lock);

-
-   return 0;
+unlock:
+   mutex_unlock(>lock);
+   return ret;
  }
  
  DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,

@@ -4230,7 +4215,7 @@ i915_min_freq_set(void *data, u64 val)
  
  	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
  
-	ret = mutex_lock_interruptible(_priv->pcu_lock);

+   ret = mutex_lock_interruptible(>lock);
if (ret)
return ret;
  
@@ -4244,8 +4229,8 @@ i915_min_freq_set(void *data, u64 val)
  
  	if (val < hw_min ||

val > hw_max || val > rps->max_freq_softlimit) {
-   mutex_unlock(_priv->pcu_lock);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto unlock;
}
  
  	rps->min_freq_softlimit = val;

@@ -4253,9 +4238,9 @@ i915_min_freq_set(void *data, u64 val)
if (intel_set_rps(dev_priv, val))
DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
  
-	mutex_unlock(_priv->pcu_lock);

-
-   return 0;
+unlock:
+   mutex_unlock(>lock);
+   return ret;
  }
  
  DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 67cf0fe533f8..1f246d2a4e84 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -735,6 +735,8 @@ struct intel_rps_ei {
  };
  
  struct intel_rps {

+   struct mutex lock;
+

I think this lock can now become part of struct intel_gt_pm.

/*
 * work, interrupts_enabled and pm_iir are protected by
 * dev_priv->irq_lock
@@ -1783,14 +1785,6 @@ struct drm_i915_private {
/* Cannot be determined by PCIID. You must always read a register. */
u32 edram_cap;
  
-	/*

-* Protects RPS/RC6 register access and PCU communication.
-* Must be taken after struct_mutex if nested. Note that
-* this lock may be held for long periods of time when
-* talking to hw - so only take it when talking to hw!
-*/
-   struct mutex pcu_lock;
-
/* gen6+ GT PM state */
struct intel_gen6_power_mgmt gt_pm;
  

...

-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
-   u32 mbox, u32 val,
-   int fast_timeout_us, int slow_timeout_ms)
+static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
+u32 mbox, u32 val,
+int fast_timeout_us,
+        int slow_timeout_ms)
  {
int status;
  
-	WARN_ON(!mutex_is_locked(_priv->pcu_lock));

-

lockdep_assert is missed here.

With this change, patch looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

/* GEN6_PCODE_* are outside of the forcewake domain, we can
 * use te fw I915_READ variants to reduce the amount of work
 * required when reading/writing.
 */
  
-	if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {

-   DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) 
mailbox access failed for %ps\n",
-val, mbox, __builtin_return_address(0));
+   if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
return -EAGAIN;
-   }
  
  	I915_WRITE_FW(GEN6_PCODE_DATA, val);

I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
@@ -9290,11 +9273,8 @@ int sandybridge_pcode_write_timeout(struct 
drm_i915_private *dev_priv,
if (__intel_wait_for_register_fw(dev_priv,
 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 
0,
 fast_timeout_us, slow_timeout_ms,
-NULL)) {
-   DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to 
finish for %ps\n",
- val, mbox, __builtin_return_address(0));
+NULL))
return -ETIMEDOUT;
-   }
  
  	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
  
@@ -9303,13 +9283,28 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,

else
status = gen6_check_mailbox_status(dev_priv);
  
+	return status;

+}
+
+int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
+   u32 mbox, u32 val,
+   int fast_timeout_us,
+   int slow_timeout_ms)
+{
+   int status;
+
+   mutex_lock(_priv->sb_lock);
+   status = __sandybridge_pcode_write_timeout(dev_priv, mbox, val,
+  

Re: [Intel-gfx] [PATCH 08/36] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

Valleyview and Cherryview update the GPU frequency via the punit, which
is very expensive as we have to ensure the cores do not sleep during the
comms.

But the patch 5 applies this workaround to only VLV.

If we perform frequent RPS evaluations, the frequent punit
requests cause measurable system overhead for little benefit, so
increase the evaluation intervals to reduce the number of times we try
and change frequency.

Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/intel_pm.c | 13 +
  1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b1a73fc7f3e8..9de7d53aa4d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6165,6 +6165,19 @@ static void gen6_set_rps_thresholds(struct 
drm_i915_private *dev_priv, u8 val)
break;
}
  
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

+   /*
+* Baytrail and Braswell control the gpu frequency via the
+* punit, which is very slow and expensive to communicate with,
+* as we synchronously force the package to C0. If we try and
+* update the gpufreq too often we cause measurable system
+* load for little benefit (effectively stealing CPU time for
+* the GPU, negatively impacting overall throughput).
+*/
+   ei_up <<= 2;
+   ei_down <<= 2;
+   }
+
/* When byt can survive without system hang with dynamic
 * sw freq adjustments, this restriction can be lifted.
 */


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v2] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

[Sagar Arun Kamble]

Are we required to add reference to intel_guc.c and intel_wopcm.c in 
Documentation/gpu/i915.rst?



On 3/15/2018 12:14 AM, Jackie Li wrote:

GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
sphinx build if not using proper reST syntax.

This patch uses reST literal blocks to make sure GuC Address Space and
WOPCM Layout diagrams to be generated correctly, and it also corrects some
errors in the diagram description.

v2:
  - Fixed errors in diagram description

Signed-off-by: Jackie Li <yaodong...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
---
  drivers/gpu/drm/i915/intel_guc.c   | 52 --
  drivers/gpu/drm/i915/intel_wopcm.c | 44 +---
  2 files changed, 50 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3eb516e..6a4f36e 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -495,35 +495,37 @@ int intel_guc_resume(struct intel_guc *guc)
  /**
   * DOC: GuC Address Space
   *
- * The layout of GuC address space is shown as below:
+ * The layout of GuC address space is shown below:
   *
- *+==> ++ <== GUC_GGTT_TOP
- *^||
- *|||
- *||DRAM|
- *||   Memory   |
- *|||
- *   GuC   ||
- * Address  +> ++ <== WOPCM Top
- *  Space   ^  |   HW contexts RSVD |
- *| |  |WOPCM   |
- *| | +==> ++ <== GuC WOPCM Top
- *|GuC^||
- *|GGTT   |||
- *|Pin   GuC   |GuC |
- *|Bias WOPCM  |   WOPCM|
- *| |Size  ||
- *| | |||
- *v v v||
- *+=+=+==> ++ <== GuC WOPCM Base
- * |   Non-GuC WOPCM|
- * |   (HuC/Reserved)   |
- * ++ <== WOPCM Base
+ * ::
+ *
+ * +==> ++ <== GUC_GGTT_TOP
+ * ^||
+ * |||
+ * ||DRAM|
+ * ||   Memory   |
+ * |||
+ *GuC   ||
+ *  Address  +> ++ <== WOPCM Top
+ *   Space   ^  |   HW contexts RSVD |
+ * | |  |WOPCM   |
+ * | | +==> ++ <== GuC WOPCM Top
+ * |GuC^||
+ * |GGTT   |||
+ * |Pin   GuC   |GuC |
+ * |Bias WOPCM  |   WOPCM|
+ * | |Size  ||
+ * | | |||
+ * v v v||
+ * +=+=+==> ++ <== GuC WOPCM Base
+ *  |   Non-GuC WOPCM|
+ *  |   (HuC/Reserved)   |
+ *  ++ <== WOPCM Base
   *
   * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of
   * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value 
of
- * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is
- * set in GUC_WOPCM_SIZE register.
+ * the GuC ggtt_pin_bias is determined by the GuC WOPCM size which is set in
+ * GUC_WOPCM_SIZE register.
   */
  
  /**

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/intel_wopcm.c
index 4117886..74bf76f 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -11,28 +11,30 @@
   * DOC: WOPCM Layout
   *
   * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
- * offset registers whose are calculated are determined by size of HuC/GuC
- * firmware size and set of hw requirements/restrictions as shown below:
+ * offset registers whose values are calculated and determined by HuC/GuC
+ * firmware size and set of hardware requirements/restrictions as shown below:
   *
- *   +=> ++ <== WOPCM Top
- *   ^   |  HW contexts RSVD  |
- *   | +===> ++ <== GuC WOPCM Top
- *   | ^ ||
- *   | | ||
- *   | | ||
- *   |

Re: [Intel-gfx] [PATCH 20/36] drm/i915: Remove obsolete min/max freq setters from debugfs

[Sagar Arun Kamble]

On 3/14/2018 3:07 PM, Chris Wilson wrote:

A more complete, and more importantly stable, interface for controlling
the RPS frequency range is available in sysfs, obsoleting the unstable
debugfs.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

(I'm assuming we don't want to mention "getters" in subject as it is 
trivial and obvious :) )

---
  drivers/gpu/drm/i915/i915_debugfs.c | 115 
  1 file changed, 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5965df3e6215..034fb7cfc80e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4136,119 +4136,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
i915_drop_caches_get, i915_drop_caches_set,
"0x%08llx\n");
  
-static int

-i915_max_freq_get(void *data, u64 *val)
-{
-   struct drm_i915_private *dev_priv = data;
-
-   if (INTEL_GEN(dev_priv) < 6)
-   return -ENODEV;
-
-   *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
-   return 0;
-}
-
-static int
-i915_max_freq_set(void *data, u64 val)
-{
-   struct drm_i915_private *dev_priv = data;
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   u32 hw_max, hw_min;
-   int ret;
-
-   if (INTEL_GEN(dev_priv) < 6)
-   return -ENODEV;
-
-   DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
-
-   ret = mutex_lock_interruptible(>lock);
-   if (ret)
-   return ret;
-
-   /*
-* Turbo will still be enabled, but won't go above the set value.
-*/
-   val = intel_freq_opcode(dev_priv, val);
-
-   hw_max = rps->max_freq;
-   hw_min = rps->min_freq;
-
-   if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
-   ret = -EINVAL;
-   goto unlock;
-   }
-
-   rps->max_freq_softlimit = val;
-
-   if (intel_set_rps(dev_priv, val))
-   DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
-
-unlock:
-   mutex_unlock(>lock);
-   return ret;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
-   i915_max_freq_get, i915_max_freq_set,
-   "%llu\n");
-
-static int
-i915_min_freq_get(void *data, u64 *val)
-{
-   struct drm_i915_private *dev_priv = data;
-
-   if (INTEL_GEN(dev_priv) < 6)
-   return -ENODEV;
-
-   *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
-   return 0;
-}
-
-static int
-i915_min_freq_set(void *data, u64 val)
-{
-   struct drm_i915_private *dev_priv = data;
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   u32 hw_max, hw_min;
-   int ret;
-
-   if (INTEL_GEN(dev_priv) < 6)
-   return -ENODEV;
-
-   DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
-
-   ret = mutex_lock_interruptible(>lock);
-   if (ret)
-   return ret;
-
-   /*
-* Turbo will still be enabled, but won't go below the set value.
-*/
-   val = intel_freq_opcode(dev_priv, val);
-
-   hw_max = rps->max_freq;
-   hw_min = rps->min_freq;
-
-   if (val < hw_min ||
-   val > hw_max || val > rps->max_freq_softlimit) {
-   ret = -EINVAL;
-   goto unlock;
-   }
-
-   rps->min_freq_softlimit = val;
-
-   if (intel_set_rps(dev_priv, val))
-   DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
-
-unlock:
-   mutex_unlock(>lock);
-   return ret;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
-   i915_min_freq_get, i915_min_freq_set,
-   "%llu\n");
-
  static int
  i915_cache_sharing_get(void *data, u64 *val)
  {
@@ -4749,8 +4636,6 @@ static const struct i915_debugfs_files {
const struct file_operations *fops;
  } i915_debugfs_files[] = {
{"i915_wedged", _wedged_fops},
-   {"i915_max_freq", _max_freq_fops},
-   {"i915_min_freq", _min_freq_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_ring_missed_irq", _ring_missed_irq_fops},
{"i915_ring_test_irq", _ring_test_irq_fops},


--
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Sagar

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Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

[Sagar Arun Kamble]

On 3/14/2018 2:33 PM, Chris Wilson wrote:

Quoting Sagar Arun Kamble (2018-03-14 08:15:15)


On 3/13/2018 7:28 PM, Chris Wilson wrote:

Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.

v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
v4: Check the frequencies reported by the kernel across the entire
range.
v5: Rewrite sandwich to create a sandwich between multiple concurrent
engines.
v6: Exercise sysfs overrides.
v7: Reset min/max of default context after independent(); don't ask
about failure
v8: Check transition beyond randomly chosen frequencies as well as
up/down ramps.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Praveen Paneri <praveen.pan...@intel.com>
Cc: Sagar A Kamble <sagar.a.kam...@intel.com>
Cc: Antonio Argenziano <antonio.argenzi...@intel.com>
Reviewed-by: Antonio Argenziano <antonio.argenzi...@intel.com> #v5

There are few stray whitespaces in __pmu_within_tolerance, pmu_assert.
Otherwise looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Can you please clarify few things below:

---



+
+static void sysfs_clamp(int fd, const struct intel_execution_engine *e)
+{
+#define N_STEPS 10
+ const unsigned int engine = e->exec_id | e->flags;
+ uint32_t ctx = gem_context_create(fd);
+ uint32_t sys_min, sys_max;
+ uint32_t min, max;
+ double measured;
+ igt_spin_t *spin;
+ int pmu;
+
+ get_sysfs_freq(_min, _max);
+ igt_info("System min freq: %dMHz; max freq: %dMHz\n", sys_min, sys_max);
+
+ get_freq(fd, ctx, , );
+ igt_info("Context min freq: %dMHz; max freq: %dMHz\n", min, max);
+
+ pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ igt_require(pmu >= 0);
+
+ for (int outer = 0; outer <= 2*N_STEPS; outer++) {
+ int ofrac = outer > N_STEPS ? 2*N_STEPS - outer : outer;
+ uint32_t ofreq = min + (max - min) * ofrac / N_STEPS;
+ uint32_t cur, discard;
+
+ for (int inner = 0; inner <= 2*N_STEPS; inner++) {
+ int ifrac = inner > N_STEPS ? 2*N_STEPS - inner : inner;
+ uint32_t ifreq = min + (max - min) * ifrac / N_STEPS;
+
+ set_freq(fd, ctx, ifreq, ifreq);
+
+ gem_quiescent_gpu(fd);
+ spin = __igt_spin_batch_new(fd, ctx, engine, 0);
+ usleep(1);
+
+ set_sysfs_freq(ofreq, ofreq);
+ get_sysfs_freq(, );

We don't sleep here because we know that we set the frequency in sysfs?

sysfs is a synchronous interface, yes.


+
+ measured = measure_frequency(pmu, SAMPLE_PERIOD);
+ igt_debugfs_dump(fd, "i915_rps_boost_info");
+
+ set_sysfs_freq(sys_min, sys_max);
+
+ igt_spin_batch_free(fd, spin);
+ igt_info("%s(sysfs): Measured %.1fMHz, context %dMhz, expected 
%dMhz\n",
+ e->name, measured, ifreq, cur);
+ pmu_assert(measured, cur);
+ }
+ }
+ gem_quiescent_gpu(fd);
+
+ close(pmu);
+ gem_context_destroy(fd, ctx);
+
+#undef N_STEPS
+}
+

...

+static void disable_boost(int fd)
+{
+ char *value;
+
+ value = igt_sysfs_get(fd, "gt_RPn_freq_mhz");
+ igt_sysfs_set(fd, "gt_boost_freq_mhz", value);

Why is this needed? kernel will not clamp boost freq as well within
ctx_freq_min/max?

Boosting is a separate mechanism than ctx->freq, as it is performed on
behalf of *another* client.

Right. I meant i915 min|max_freq_context in your upcoming patch.
boost_freq is clamped against max_hw and min_user|soft|context
Understood that setting it to Rpn will make it get clamped in the 
expected range :)

Thanks for clarification.

Kernel disabling boost seems more effective than setting boost_freq to Rpn.

This is how we tell the kernel to disable boost, by setting it to a
value that never applies.

The tests try to avoid triggering boosts, but I felt it was sensible to
override the mechanism entirely. We still need various random sleeps
inside the tests in order to give the worker a chance to run, which is a
nuisance.
-Chris


--
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Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

[Sagar Arun Kamble]

On 3/2/2018 3:44 PM, Sagar Arun Kamble wrote:



On 3/2/2018 2:01 PM, Chris Wilson wrote:

Quoting Sagar Arun Kamble (2018-03-01 16:45:45)
+static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma 
*vma)

+{
+   struct intel_huc *huc = container_of(huc_fw, struct 
intel_huc, fw);

+   struct drm_i915_private *dev_priv = huc_to_i915(huc);
+   unsigned long offset = 0;
+   u32 size;
+   int ret;
+
+   GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
+
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   /* Set the source address for the uCode */
+   offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
+   I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+   I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0x);

So these same registers are used to transfer the guc image. What
serialisation do we have between the two to prevent conflicts?

(lockdep_assert_held the appropriate guard with explanation :)
Yes. Currently they are implicitly serialized by load ordering. Will 
need locking if async load is to be done.

But no harm in adding locking/lockdep now. Will do. Thank you.

Hi Chris,

Checked more on this and I see that *HuC has to be loaded before GuC 
always* hence we will not have situation of

dma_xfer for them happening in parallel. So we don't need the locking.

Thanks,
Sagar

As it's not a new issue, please follow up with another patch and we'll
apply this in the meantime.
-Chris




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Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

[Sagar Arun Kamble]

On 3/13/2018 7:28 PM, Chris Wilson wrote:

Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.

v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
v4: Check the frequencies reported by the kernel across the entire
range.
v5: Rewrite sandwich to create a sandwich between multiple concurrent
engines.
v6: Exercise sysfs overrides.
v7: Reset min/max of default context after independent(); don't ask
about failure
v8: Check transition beyond randomly chosen frequencies as well as
up/down ramps.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Praveen Paneri <praveen.pan...@intel.com>
Cc: Sagar A Kamble <sagar.a.kam...@intel.com>
Cc: Antonio Argenziano <antonio.argenzi...@intel.com>
Reviewed-by: Antonio Argenziano <antonio.argenzi...@intel.com> #v5

There are few stray whitespaces in __pmu_within_tolerance, pmu_assert.
Otherwise looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Can you please clarify few things below:

---



+
+static void sysfs_clamp(int fd, const struct intel_execution_engine *e)
+{
+#define N_STEPS 10
+   const unsigned int engine = e->exec_id | e->flags;
+   uint32_t ctx = gem_context_create(fd);
+   uint32_t sys_min, sys_max;
+   uint32_t min, max;
+   double measured;
+   igt_spin_t *spin;
+   int pmu;
+
+   get_sysfs_freq(_min, _max);
+   igt_info("System min freq: %dMHz; max freq: %dMHz\n", sys_min, sys_max);
+
+   get_freq(fd, ctx, , );
+   igt_info("Context min freq: %dMHz; max freq: %dMHz\n", min, max);
+
+   pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+   igt_require(pmu >= 0);
+
+   for (int outer = 0; outer <= 2*N_STEPS; outer++) {
+   int ofrac = outer > N_STEPS ? 2*N_STEPS - outer : outer;
+   uint32_t ofreq = min + (max - min) * ofrac / N_STEPS;
+   uint32_t cur, discard;
+
+   for (int inner = 0; inner <= 2*N_STEPS; inner++) {
+   int ifrac = inner > N_STEPS ? 2*N_STEPS - inner : inner;
+   uint32_t ifreq = min + (max - min) * ifrac / N_STEPS;
+
+   set_freq(fd, ctx, ifreq, ifreq);
+
+   gem_quiescent_gpu(fd);
+   spin = __igt_spin_batch_new(fd, ctx, engine, 0);
+   usleep(1);
+
+   set_sysfs_freq(ofreq, ofreq);
+   get_sysfs_freq(, );

We don't sleep here because we know that we set the frequency in sysfs?

+
+   measured = measure_frequency(pmu, SAMPLE_PERIOD);
+   igt_debugfs_dump(fd, "i915_rps_boost_info");
+
+   set_sysfs_freq(sys_min, sys_max);
+
+   igt_spin_batch_free(fd, spin);
+   igt_info("%s(sysfs): Measured %.1fMHz, context %dMhz, 
expected %dMhz\n",
+   e->name, measured, ifreq, cur);
+   pmu_assert(measured, cur);
+   }
+   }
+   gem_quiescent_gpu(fd);
+
+   close(pmu);
+   gem_context_destroy(fd, ctx);
+
+#undef N_STEPS
+}
+

...

+static void disable_boost(int fd)
+{
+   char *value;
+
+   value = igt_sysfs_get(fd, "gt_RPn_freq_mhz");
+   igt_sysfs_set(fd, "gt_boost_freq_mhz", value);
Why is this needed? kernel will not clamp boost freq as well within 
ctx_freq_min/max?

Kernel disabling boost seems more effective than setting boost_freq to Rpn.

+   free(value);
+}
+
+igt_main
+{
+   const struct intel_execution_engine *e;
+   int fd = -1;
+
+   igt_fixture {
+   fd = drm_open_driver(DRIVER_INTEL);
+   igt_require_gem(fd);
+
+   igt_require(has_ctx_freq(fd));
+
+   sysfs = igt_sysfs_open(fd, NULL);
+   igt_assert(sysfs != -1);
+   igt_install_exit_handler(restore_sysfs_freq);
+
+   disable_boost(sysfs);
+   }
+
+   igt_subtest("invalid")
+   invalid(fd);
+
+   igt_subtest("idempotent")
+   idempotent(fd);
+
+   igt_subtest("range")
+   range(fd);
+
+   igt_subtest("independent")
+   independent(fd);
+
+   igt_skip_on_simulation();
+
+   for (e = intel_execution_engines; e->name; e++) {
+   igt_subtest_group {
+   igt_fixture {
+   gem_require_ring(fd, e->exec_id | e->flags);
+   }
+
+   igt_subtest_f("%s-single", e->name)
+   single(fd, e);
+   igt_subtest_f(&qu

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

[Sagar Arun Kamble]

On 3/13/2018 7:24 PM, Michal Wajdeczko wrote:

Some functions already use i915 name instead of dev_priv.
Let's rename this param in all remaining functions, except
those that still use legacy macros.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Function comment description is not updated for sanitize_options_early 
and intel_uc_init_mmio.

With that:
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_uc.c | 122 
  1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0bc8f3b..c22155b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -50,10 +50,10 @@ static int __intel_uc_reset_hw(struct drm_i915_private 
*dev_priv)
return ret;
  }
  
-static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)

+static int __get_platform_enable_guc(struct drm_i915_private *i915)
  {
-   struct intel_uc_fw *guc_fw = _priv->guc.fw;
-   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+   struct intel_uc_fw *guc_fw = >guc.fw;
+   struct intel_uc_fw *huc_fw = >huc.fw;
int enable_guc = 0;
  
  	/* Default is to enable GuC/HuC if we know their firmwares */

@@ -67,12 +67,12 @@ static int __get_platform_enable_guc(struct 
drm_i915_private *dev_priv)
return enable_guc;
  }
  
-static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)

+static int __get_default_guc_log_level(struct drm_i915_private *i915)
  {
int guc_log_level = 0; /* disabled */
  
  	/* Enable if we're running on platform with GuC and debug config */

-   if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&
+   if (HAS_GUC(i915) && intel_uc_is_using_guc() &&
(IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
 IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)))
guc_log_level = 1 + GUC_LOG_VERBOSITY_MAX;
@@ -99,14 +99,14 @@ static int __get_default_guc_log_level(struct 
drm_i915_private *dev_priv)
   * unless GuC is enabled on given platform and the driver is compiled with
   * debug config when this modparam will default to "enable(1..4)".
   */
-static void sanitize_options_early(struct drm_i915_private *dev_priv)
+static void sanitize_options_early(struct drm_i915_private *i915)
  {
-   struct intel_uc_fw *guc_fw = _priv->guc.fw;
-   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+   struct intel_uc_fw *guc_fw = >guc.fw;
+   struct intel_uc_fw *huc_fw = >huc.fw;
  
  	/* A negative value means "use platform default" */

if (i915_modparams.enable_guc < 0)
-   i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
+   i915_modparams.enable_guc = __get_platform_enable_guc(i915);
  
  	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",

 i915_modparams.enable_guc,
@@ -117,28 +117,28 @@ static void sanitize_options_early(struct 
drm_i915_private *dev_priv)
if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "enable_guc", i915_modparams.enable_guc,
-!HAS_GUC(dev_priv) ? "no GuC hardware" :
- "no GuC firmware");
+!HAS_GUC(i915) ? "no GuC hardware" :
+ "no GuC firmware");
}
  
  	/* Verify HuC firmware availability */

if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "enable_guc", i915_modparams.enable_guc,
-!HAS_HUC(dev_priv) ? "no HuC hardware" :
- "no HuC firmware");
+!HAS_HUC(i915) ? "no HuC hardware" :
+ "no HuC firmware");
}
  
  	/* A negative value means "use platform/config default" */

if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
-   __get_default_guc_log_level(dev_priv);
+   __get_default_guc_log_level(i915);
  
  	if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {

DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "guc_log_level", i915_modparams.guc_log_level,
-!HAS_GUC(dev_priv) ? "no GuC hardware" :
- "GuC not enabled"

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/uc: Use helper functions to detect fw load status

[Sagar Arun Kamble]

On 3/13/2018 7:24 PM, Michal Wajdeczko wrote:

We don't have to check load status values.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_huc.c | 2 +-
  drivers/gpu/drm/i915/intel_uc.c  | 4 ++--
  2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 65e2afb..5c3423a 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -51,7 +51,7 @@ int intel_huc_auth(struct intel_huc *huc)
u32 status;
int ret;
  
-	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)

+   if (!intel_uc_fw_is_loaded(>fw))
return -ENOEXEC;
  
  	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index f89acf4..0bc8f3b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -490,7 +490,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
  
-	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)

+   if (!intel_guc_is_loaded(guc))
return 0;
  
  	err = intel_guc_suspend(guc);

@@ -512,7 +512,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
  
-	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)

+   if (!intel_guc_is_loaded(guc))
return 0;
  
  	if (i915_modparams.guc_log_level)


--
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Sagar

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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915/uc: Use correct error code for GuC initialization failure

[Sagar Arun Kamble]

On 3/13/2018 7:24 PM, Michal Wajdeczko wrote:

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-EIO).

Unfortunately since commit 121981fafe69 ("drm/i915/guc: Combine
enable_guc_loading|submission modparams") we stopped using that
error code to avoid unwanted fallback to execlist submission mode.

In result any GuC initialization failure was treated as non-recoverable
error leading to driver load abort, so we could not even read related
GuC error log to investigate cause of the problem.

Fix that by always returning -EIO on uC hardware related failure.

v2: don't allow -EIO from uc_init
 don't call uc_fini[_misc] on -EIO
 mark guc fw as failed on hw init failure
 prepare uc_fini_hw to run after earlier -EIO

v3: update comments (Sagar)
 use sanitize functions on failure in init_hw (Michal)
 and also sanitize guc/huc fw in fini_hw (Michal)

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiar...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
  drivers/gpu/drm/i915/i915_gem.c| 17 ++---
  drivers/gpu/drm/i915/intel_guc.h   |  5 +
  drivers/gpu/drm/i915/intel_uc.c| 18 ++
  drivers/gpu/drm/i915/intel_uc_fw.h |  5 +
  4 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 05b0724..8eed87d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5338,8 +5338,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_init_gt_powersave(dev_priv);
  
  	ret = intel_uc_init(dev_priv);

-   if (ret)
+   if (ret) {
+   GEM_BUG_ON(ret == -EIO);
goto err_pm;
+   }
  
  	ret = i915_gem_init_hw(dev_priv);

if (ret)
@@ -5386,7 +5388,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
intel_uc_fini_hw(dev_priv);
  err_uc_init:
-   intel_uc_fini(dev_priv);
+   if (ret != -EIO)
+   intel_uc_fini(dev_priv);
  err_pm:
if (ret != -EIO) {
intel_cleanup_gt_powersave(dev_priv);
@@ -5400,15 +5403,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
  
-	intel_uc_fini_misc(dev_priv);

-
-   if (ret != -EIO)
+   if (ret != -EIO) {
+   intel_uc_fini_misc(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
+   }
  
  	if (ret == -EIO) {

/*
-* Allow engine initialisation to fail by marking the GPU as
-* wedged. But we only want to do this where the GPU is angry,
+* Allow engines or uC initialization to fail by marking the GPU
+* as wedged. But we only want to do this when the GPU is angry,
 * for all other failure, such as an allocation failure, bail.
 */
if (!i915_terminally_wedged(_priv->gpu_error)) {
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d878160..faa9e01 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -139,4 +139,9 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
  }
  
+static inline bool intel_guc_is_loaded(struct intel_guc *guc)

+{
+   return intel_uc_fw_is_loaded(>fw);
+}
+
  #endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9d5ffd7..f89acf4 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -447,15 +447,20 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 * Note that there is no fallback as either user explicitly asked for
 * the GuC or driver default option was to run with the GuC enabled.
 */
-   if (GEM_WARN_ON(ret == -EIO))
-   ret = -EINVAL;
-
dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret);
-   return ret;
+
+   /* Sanitize GuC/HuC to avoid clean-up on wedged */
+   intel_huc_sanitize(huc);
+   intel_guc_sanitize(guc);
+   GEM_BUG_ON(intel_guc_is_loaded(guc));
+

How about also resetting the hw using __intel_uc_reset_hw().

+   /* We want to disable GPU submission but keep KMS alive */
+   return -EIO;
  }
  
  void intel_uc_fini_hw(struct drm_i915_private *dev_priv)

  {
+   struct intel_huc *huc = _priv->huc;
struct intel_guc *guc = _priv->guc;
  
  	if (!USES_GUC(d

Re: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

[Sagar Arun Kamble]

On 3/10/2018 3:05 AM, Chris Wilson wrote:

Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.

v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
v4: Check the frequencies reported by the kernel across the entire
range.
v5: Rewrite sandwich to create a sandwich between multiple concurrent
engines.

Signed-off-by: Chris Wilson 
Cc: Praveen Paneri 
Cc: Sagar A Kamble 
Cc: Antonio Argenziano 



+static void single(int fd, const struct intel_execution_engine *e)
+{
+#define N_STEPS 10
+   const unsigned int engine = e->exec_id | e->flags;
+   uint32_t ctx = gem_context_create(fd);
+   uint32_t min, max;
+   double measured;
+   igt_spin_t *spin;
+   int pmu;
+
+   get_freq(fd, ctx, , );
+   igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max);
+
+   pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+   igt_require(pmu >= 0);

This igt_require can go to igt_fixture below.

+
+   for (int step = 0; step <= 2*N_STEPS; step++) {
+   int frac = step > N_STEPS ? 2*N_STEPS - step : step;
+   uint32_t freq = min + (max - min) * frac / N_STEPS;
+   uint32_t cur, discard;
+
+   set_freq(fd, ctx, freq, freq);
+   get_freq(fd, ctx, , );
+
+   gem_quiescent_gpu(fd);
+   spin = __igt_spin_batch_new(fd, ctx, engine, 0);
+   usleep(1);
+
+   measured = measure_frequency(pmu, SAMPLE_PERIOD);
+   igt_debugfs_dump(fd, "i915_rps_boost_info");
+
+   igt_spin_batch_free(fd, spin);
+   igt_info("%s(single): Measured %.1fMHz, expected %dMhz\n",
+e->name, measured, cur);
+   igt_assert(measured > cur - 100 && measured < cur + 100);

Is this margin of 100Mhz for PMU accuracy?

+   }
+   gem_quiescent_gpu(fd);
+
+   close(pmu);
+   gem_context_destroy(fd, ctx);
+
+#undef N_STEPS
+}
+
+static void continuous(int fd, const struct intel_execution_engine *e)
+{
+#define N_STEPS 10
+   const unsigned int engine = e->exec_id | e->flags;
+   uint32_t ctx = gem_context_create(fd);
+   uint32_t min, max;
+   double measured;
+   igt_spin_t *spin;
+   int pmu;
+
+   get_freq(fd, ctx, , );
+   igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max);
+
+   pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+   igt_require(pmu >= 0);
+
+   gem_quiescent_gpu(fd);
+   spin = __igt_spin_batch_new(fd, ctx, engine, 0);
+   for (int step = 0; step <= 2*N_STEPS; step++) {
+   int frac = step > N_STEPS ? 2*N_STEPS - step : step;
+   uint32_t freq = min + (max - min) * frac / N_STEPS;
+   uint32_t cur, discard;
+   igt_spin_t *kick;
+
+   set_freq(fd, ctx, freq, freq);
+   get_freq(fd, ctx, , );
+
+   /*
+* When requesting a new frequency on the currently
+* executing context, it does not take effect until the
+* next context switch. In this case, we trigger a lite
+* restore.
+*/
+   kick = __igt_spin_batch_new(fd, ctx, engine, 0);
+   igt_spin_batch_free(fd, spin);
+   spin = kick;
+
+   usleep(1);
+
+   measured = measure_frequency(pmu, SAMPLE_PERIOD);
+   igt_debugfs_dump(fd, "i915_rps_boost_info");
+
+   igt_info("%s(continuous): Measured %.1fMHz, expected %dMhz\n",
+e->name, measured, cur);
+   igt_assert(measured > cur - 100 && measured < cur + 100);
+   }
+   igt_spin_batch_free(fd, spin);
+   gem_quiescent_gpu(fd);
+
+   close(pmu);
+   gem_context_destroy(fd, ctx);
+#undef N_STEPS
+}
+
+static void inflight(int fd, const struct intel_execution_engine *e)
+{
+   const unsigned int engine = e->exec_id | e->flags;
+   uint32_t ctx, min, max, freq, discard;
+   double measured;
+   igt_spin_t *plug, *work[2];
+   int pmu;
+
+   pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+   igt_require(pmu >= 0);
+
+   ctx = gem_context_create(fd);
+   get_freq(fd, ctx, , );
+   set_freq(fd, ctx, min, min);
+
+   igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max);
+
+   gem_quiescent_gpu(fd);
+   plug = igt_spin_batch_new(fd, ctx, engine, 0);
+   gem_context_destroy(fd, ctx);
+   for (int n = 0; n < 16; n++) {
+   struct drm_i915_gem_exec_object2 obj = {
+   .handle = plug->handle,
+   };
+   struct drm_i915_gem_execbuffer2 eb = {
+   

Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Sanitize uC together with GEM

[Sagar Arun Kamble]

On 3/9/2018 2:30 AM, Michal Wajdeczko wrote:

Instead of dancing around uC on reset/suspend/resume scenarios,
explicitly sanitize uC when we sanitize GEM to force uC reload
and start from known beginning.

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thie...@intel.com>
---
  drivers/gpu/drm/i915/i915_gem.c|  2 ++
  drivers/gpu/drm/i915/intel_guc.h   |  6 ++
  drivers/gpu/drm/i915/intel_huc.h   |  6 ++
  drivers/gpu/drm/i915/intel_uc.c| 18 ++
  drivers/gpu/drm/i915/intel_uc.h|  1 +
  drivers/gpu/drm/i915/intel_uc_fw.h |  6 ++
  6 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ab88ca5..49c81ae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4892,6 +4892,8 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 */
if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
above intel_gpu_reset also resets uC. Should we just let it reset only 
real engines with this change then?

+
+   intel_uc_sanitize(i915);
  }
  
  int i915_gem_suspend(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b9424ac..ec8569f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -132,4 +132,10 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
  u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
  
+static inline int intel_guc_sanitize(struct intel_guc *guc)

+{
+   intel_uc_fw_sanitize(>fw);
+   return 0;
+}
+
  #endif
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 5d6e804..b185850 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -38,4 +38,10 @@ struct intel_huc {
  void intel_huc_init_early(struct intel_huc *huc);
  int intel_huc_auth(struct intel_huc *huc);
  
+static inline int intel_huc_sanitize(struct intel_huc *huc)

+{
+   intel_uc_fw_sanitize(>fw);
+   return 0;
+}
+
  #endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index a45171c..abd1f7b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -327,6 +327,24 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
intel_guc_fini(guc);
  }
  
+void intel_uc_sanitize(struct drm_i915_private *i915)

+{
+   struct intel_guc *guc = >guc;
+   struct intel_huc *huc = >huc;
+
+   if (!USES_GUC(i915))
+   return;
+
+   GEM_BUG_ON(!HAS_GUC(i915));
+
+   guc_disable_communication(guc);
+
+   intel_huc_sanitize(huc);
+   intel_guc_sanitize(guc);
+
+   __intel_uc_reset_hw(i915);
+}
+
  int intel_uc_init_hw(struct drm_i915_private *dev_priv)
  {
struct intel_guc *guc = _priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index dce4813..937e611 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -34,6 +34,7 @@
  void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
  int intel_uc_init_misc(struct drm_i915_private *dev_priv);
  void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
  int intel_uc_init_hw(struct drm_i915_private *dev_priv);
  void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
  int intel_uc_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h 
b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..2601521 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,12 @@ static inline bool intel_uc_fw_is_selected(struct 
intel_uc_fw *uc_fw)
return uc_fw->path != NULL;
  }
  
+static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)

+{
+   if (uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)
+   uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
+}
+
  void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
   struct intel_uc_fw *uc_fw);
  int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Default to non-verbose GuC logging

[Sagar Arun Kamble]

On 3/8/2018 9:17 PM, Michał Winiarski wrote:

Now that we've decoupled logging from relay, GuC log level is only
controlling the GuC behavior - there shouldn't be any impact on i915
behaviour. We're only going to see a single extra interrupt when log
will get half full.
That, and the fact that we're seeing igt/gem_exec_nop/basic-series
failing with non-verbose logging being disabled.

v2: Bring back the "auto" guc_log_level, now that we fixed the log

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> (v1)

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_params.h | 2 +-
  drivers/gpu/drm/i915/intel_uc.c| 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..c96360398072 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@ struct drm_printer;
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
param(int, enable_guc, 0) \
-   param(int, guc_log_level, 0) \
+   param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 3fb5f75aa7c9..2f579fff58cd 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -69,7 +69,7 @@ static int __get_platform_enable_guc(struct drm_i915_private 
*dev_priv)
  
  static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)

  {
-   int guc_log_level = 0; /* disabled */
+   int guc_log_level = 1; /* non-verbose */
  
  	/* Enable if we're running on platform with GuC and debug config */

if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&


--
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Sagar

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Re: [Intel-gfx] [PATCH v2 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

[Sagar Arun Kamble]

On 3/8/2018 9:17 PM, Michał Winiarski wrote:

If nobody has enabled the relay, we're not comunicating with GuC, which
means that the stats don't have any meaning. Let's also remove interrupt
counter and tidy the debugfs formatting.

v2: Correct stats accounting (Sagar)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 45 
  drivers/gpu/drm/i915/intel_guc.c |  5 +---
  drivers/gpu/drm/i915/intel_guc_log.c | 22 +-
  drivers/gpu/drm/i915/intel_guc_log.h | 10 
  4 files changed, 48 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d29bacb1f308..94516ab4eaed 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2326,30 +2326,45 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
return 0;
  }
  
+static const char *

+stringify_guc_log_type(enum guc_log_buffer_type type)
+{
+   switch (type) {
+   case GUC_ISR_LOG_BUFFER:
+   return "ISR";
+   case GUC_DPC_LOG_BUFFER:
+   return "DPC";
+   case GUC_CRASH_DUMP_LOG_BUFFER:
+   return "CRASH";
+   default:
+   MISSING_CASE(type);
+   }
+
+   return "";
+}
+
  static void i915_guc_log_info(struct seq_file *m,
  struct drm_i915_private *dev_priv)
  {
struct intel_guc *guc = _priv->guc;
+   enum guc_log_buffer_type type;
  
-	seq_puts(m, "GuC logging stats:\n");

-
-   seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_ISR_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
-
-   seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_DPC_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
-
-   seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
+   if (!intel_guc_log_relay_enabled(guc)) {
+   seq_puts(m, "GuC log relay disabled\n");
+   return;
+   }
  
-	seq_printf(m, "\tTotal flush interrupt count: %u\n",

-  guc->log.flush_interrupt_count);
+   seq_puts(m, "GuC logging stats:\n");
  
  	seq_printf(m, "\tRelay full count: %u\n",

   guc->log.relay.full_count);
+
+   for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
+  stringify_guc_log_type(type),
+  guc->log.stats[type].flush,
+  guc->log.stats[type].overflow);

Didn't see this earlier. Should be sampled_overflow.
And ordering of intel_guc_log_relay_enabled() declaration w.r.t other 
declarations needs to be fixed.

With that:
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

+   }
  }
  
  static void i915_guc_client_info(struct seq_file *m,

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index cab158e42577..3e2f0f8503ed 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -388,12 +388,9 @@ void intel_guc_to_host_event_handler(struct intel_guc *guc)
spin_unlock(>irq_lock);
  
  	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

-  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
+  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
queue_work(guc->log.relay.flush_wq,
   >log.relay.flush_work);
-
-   guc->log.flush_interrupt_count++;
-   }
  }
  
  int intel_guc_sample_forcewake(struct intel_guc *guc)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 7c4339dae534..a72fe4a369f4 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -171,22 +171,22 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
return relay_reserve(guc->log.relay.channel, 0);
  }
  
-static bool guc_check_log_buf_overflow(struct intel_guc *guc,

+static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
   enum guc_log_buffer_type type,
   

Re: [Intel-gfx] [PATCH v2 10/15] drm/i915/guc: Get rid of GuC log runtime

[Sagar Arun Kamble]

On 3/8/2018 9:17 PM, Michał Winiarski wrote:

Runtime is not a very good name. Let's also move counting relay
overflows inside relay struct.

v2: Rename things rather than remove the struct (Chris)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Some might want other stats too as part of relay since we print them 
when relay is enabled.

But this is not a big issue. w/ or w/o that change:
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
  drivers/gpu/drm/i915/intel_guc.c | 12 +++
  drivers/gpu/drm/i915/intel_guc_log.c | 66 ++--
  drivers/gpu/drm/i915/intel_guc_log.h |  7 ++--
  4 files changed, 44 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index f99fe9910634..d7c0bf6facf6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2348,8 +2348,8 @@ static void i915_guc_log_info(struct seq_file *m,
seq_printf(m, "\tTotal flush interrupt count: %u\n",
   guc->log.flush_interrupt_count);
  
-	seq_printf(m, "\tCapture miss count: %u\n",

-  guc->log.capture_miss_count);
+   seq_printf(m, "\tRelay full count: %u\n",
+  guc->log.relay.full_count);
  }
  
  static void i915_guc_client_info(struct seq_file *m,

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 0d92caf6a83f..cab158e42577 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -87,9 +87,9 @@ int intel_guc_init_wq(struct intel_guc *guc)
 * or scheduled later on resume. This way the handling of work
 * item can be kept same between system suspend & rpm suspend.
 */
-   guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
+   guc->log.relay.flush_wq = alloc_ordered_workqueue("i915-guc_log",
WQ_HIGHPRI | WQ_FREEZABLE);
-   if (!guc->log.runtime.flush_wq) {
+   if (!guc->log.relay.flush_wq) {
DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
return -ENOMEM;
}
@@ -112,7 +112,7 @@ int intel_guc_init_wq(struct intel_guc *guc)
guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
  WQ_HIGHPRI);
if (!guc->preempt_wq) {
-   destroy_workqueue(guc->log.runtime.flush_wq);
+   destroy_workqueue(guc->log.relay.flush_wq);
DRM_ERROR("Couldn't allocate workqueue for GuC "
  "preemption\n");
return -ENOMEM;
@@ -130,7 +130,7 @@ void intel_guc_fini_wq(struct intel_guc *guc)
USES_GUC_SUBMISSION(dev_priv))
destroy_workqueue(guc->preempt_wq);
  
-	destroy_workqueue(guc->log.runtime.flush_wq);

+   destroy_workqueue(guc->log.relay.flush_wq);
  }
  
  static int guc_shared_data_create(struct intel_guc *guc)

@@ -389,8 +389,8 @@ void intel_guc_to_host_event_handler(struct intel_guc *guc)
  
  	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
-   queue_work(guc->log.runtime.flush_wq,
-  >log.runtime.flush_work);
+   queue_work(guc->log.relay.flush_wq,
+  >log.relay.flush_work);
  
  		guc->log.flush_interrupt_count++;

}
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 92a7bf0fd729..7c4339dae534 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -151,10 +151,10 @@ static void guc_move_to_next_buf(struct intel_guc *guc)
smp_wmb();
  
  	/* All data has been written, so now move the offset of sub buffer. */

-   relay_reserve(guc->log.runtime.relay_chan, 
guc->log.vma->obj->base.size);
+   relay_reserve(guc->log.relay.channel, guc->log.vma->obj->base.size);
  
  	/* Switch to the next sub buffer */

-   relay_flush(guc->log.runtime.relay_chan);
+   relay_flush(guc->log.relay.channel);
  }
  
  static void *guc_get_write_buffer(struct intel_guc *guc)

@@ -168,7 +168,7 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
 * done without using relay_reserve() along with relay_write(). So its
 * better to use relay_reserve() alone.
 */
-  

Re: [Intel-gfx] [PATCH v2 08/15] drm/i915/guc: Split relay control and GuC log level

[Sagar Arun Kamble]

On 3/8/2018 9:17 PM, Michał Winiarski wrote:

Those two concepts are really separate. Since GuC is writing data into
its own buffer and we even provide a way for userspace to read directly
from it using i915_guc_log_dump debugfs, there's no real reason to tie
log level with relay creation.
Let's create a separate debugfs, giving userspace a way to create a
relay on demand, when it wants to read a continuous log rather than a
snapshot.

v2: Don't touch guc_log_level on relay creation error, adjust locking
 after rebase, s/dev_priv/i915, pass guc to file->private_data (Sagar)
 Use struct_mutex rather than runtime.lock for set_log_level

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>



diff --git a/drivers/gpu/drm/i915/intel_guc_log.h 
b/drivers/gpu/drm/i915/intel_guc_log.h
index 8c26cce77a98..df91f12a36ed 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -61,9 +61,10 @@ struct intel_guc_log {
  int intel_guc_log_create(struct intel_guc *guc);
  void intel_guc_log_destroy(struct intel_guc *guc);
  void intel_guc_log_init_early(struct intel_guc *guc);
-int intel_guc_log_control_get(struct intel_guc *guc);
-int intel_guc_log_control_set(struct intel_guc *guc, u64 control_val);
-int intel_guc_log_register(struct intel_guc *guc);
-void intel_guc_log_unregister(struct intel_guc *guc);
+int intel_guc_log_level_get(struct intel_guc *guc);
+int intel_guc_log_level_set(struct intel_guc *guc, u64 control_val);
+int intel_guc_log_relay_open(struct intel_guc *guc);
+void intel_guc_log_relay_close(struct intel_guc *guc);
+void intel_guc_log_relay_flush(struct intel_guc *guc);

Need to maintain order of definition. init_early is also not in order.
With that:
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
  
  #endif

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 90d2f38e22c9..abce0e38528a 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -219,28 +219,6 @@ static void guc_free_load_err_log(struct intel_guc *guc)
i915_gem_object_put(guc->load_err_log);
  }
  
-int intel_uc_register(struct drm_i915_private *i915)

-{
-   int ret = 0;
-
-   if (!USES_GUC(i915))
-   return 0;
-
-   if (i915_modparams.guc_log_level)
-   ret = intel_guc_log_register(>guc);
-
-   return ret;
-}
-
-void intel_uc_unregister(struct drm_i915_private *i915)
-{
-   if (!USES_GUC(i915))
-   return;
-
-   if (i915_modparams.guc_log_level)
-   intel_guc_log_unregister(>guc);
-}
-
  static int guc_enable_communication(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index d6af984cd789..f76d51d1ce70 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -31,8 +31,6 @@
  void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
  void intel_uc_init_early(struct drm_i915_private *dev_priv);
  void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
-int intel_uc_register(struct drm_i915_private *dev_priv);
-void intel_uc_unregister(struct drm_i915_private *dev_priv);
  void intel_uc_init_fw(struct drm_i915_private *dev_priv);
  void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
  int intel_uc_init_misc(struct drm_i915_private *dev_priv);


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v2 07/15] drm/i915/guc: Flush directly in log unregister

[Sagar Arun Kamble]

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

Having both guc_flush_logs and guc_log_flush functions is confusing.
While we could just rename things, guc_flush_logs implementation is
quite simple. Let's get rid of it and move its content to unregister.

v2: s/dev_priv/i915 (Sagar)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_guc_log.c | 34 ++
  1 file changed, 14 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index ee0981f5a208..5ff4b510569a 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -443,25 +443,6 @@ static void guc_log_capture_logs(struct intel_guc *guc)
intel_runtime_pm_put(dev_priv);
  }
  
-static void guc_flush_logs(struct intel_guc *guc)

-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
-   /*
-* Before initiating the forceful flush, wait for any pending/ongoing
-* flush to complete otherwise forceful flush may not actually happen.
-*/
-   flush_work(>log.runtime.flush_work);
-
-   /* Ask GuC to update the log buffer state */
-   intel_runtime_pm_get(dev_priv);
-   guc_log_flush(guc);
-   intel_runtime_pm_put(dev_priv);
-
-   /* GuC would have updated log buffer by now, so capture it */
-   guc_log_capture_logs(guc);
-}
-
  int intel_guc_log_create(struct intel_guc *guc)
  {
struct i915_vma *vma;
@@ -630,15 +611,28 @@ int intel_guc_log_register(struct intel_guc *guc)
  
  void intel_guc_log_unregister(struct intel_guc *guc)

  {
+   struct drm_i915_private *i915 = guc_to_i915(guc);
+
guc_log_flush_irq_disable(guc);
  
+	/*

+* Before initiating the forceful flush, wait for any pending/ongoing
+* flush to complete otherwise forceful flush may not actually happen.
+*/
+   flush_work(>log.runtime.flush_work);
+
/*
 * Once logging is disabled, GuC won't generate logs & send an
 * interrupt. But there could be some data in the log buffer
 * which is yet to be captured. So request GuC to update the log
 * buffer state and then collect the left over logs.
 */
-   guc_flush_logs(guc);
+   intel_runtime_pm_get(i915);
+   guc_log_flush(guc);
+   intel_runtime_pm_put(i915);
+
+   /* GuC would have updated log buffer by now, so capture it */
+   guc_log_capture_logs(guc);
  
  	mutex_lock(>log.runtime.lock);
  


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v2 06/15] drm/i915/guc: Merge log relay file and channel creation

[Sagar Arun Kamble]

Hi Michal,

One comment was missed and another comment update suggested.

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

We have all the information we need at relay_open call time.
Since there's no reason to split the process into relay_open and
relay_late_setup_files, let's remove the extra code.

v2: Remove obsoleted comments (Sagar)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
  drivers/gpu/drm/i915/intel_guc_log.c | 64 +++-
  1 file changed, 5 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 4eb3ebd8d6c3..ee0981f5a208 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -121,14 +121,7 @@ static struct dentry *create_buf_file_callback(const char 
*filename,
if (!parent)
return NULL;
  
-	/*

-* Not using the channel filename passed as an argument, since for each
-* channel relay appends the corresponding CPU number to the filename
-* passed in relay_open(). This should be fine as relay just needs a
-* dentry of the file associated with the channel buffer and that file's
-* name need not be same as the filename passed as an argument.
-*/
-   buf_file = debugfs_create_file("guc_log", mode,
+   buf_file = debugfs_create_file(filename, mode,
   parent, buf, _file_operations);
return buf_file;
  }
@@ -149,43 +142,6 @@ static struct rchan_callbacks relay_callbacks = {
.remove_buf_file = remove_buf_file_callback,
  };
  
-static int guc_log_relay_file_create(struct intel_guc *guc)

-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   struct dentry *log_dir;
-   int ret;
-
-   lockdep_assert_held(>log.runtime.lock);
-
-   /* For now create the log file in /sys/kernel/debug/dri/0 dir */
-   log_dir = dev_priv->drm.primary->debugfs_root;
-
-   /*
-* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
-* not mounted and so can't create the relay file.
-* The relay API seems to fit well with debugfs only, for availing relay
-* there are 3 requirements which can be met for debugfs file only in a
-* straightforward/clean manner :-
-* i)   Need the associated dentry pointer of the file, while opening 
the
-*  relay channel.
-* ii)  Should be able to use 'relay_file_operations' fops for the file.
-* iii) Set the 'i_private' field of file's inode to the pointer of
-*  relay channel buffer.
-*/
-   if (!log_dir) {
-   DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
-   return -ENODEV;
-   }
-
-   ret = relay_late_setup_files(guc->log.runtime.relay_chan, "guc_log", 
log_dir);
-   if (ret < 0 && ret != -EEXIST) {
-   DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
-   return ret;
-   }
-
-   return 0;
-}
-
  static void guc_move_to_next_buf(struct intel_guc *guc)
  {
/*
@@ -271,7 +227,6 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
/* Get the pointer to shared GuC log buffer */
log_buf_state = src_data = guc->log.runtime.buf_addr;
  
-

/* Get the pointer to local buffer to store the logs */
log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
  
@@ -443,8 +398,10 @@ static int guc_log_relay_create(struct intel_guc *guc)

 * the GuC firmware logs, the channel will be linked with a file
 * later on when debugfs is registered.
 */

Above comment needs to be removed/updated.

-   guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
-   n_subbufs, _callbacks, dev_priv);
+   guc_log_relay_chan = relay_open("guc_log",
+   dev_priv->drm.primary->debugfs_root,
+   subbuf_size, n_subbufs,
+   _callbacks, dev_priv);
if (!guc_log_relay_chan) {
DRM_ERROR("Couldn't create relay chan for GuC logging\n");
  
@@ -649,11 +606,6 @@ int intel_guc_log_register(struct intel_guc *guc)
  
  	GEM_BUG_ON(guc_log_has_runtime(guc));
  
-	/*

-* If log was disabled at boot time, then setup needed to handle
-* log buffer flush interrupts would not have been done yet, so
-* do that now.
-*/

May be this comment shou

Re: [Intel-gfx] [PATCH v2 05/15] drm/i915/guc: Log runtime should consist of both mapping and relay

[Sagar Arun Kamble]

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

Currently, we're treating relay and mapping of GuC log as a separate
concepts. We're also using inconsistent locking, sometimes using
relay_lock, sometimes using struct mutex.
Let's correct that. Anything touching the runtime is now serialized
using runtime.lock, while we're still using struct mutex as inner lock
for mapping.
We're still racy in setting the log level - but we'll take care of that
in the following patches.

v2: Tidy locking (Sagar)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_guc_log.c | 113 +++
  drivers/gpu/drm/i915/intel_guc_log.h |   3 +-
  2 files changed, 36 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 89cb3939467f..4eb3ebd8d6c3 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -155,10 +155,7 @@ static int guc_log_relay_file_create(struct intel_guc *guc)
struct dentry *log_dir;
int ret;
  
-	if (!i915_modparams.guc_log_level)

-   return 0;
-
-   mutex_lock(>log.runtime.relay_lock);
+   lockdep_assert_held(>log.runtime.lock);
  
  	/* For now create the log file in /sys/kernel/debug/dri/0 dir */

log_dir = dev_priv->drm.primary->debugfs_root;
@@ -177,28 +174,16 @@ static int guc_log_relay_file_create(struct intel_guc 
*guc)
 */
if (!log_dir) {
DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
-   ret = -ENODEV;
-   goto out_unlock;
+   return -ENODEV;
}
  
  	ret = relay_late_setup_files(guc->log.runtime.relay_chan, "guc_log", log_dir);

if (ret < 0 && ret != -EEXIST) {
DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
-   goto out_unlock;
+   return ret;
}
  
-	ret = 0;

-
-out_unlock:
-   mutex_unlock(>log.runtime.relay_lock);
-   return ret;
-}
-
-static bool guc_log_has_relay(struct intel_guc *guc)
-{
-   lockdep_assert_held(>log.runtime.relay_lock);
-
-   return guc->log.runtime.relay_chan != NULL;
+   return 0;
  }
  
  static void guc_move_to_next_buf(struct intel_guc *guc)

@@ -209,9 +194,6 @@ static void guc_move_to_next_buf(struct intel_guc *guc)
 */
smp_wmb();
  
-	if (!guc_log_has_relay(guc))

-   return;
-
/* All data has been written, so now move the offset of sub buffer. */
relay_reserve(guc->log.runtime.relay_chan, 
guc->log.vma->obj->base.size);
  
@@ -221,9 +203,6 @@ static void guc_move_to_next_buf(struct intel_guc *guc)
  
  static void *guc_get_write_buffer(struct intel_guc *guc)

  {
-   if (!guc_log_has_relay(guc))
-   return NULL;
-
/*
 * Just get the base address of a new sub buffer and copy data into it
 * ourselves. NULL will be returned in no-overwrite mode, if all sub
@@ -284,13 +263,14 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
void *src_data, *dst_data;
bool new_overflow;
  
+	mutex_lock(>log.runtime.lock);

+
if (WARN_ON(!guc->log.runtime.buf_addr))
-   return;
+   goto out_unlock;
  
  	/* Get the pointer to shared GuC log buffer */

log_buf_state = src_data = guc->log.runtime.buf_addr;
  
-	mutex_lock(>log.runtime.relay_lock);
  
  	/* Get the pointer to local buffer to store the logs */

log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
@@ -302,9 +282,8 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
 */
DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
-   mutex_unlock(>log.runtime.relay_lock);
  
-		return;

+   goto out_unlock;
}
  
  	/* Actual logs are present from the 2nd page */

@@ -375,7 +354,8 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
  
  	guc_move_to_next_buf(guc);
  
-	mutex_unlock(>log.runtime.relay_lock);

+out_unlock:
+   mutex_unlock(>log.runtime.lock);
  }
  
  static void capture_logs_work(struct work_struct *work)

@@ -391,20 +371,20 @@ static bool guc_log_has_runtime(struct intel_guc *guc)
return guc->log.runtime.buf_addr != NULL;
  }
  
-static int guc_log_runtime_create(struct intel_guc *guc)

+static int guc_log_map(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc

Re: [Intel-gfx] [PATCH v2 03/15] drm/i915/guc: Move GuC notification handling to separate function

[Sagar Arun Kamble]

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

From: Michal Wajdeczko <michal.wajdec...@intel.com>

To allow future code reuse. While here, fix comment style.

v2: Notifications are a separate thing - rename the handler (Sagar)

Suggested-by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
I am suggesting update to the comments below since it is not clear the 
reason for clearing. Please check and incorporate in this patch

itself if you feel it is right. Otherwise change looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_irq.c  | 33 ++---
  drivers/gpu/drm/i915/intel_guc.c | 37 +
  drivers/gpu/drm/i915/intel_guc.h |  1 +
  3 files changed, 40 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 633c18785c1e..6b0cd6bc83f8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1766,37 +1766,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private 
*dev_priv, u32 pm_iir)
  
  static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)

  {
-   if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
-   /* Sample the log buffer flush related bits & clear them out now
-* itself from the message identity register to minimize the
-* probability of losing a flush interrupt, when there are back
-* to back flush interrupts.
-* There can be a new flush interrupt, for different log buffer
-* type (like for ISR), whilst Host is handling one (for DPC).
-* Since same bit is used in message register for ISR & DPC, it
-* could happen that GuC sets the bit for 2nd interrupt but Host
-* clears out the bit on handling the 1st interrupt.
-*/
-   u32 msg, flush;
-
-   msg = I915_READ(SOFT_SCRATCH(15));
-   flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
-  INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
-   if (flush) {
-   /* Clear the message bits that are handled */
-   I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
-   /* Handle flush interrupt in bottom half */
-   queue_work(dev_priv->guc.log.runtime.flush_wq,
-  _priv->guc.log.runtime.flush_work);
-
-   dev_priv->guc.log.flush_interrupt_count++;
-   } else {
-   /* Not clearing of unhandled event bits won't result in
-* re-triggering of the interrupt.
-*/
-   }
-   }
+   if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
+   intel_guc_to_host_event_handler(_priv->guc);
  }
  
  static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index ff08ea0ebf49..25f92291fd40 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -364,6 +364,43 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
return ret;
  }
  
+void intel_guc_to_host_event_handler(struct intel_guc *guc)

+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   u32 msg, flush;
+
+   /*
+* Sample the log buffer flush related bits & clear them out now
+* itself from the message identity register to minimize the
+* probability of losing a flush interrupt, when there are back
+* to back flush interrupts.

This paragraph is updated as:

                    /*
                 * Note: Logging protocol is, GuC will set the bit 
in message identity register and raise the GuC to Host
                 * interrupt and then Host will read the bit, clear 
it, copy the logs and send ack.
                 * If bits are cleared after sending ack, i915 
might lose next log flush interrupt if Host clear operation
                 * happens post GuC's update to message identity 
register corresponding to next interrupt.
                 * Hence, sample the log buffer flush related bits 
and clear them out now
                 * itself from the message identity register before 
sending ack to GuC about

                 * flush completion through guc_log_flush_complete.
                 */

and may be we can

Re: [Intel-gfx] [PATCH v2 02/15] drm/i915/guc: Create common entry points for log register/unregister

[Sagar Arun Kamble]

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

We have many functions responsible for allocating different parts of
GuC log runtime called from multiple places. Let's stick with keeping
everything in guc_log_register instead.

v2: Use more generic intel_uc_register name, keep using "misc" suffix (Michał)
 s/dev_priv/i915 (Sagar)
 Make guc_log_relay_* static (sparse)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_drv.c  |   6 +-
  drivers/gpu/drm/i915/intel_guc_log.c | 156 ++-
  drivers/gpu/drm/i915/intel_guc_log.h |   6 +-
  drivers/gpu/drm/i915/intel_uc.c  |  41 +
  drivers/gpu/drm/i915/intel_uc.h  |   2 +
  5 files changed, 95 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7c4de45644d..987c6770d1a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1238,9 +1238,11 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
i915_debugfs_register(dev_priv);
-   i915_guc_log_register(dev_priv);
i915_setup_sysfs(dev_priv);
  
+		/* Depends on debugfs having been initialized */

+   intel_uc_register(dev_priv);
+
/* Depends on sysfs having been initialized */
i915_perf_register(dev_priv);
} else
@@ -1298,7 +1300,7 @@ static void i915_driver_unregister(struct 
drm_i915_private *dev_priv)
i915_pmu_unregister(dev_priv);
  
  	i915_teardown_sysfs(dev_priv);

-   i915_guc_log_unregister(dev_priv);
+   intel_uc_unregister(dev_priv);
drm_dev_unregister(_priv->drm);
  
  	i915_gem_shrinker_unregister(dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 7e59fb07b06b..90b395f34808 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -443,7 +443,7 @@ void intel_guc_log_init_early(struct intel_guc *guc)
INIT_WORK(>log.runtime.flush_work, capture_logs_work);
  }
  
-int intel_guc_log_relay_create(struct intel_guc *guc)

+static int guc_log_relay_create(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct rchan *guc_log_relay_chan;
@@ -496,7 +496,7 @@ int intel_guc_log_relay_create(struct intel_guc *guc)
return ret;
  }
  
-void intel_guc_log_relay_destroy(struct intel_guc *guc)

+static void guc_log_relay_destroy(struct intel_guc *guc)
  {
mutex_lock(>log.runtime.relay_lock);
  
@@ -514,49 +514,6 @@ void intel_guc_log_relay_destroy(struct intel_guc *guc)

mutex_unlock(>log.runtime.relay_lock);
  }
  
-static int guc_log_late_setup(struct intel_guc *guc)

-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   int ret;
-
-   if (!guc_log_has_runtime(guc)) {
-   /*
-* If log was disabled at boot time, then setup needed to handle
-* log buffer flush interrupts would not have been done yet, so
-* do that now.
-*/
-   ret = intel_guc_log_relay_create(guc);
-   if (ret)
-   goto err;
-
-   mutex_lock(_priv->drm.struct_mutex);
-   intel_runtime_pm_get(dev_priv);
-   ret = guc_log_runtime_create(guc);
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
-
-   if (ret)
-   goto err_relay;
-   }
-
-   ret = guc_log_relay_file_create(guc);
-   if (ret)
-   goto err_runtime;
-
-   return 0;
-
-err_runtime:
-   mutex_lock(_priv->drm.struct_mutex);
-   guc_log_runtime_destroy(guc);
-   mutex_unlock(_priv->drm.struct_mutex);
-err_relay:
-   intel_guc_log_relay_destroy(guc);
-err:
-   /* logging will remain off */
-   i915_modparams.guc_log_level = 0;
-   return ret;
-}
-
  static void guc_log_capture_logs(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,16 +533,6 @@ static void guc_flush_logs(struct intel_guc *guc)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
  
-	if (!USES_GUC_SUBMISSION(dev_priv) || !i915_modparams.guc_log_level)

-   return;
-
-   /* First disable the interrupts, will be renabled afterwards */
-   mutex_lock(_priv->drm.struct_mutex);
-   intel_runtime_pm_get(dev_priv);
- 

Re: [Intel-gfx] [PATCH v2 01/15] drm/i915/guc: Tidy guc_log_control

[Sagar Arun Kamble]

On 3/8/2018 9:16 PM, Michał Winiarski wrote:

We plan to decouple log runtime (mapping + relay) from verbosity control.
Let's tidy the code now to reduce the churn in the following patches.

v2: Tidy macros, keep debug messages, use helper var for enable,
 correct typo (Michał)
 Fix incorrect input validaction (Sagar)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_debugfs.c  | 11 ++---
  drivers/gpu/drm/i915/intel_guc_log.c | 80 +---
  drivers/gpu/drm/i915/intel_guc_log.h |  3 +-
  3 files changed, 53 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 89f7ff2c652e..fa0755fe10d0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2500,13 +2500,10 @@ static int i915_guc_log_control_get(void *data, u64 
*val)
  {
struct drm_i915_private *dev_priv = data;
  
-	if (!HAS_GUC(dev_priv))

+   if (!USES_GUC(dev_priv))
return -ENODEV;
  
-	if (!dev_priv->guc.log.vma)

-   return -EINVAL;
-
-   *val = i915_modparams.guc_log_level;
+   *val = intel_guc_log_control_get(_priv->guc);
  
  	return 0;

  }
@@ -2515,10 +2512,10 @@ static int i915_guc_log_control_set(void *data, u64 val)
  {
struct drm_i915_private *dev_priv = data;
  
-	if (!HAS_GUC(dev_priv))

+   if (!USES_GUC(dev_priv))
return -ENODEV;
  
-	return intel_guc_log_control(_priv->guc, val);

+   return intel_guc_log_control_set(_priv->guc, val);
  }
  
  DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index c0c2e7d1c7d7..7e59fb07b06b 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -659,51 +659,63 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(>log.vma);
  }
  
-int intel_guc_log_control(struct intel_guc *guc, u64 control_val)

+int intel_guc_log_control_get(struct intel_guc *guc)
+{
+   GEM_BUG_ON(!guc->log.vma);
+   GEM_BUG_ON(i915_modparams.guc_log_level < 0);
+
+   return i915_modparams.guc_log_level;
+}
+
+#define GUC_LOG_LEVEL_DISABLED 0
+#define LOG_LEVEL_TO_ENABLED(x)((x) > 0)
+#define LOG_LEVEL_TO_VERBOSITY(x) ({   \
+   typeof(x) _x = (x); \
+   LOG_LEVEL_TO_ENABLED(_x) ? _x - 1 : 0;  \
+})
+#define VERBOSITY_TO_LOG_LEVEL(x)  ((x) + 1)
+int intel_guc_log_control_set(struct intel_guc *guc, u64 val)
  {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   bool enable_logging = control_val > 0;
-   u32 verbosity;
+   bool enabled = LOG_LEVEL_TO_ENABLED(val);
int ret;
  
-	if (!guc->log.vma)

-   return -ENODEV;
+   BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
+   GEM_BUG_ON(!guc->log.vma);
+   GEM_BUG_ON(i915_modparams.guc_log_level < 0);
  
-	BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN);

-   if (control_val > 1 + GUC_LOG_VERBOSITY_MAX)
+   /*
+* GuC is recognizing log levels starting from 0 to max, we're using 0
+* as indication that logging should be disabled.
+*/
+   if (val < GUC_LOG_LEVEL_DISABLED ||
+   val > VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX))
return -EINVAL;
  
-	/* This combination doesn't make sense & won't have any effect */

-   if (!enable_logging && !i915_modparams.guc_log_level)
-   return 0;
+   mutex_lock(_priv->drm.struct_mutex);
  
-	verbosity = enable_logging ? control_val - 1 : 0;

+   if (i915_modparams.guc_log_level == val) {
+   ret = 0;
+   goto out_unlock;
+   }
  
-	ret = mutex_lock_interruptible(_priv->drm.struct_mutex);

-   if (ret)
-   return ret;
intel_runtime_pm_get(dev_priv);
-   ret = guc_log_control(guc, enable_logging, verbosity);
+   ret = guc_log_control(guc, enabled, LOG_LEVEL_TO_VERBOSITY(val));
intel_runtime_pm_put(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
-
-   if (ret < 0) {
-   DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
-   return ret;
+   if (ret) {
+   DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
+   goto out_unlock;
}
  
-	if (enable_logging) {

-   i915_modparams.guc_log_level = 1 + verbosity;
+   i915_modparams.guc_log_level = val;
  
-		/*

-   

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/uc: Start preparing GuC/HuC for reset

[Sagar Arun Kamble]

On 3/5/2018 8:13 PM, Chris Wilson wrote:

Quoting Michal Wajdeczko (2018-03-05 14:29:16)

Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.

v2: s/reset_prepare/prepare_to_reset (Michel)
 don't forget about gem_sanitize path (Daniele)
v3: rebased

Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thie...@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
---
  drivers/gpu/drm/i915/i915_gem.c|  5 -
  drivers/gpu/drm/i915/intel_guc.h   |  5 +
  drivers/gpu/drm/i915/intel_huc.h   |  5 +
  drivers/gpu/drm/i915/intel_uc.c| 14 ++
  drivers/gpu/drm/i915/intel_uc.h|  1 +
  drivers/gpu/drm/i915/intel_uc_fw.h |  6 ++
  6 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a5bd073..aedb17d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2981,6 +2981,7 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
 }
  
 i915_gem_revoke_fences(dev_priv);

+   intel_uc_prepare_to_reset(dev_priv);
  
 return err;

  }
@@ -4882,8 +4883,10 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
  * it may impact the display and we are uncertain about the stability
  * of the reset, so this could be applied to even earlier gen.
  */
-   if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
+   if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) {
+   intel_uc_prepare_to_reset(i915);
 WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));

This still feels wrong. If we accept that we will have to reload the fw
on resume, why are we not just sanitzing the uc state and forcing the
reload?

Hi Chris,

intel_uc_prepare_to_reset() is sanitizing uc state and reload is 
happening through gem_init_hw in resume path.

what are we missing?

Thanks,
Sagar

-Chris


--
Thanks,
Sagar

___
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Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Default to non-verbose GuC logging

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

Now that we've decoupled logging from relay, GuC log level is only
controlling the GuC behavior - there shouldn't be any impact on i915
behaviour. We're only going to see a single extra interrupt when log
will get half full.
That, and the fact that we're seeing igt/gem_exec_nop/basic-series
failing with non-verbose logging being disabled.

Looks like gem_sync is now passing with non-verbose logging disabled :)

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_uc.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9884a79c77bd..cd6203740c07 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -69,7 +69,7 @@ static int __get_platform_enable_guc(struct drm_i915_private 
*dev_priv)
  
  static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)

  {
-   int guc_log_level = 0; /* disabled */
+   int guc_log_level = 1; /* non-verbose */
  
  	/* Enable if we're running on platform with GuC and debug config */

if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&


--
Thanks,
Sagar

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

[Sagar Arun Kamble]

I think we should also clear the stats.count and relay_full_count on 
relay_open.


Thanks
Sagar

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

If nobody has enabled the relay, we're not comunicating with GuC, which
means that the stats don't have any meaning. Let's also remove interrupt
counter and tidy the debugfs formatting.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 47 
  drivers/gpu/drm/i915/intel_guc.c |  5 +---
  drivers/gpu/drm/i915/intel_guc_log.c | 24 +-
  drivers/gpu/drm/i915/intel_guc_log.h | 12 +
  4 files changed, 51 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 866d44a091b3..65f758f7c425 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2326,30 +2326,45 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
return 0;
  }
  
+static const char *

+stringify_guc_log_type(enum guc_log_buffer_type type)
+{
+   switch (type) {
+   case GUC_ISR_LOG_BUFFER:
+   return "ISR";
+   case GUC_DPC_LOG_BUFFER:
+   return "DPC";
+   case GUC_CRASH_DUMP_LOG_BUFFER:
+   return "CRASH";
+   default:
+   MISSING_CASE(type);
+   }
+
+   return "";
+}
+
  static void i915_guc_log_info(struct seq_file *m,
  struct drm_i915_private *dev_priv)
  {
struct intel_guc *guc = _priv->guc;
+   enum guc_log_buffer_type type;
  
-	seq_puts(m, "GuC logging stats:\n");

-
-   seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_ISR_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
-
-   seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_DPC_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
+   if (!intel_guc_log_relay_enabled(guc)) {
+   seq_puts(m, "GuC log relay disabled\n");
+   return;
+   }
  
-	seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",

-  guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
+   seq_puts(m, "GuC logging stats:\n");
  
-	seq_printf(m, "\tTotal flush interrupt count: %u\n",

-  guc->log.flush_interrupt_count);
+   seq_printf(m, "\tRelay full count: %u\n",
+  guc->log.relay_full_count);
  
-	seq_printf(m, "\tCapture miss count: %u\n",

-  guc->log.capture_miss_count);
+   for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
+  stringify_guc_log_type(type),
+  guc->log.stats[type].flush,
+  guc->log.stats[type].overflow);
+   }
  }
  
  static void i915_guc_client_info(struct seq_file *m,

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e3b6ae158a12..0500b4164254 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -388,12 +388,9 @@ void intel_guc_notification_handler(struct intel_guc *guc)
spin_unlock(>irq_lock);
  
  	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

-  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
+  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
queue_work(guc->log.flush_wq,
   >log.flush_work);
-
-   guc->log.flush_interrupt_count++;
-   }
  }
  
  int intel_guc_sample_forcewake(struct intel_guc *guc)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index f95e18be1c5f..bdf6b3178488 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -176,22 +176,22 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
return relay_reserve(guc->log.relay_chan, 0);
  }
  
-static bool guc_check_log_buf_overflow(struct intel_guc *guc,

+static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
   enum guc_log_buffer_type type,
   unsigned int full_cnt)
  {
-   unsigned int prev_full

Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc: Allow user to control default GuC logging

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

While both naming and actual log enable logic in GuC interface are
confusing, we can simply expose the default log as yet another log
level.
GuC logic aside, from i915 point of view we now have the following GuC
log levels:
0 Log disabled
1 Non-verbose log
2-5 Verbose log

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Change looks good.
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

Firmware should have enabled default logging internally without user 
controls or should have created new verbosity level.
This was supposed to be fixed in the firmware based on the discussion 
here https://patchwork.freedesktop.org/patch/178281/
Until this gets fixed in firmware, this patch will be needed for 
multiple log captures.

---
  drivers/gpu/drm/i915/intel_guc.c  | 21 -
  drivers/gpu/drm/i915/intel_guc_fwif.h |  5 +++--
  drivers/gpu/drm/i915/intel_guc_log.c  |  9 +
  drivers/gpu/drm/i915/intel_guc_log.h  | 11 +++
  drivers/gpu/drm/i915/intel_uc.c   | 14 +-
  5 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 0500b4164254..83d813a6ff92 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -221,17 +221,20 @@ static u32 get_core_family(struct drm_i915_private 
*dev_priv)
}
  }
  
-static u32 get_log_verbosity_flags(void)

+static u32 get_log_control_flags(void)
  {
-   if (i915_modparams.guc_log_level > 0) {
-   u32 verbosity = i915_modparams.guc_log_level - 1;
+   u32 level = i915_modparams.guc_log_level;
+   u32 flags = 0;
  
-		GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);

-   return verbosity << GUC_LOG_VERBOSITY_SHIFT;
-   }
+   GEM_BUG_ON(level < 0);
+
+   if (!GUC_LOG_IS_ENABLED(level))
+   flags = GUC_LOG_DEFAULT_DISABLED | GUC_LOG_DISABLED;
+   else if (GUC_LOG_IS_VERBOSE(level))
+   flags = GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
+   GUC_LOG_VERBOSITY_SHIFT;
  
-	GEM_BUG_ON(i915_modparams.enable_guc < 0);

-   return GUC_LOG_DISABLED;
+   return flags;
  }
  
  /*

@@ -266,7 +269,7 @@ void intel_guc_init_params(struct intel_guc *guc)
  
  	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
  
-	params[GUC_CTL_DEBUG] = get_log_verbosity_flags();

+   params[GUC_CTL_DEBUG] = get_log_control_flags();
  
  	/* If GuC submission is enabled, set up additional parameters here */

if (USES_GUC_SUBMISSION(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 6a10aa6f04d3..4971685a2ea8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -127,7 +127,7 @@
  #define   GUC_PROFILE_ENABLED (1 << 7)
  #define   GUC_WQ_TRACK_ENABLED(1 << 8)
  #define   GUC_ADS_ENABLED (1 << 9)
-#define   GUC_DEBUG_RESERVED   (1 << 10)
+#define   GUC_LOG_DEFAULT_DISABLED (1 << 10)
  #define   GUC_ADS_ADDR_SHIFT  11
  #define   GUC_ADS_ADDR_MASK   0xf800
  
@@ -539,7 +539,8 @@ union guc_log_control {

u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
-   u32 reserved2:24;
+   u32 default_logging:1;
+   u32 reserved2:23;
};
u32 value;
  } __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index bdf6b3178488..ade7dadc34b8 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -58,11 +58,13 @@ static int guc_log_flush(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
  }
  
-static int guc_log_control(struct intel_guc *guc, bool enable, u32 verbosity)

+static int guc_log_control(struct intel_guc *guc, bool enable,
+  bool default_logging, u32 verbosity)
  {
union guc_log_control control_val = {
.logging_enabled = enable,
.verbosity = verbosity,
+   .default_logging = default_logging,
};
u32 action[] = {
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
@@ -506,8 +508,6 @@ int intel_guc_log_level_get(struct intel_guc *guc)
return i915_modparams.guc_log_level;
  }
  
-#define GUC_LOG_IS_ENABLED(x)		(x > 0)

-#define GUC_LOG_LEVEL_TO_VERBOSITY(x)  (GUC_LOG_IS_ENABLED(x) ? x - 1 : 0)
  int intel_guc_log_level_set(struct intel_guc *guc, u64 val)
  {
struc

Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc: Don't print out relay statistics when relay is disabled

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

If nobody has enabled the relay, we're not comunicating with GuC, which
means that the stats don't have any meaning. Let's also remove interrupt
counter

reason for this? I think this was needed for verifying log flushes.

  and tidy the debugfs formatting.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 47 
  drivers/gpu/drm/i915/intel_guc.c |  5 +---
  drivers/gpu/drm/i915/intel_guc_log.c | 24 +-
  drivers/gpu/drm/i915/intel_guc_log.h | 12 +
  4 files changed, 51 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 866d44a091b3..65f758f7c425 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2326,30 +2326,45 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
return 0;
  }
  
+static const char *

+stringify_guc_log_type(enum guc_log_buffer_type type)
+{
+   switch (type) {
+   case GUC_ISR_LOG_BUFFER:
+   return "ISR";
+   case GUC_DPC_LOG_BUFFER:
+   return "DPC";
+   case GUC_CRASH_DUMP_LOG_BUFFER:
+   return "CRASH";
+   default:
+   MISSING_CASE(type);
+   }
+
+   return "";
+}
+
  static void i915_guc_log_info(struct seq_file *m,
  struct drm_i915_private *dev_priv)
  {
struct intel_guc *guc = _priv->guc;
+   enum guc_log_buffer_type type;
  
-	seq_puts(m, "GuC logging stats:\n");

-
-   seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_ISR_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
-
-   seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
-  guc->log.flush_count[GUC_DPC_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
+   if (!intel_guc_log_relay_enabled(guc)) {
+   seq_puts(m, "GuC log relay disabled\n");
+   return;
+   }
  
-	seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",

-  guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
-  guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
+   seq_puts(m, "GuC logging stats:\n");
  
-	seq_printf(m, "\tTotal flush interrupt count: %u\n",

-  guc->log.flush_interrupt_count);
+   seq_printf(m, "\tRelay full count: %u\n",
+  guc->log.relay_full_count);
  
-	seq_printf(m, "\tCapture miss count: %u\n",

-  guc->log.capture_miss_count);
+   for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
+  stringify_guc_log_type(type),
+  guc->log.stats[type].flush,
+  guc->log.stats[type].overflow);
+   }
  }
  
  static void i915_guc_client_info(struct seq_file *m,

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e3b6ae158a12..0500b4164254 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -388,12 +388,9 @@ void intel_guc_notification_handler(struct intel_guc *guc)
spin_unlock(>irq_lock);
  
  	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

-  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
+  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
queue_work(guc->log.flush_wq,
   >log.flush_work);
-
-   guc->log.flush_interrupt_count++;
-   }
  }
  
  int intel_guc_sample_forcewake(struct intel_guc *guc)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index f95e18be1c5f..bdf6b3178488 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -176,22 +176,22 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
return relay_reserve(guc->log.relay_chan, 0);
  }
  
-static bool guc_check_log_buf_overflow(struct intel_guc *guc,

+static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
   enum guc_log_buffer_type type,
   unsigned int full_cnt)
  {
-   unsigned int prev_full_cnt = guc->log.prev_overfl

Re: [Intel-gfx] [PATCH 10/15] drm/i915/guc: Get rid of GuC log runtime

[Sagar Arun Kamble]

I think keeping the distinction between base/mandatory members and 
runtime/optional members is okay as they are handled differently.

What do others think?

another related query, should we alloc/dealloc guc_log work queue in 
relay_open/release?


On 2/27/2018 6:22 PM, Michał Winiarski wrote:

Keeping a separate runtime struct is only making the code dealing with
relay less clear to read. Let's get rid of it, keeping everything in the
log instead.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
  drivers/gpu/drm/i915/intel_guc.c | 14 
  drivers/gpu/drm/i915/intel_guc_log.c | 68 ++--
  drivers/gpu/drm/i915/intel_guc_log.h | 13 +++
  3 files changed, 46 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 41f2c3b3c482..e3b6ae158a12 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -87,9 +87,9 @@ int intel_guc_init_wq(struct intel_guc *guc)
 * or scheduled later on resume. This way the handling of work
 * item can be kept same between system suspend & rpm suspend.
 */
-   guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
-   WQ_HIGHPRI | WQ_FREEZABLE);
-   if (!guc->log.runtime.flush_wq) {
+   guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
+   WQ_HIGHPRI | WQ_FREEZABLE);
+   if (!guc->log.flush_wq) {
DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
return -ENOMEM;
}
@@ -112,7 +112,7 @@ int intel_guc_init_wq(struct intel_guc *guc)
guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
  WQ_HIGHPRI);
if (!guc->preempt_wq) {
-   destroy_workqueue(guc->log.runtime.flush_wq);
+   destroy_workqueue(guc->log.flush_wq);
DRM_ERROR("Couldn't allocate workqueue for GuC "
  "preemption\n");
return -ENOMEM;
@@ -130,7 +130,7 @@ void intel_guc_fini_wq(struct intel_guc *guc)
USES_GUC_SUBMISSION(dev_priv))
destroy_workqueue(guc->preempt_wq);
  
-	destroy_workqueue(guc->log.runtime.flush_wq);

+   destroy_workqueue(guc->log.flush_wq);
  }
  
  static int guc_shared_data_create(struct intel_guc *guc)

@@ -389,8 +389,8 @@ void intel_guc_notification_handler(struct intel_guc *guc)
  
  	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) {
-   queue_work(guc->log.runtime.flush_wq,
-  >log.runtime.flush_work);
+   queue_work(guc->log.flush_wq,
+  >log.flush_work);
  
  		guc->log.flush_interrupt_count++;

}
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index d2aca10ab986..f95e18be1c5f 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -156,10 +156,10 @@ static void guc_move_to_next_buf(struct intel_guc *guc)
smp_wmb();
  
  	/* All data has been written, so now move the offset of sub buffer. */

-   relay_reserve(guc->log.runtime.relay_chan, 
guc->log.vma->obj->base.size);
+   relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size);
  
  	/* Switch to the next sub buffer */

-   relay_flush(guc->log.runtime.relay_chan);
+   relay_flush(guc->log.relay_chan);
  }
  
  static void *guc_get_write_buffer(struct intel_guc *guc)

@@ -173,7 +173,7 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
 * done without using relay_reserve() along with relay_write(). So its
 * better to use relay_reserve() alone.
 */
-   return relay_reserve(guc->log.runtime.relay_chan, 0);
+   return relay_reserve(guc->log.relay_chan, 0);
  }
  
  static bool guc_check_log_buf_overflow(struct intel_guc *guc,

@@ -224,11 +224,11 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
void *src_data, *dst_data;
bool new_overflow;
  
-	if (WARN_ON(!guc->log.runtime.buf_addr))

+   if (WARN_ON(!guc->log.buf_addr))
return;
  
  	/* Get the pointer to shared GuC log buffer */

-   log_buf_state = src_data = guc->log.runtime.buf_addr;
+   log_buf_state = src_data = guc->log.buf_addr;
  
  	/* Get the pointe

Re: [Intel-gfx] [PATCH 11/15] drm/i915/guc: Always print log stats in i915_guc_info when using GuC

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

While some of the content in this file is related to GuC submission
only, that's not the case with log related statistics.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/i915_debugfs.c | 15 +--
  1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4bd24bbe7966..866d44a091b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2331,7 +2331,7 @@ static void i915_guc_log_info(struct seq_file *m,
  {
struct intel_guc *guc = _priv->guc;
  
-	seq_puts(m, "\nGuC logging stats:\n");

+   seq_puts(m, "GuC logging stats:\n");
  
  	seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",

   guc->log.flush_count[GUC_ISR_LOG_BUFFER],
@@ -2379,14 +2379,19 @@ static int i915_guc_info(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = _priv->guc;
  
-	if (!USES_GUC_SUBMISSION(dev_priv))

+   if (!USES_GUC(dev_priv))
return -ENODEV;
  
+	i915_guc_log_info(m, dev_priv);

+
+   if (!USES_GUC_SUBMISSION(dev_priv))
+   return 0;
+
GEM_BUG_ON(!guc->execbuf_client);
  
-	seq_printf(m, "Doorbell map:\n");

+   seq_printf(m, "\nDoorbell map:\n");
seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
-   seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
+   seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);
  
  	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);

i915_guc_client_info(m, dev_priv, guc->execbuf_client);
@@ -2396,8 +2401,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
i915_guc_client_info(m, dev_priv, guc->preempt_client);
}
  
-	i915_guc_log_info(m, dev_priv);

-
/* Add more as required ... */
  
  	return 0;


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH 09/15] drm/i915/guc: Move check for fast memcpy_wc to relay creation

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

We only need those fast memcpy_wc when we're using relay to read
continuous GuC log. Let's prevent the user from creating a relay if we
know we won't be able to keep up with GuC.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

---
  drivers/gpu/drm/i915/intel_guc_log.c | 20 ++--
  1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 4dee65692f5f..d2aca10ab986 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -452,16 +452,6 @@ int intel_guc_log_create(struct intel_guc *guc)
  
  	GEM_BUG_ON(guc->log.vma);
  
-	/*

-* We require SSE 4.1 for fast reads from the GuC log buffer and
-* it should be present on the chipsets supporting GuC based
-* submisssions.
-*/
-   if (WARN_ON(!i915_has_memcpy_from_wc())) {
-   ret = -EINVAL;
-   goto err;
-   }
-
vma = intel_guc_allocate_vma(guc, GUC_LOG_SIZE);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
@@ -568,6 +558,16 @@ int intel_guc_log_relay_open(struct intel_guc *guc)
goto out_unlock;
}
  
+	/*

+* We require SSE 4.1 for fast reads from the GuC log buffer and
+* it should be present on the chipsets supporting GuC based
+* submisssions.
+*/
+   if (!i915_has_memcpy_from_wc()) {
+   ret = -EINVAL;
+   goto out_unlock;
+   }
+
ret = guc_log_relay_create(guc);
if (ret)
goto out_unlock;


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH 08/15] drm/i915/guc: Split relay control and GuC log level

[Sagar Arun Kamble]

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

Those two concepts are really separate. Since GuC is writing data into
its own buffer and we even provide a way for userspace to read directly
from it using i915_guc_log_dump debugfs, there's no real reason to tie
log level with relay creation.
Let's create a separate debugfs, giving userspace a way to create a
relay on demand, when it wants to read a continuous log rather than a
snapshot.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 56 ++
  drivers/gpu/drm/i915/i915_drv.c  |  2 -
  drivers/gpu/drm/i915/intel_guc_log.c | 76 +++-
  drivers/gpu/drm/i915/intel_guc_log.h |  9 +++--
  drivers/gpu/drm/i915/intel_uc.c  | 22 ---
  drivers/gpu/drm/i915/intel_uc.h  |  2 -
  6 files changed, 86 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 58983cafaece..4bd24bbe7966 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2496,32 +2496,73 @@ static int i915_guc_log_dump(struct seq_file *m, void 
*data)
return 0;
  }
  
-static int i915_guc_log_control_get(void *data, u64 *val)

+static int i915_guc_log_level_get(void *data, u64 *val)
  {
struct drm_i915_private *dev_priv = data;

s/dev_priv/i915 here and at other places
  
  	if (!USES_GUC(dev_priv))

return -ENODEV;
  
-	*val = intel_guc_log_control_get(_priv->guc);

+   *val = intel_guc_log_level_get(_priv->guc);
  
  	return 0;

  }
  
-static int i915_guc_log_control_set(void *data, u64 val)

+static int i915_guc_log_level_set(void *data, u64 val)
  {
struct drm_i915_private *dev_priv = data;
  
  	if (!USES_GUC(dev_priv))

return -ENODEV;
  
-	return intel_guc_log_control_set(_priv->guc, val);

+   return intel_guc_log_level_set(_priv->guc, val);
  }
  
-DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,

-   i915_guc_log_control_get, i915_guc_log_control_set,
+DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
+   i915_guc_log_level_get, i915_guc_log_level_set,
"%lld\n");
  
+static int i915_guc_log_relay_open(struct inode *inode, struct file *file)

+{
+   struct drm_i915_private *dev_priv = inode->i_private;
+
+   if (!USES_GUC(dev_priv))
+   return -ENODEV;
+
+   file->private_data = dev_priv;
+
write is passing guc struct so should we just set private_data to 
_priv->guc?

+   return intel_guc_log_relay_open(_priv->guc);
+}
+
+static ssize_t
+i915_guc_log_relay_write(struct file *filp,
+const char __user *ubuf,
+size_t cnt,
+loff_t *ppos)
+{
+   struct drm_i915_private *dev_priv = filp->private_data;
+
+   intel_guc_log_relay_flush(_priv->guc);
+
+   return cnt;
+}



+void intel_guc_log_relay_close(struct intel_guc *guc)
+{
GEM_BUG_ON(!guc_log_has_runtime(guc));
  

guc_log_has_runtime() check has to be with runtime.lock mutex locked.

With comments addressed:
Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>

+   guc_log_flush_irq_disable(guc);
+   flush_work(>log.runtime.flush_work);
+
+   mutex_lock(>log.runtime.lock);
guc_log_unmap(guc);
guc_log_relay_destroy(guc);
-
mutex_unlock(>log.runtime.lock);
  }
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h 
b/drivers/gpu/drm/i915/intel_guc_log.h
index 8c26cce77a98..df91f12a36ed 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -61,9 +61,10 @@ struct intel_guc_log {
  int intel_guc_log_create(struct intel_guc *guc);
  void intel_guc_log_destroy(struct intel_guc *guc);
  void intel_guc_log_init_early(struct intel_guc *guc);
-int intel_guc_log_control_get(struct intel_guc *guc);
-int intel_guc_log_control_set(struct intel_guc *guc, u64 control_val);
-int intel_guc_log_register(struct intel_guc *guc);
-void intel_guc_log_unregister(struct intel_guc *guc);
+int intel_guc_log_level_get(struct intel_guc *guc);
+int intel_guc_log_level_set(struct intel_guc *guc, u64 control_val);
+int intel_guc_log_relay_open(struct intel_guc *guc);
+void intel_guc_log_relay_close(struct intel_guc *guc);
+void intel_guc_log_relay_flush(struct intel_guc *guc);
  
  #endif

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 55a9b5b673e0..27e1f4c43b7b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -219,28 +219,6 @@ static void guc_free_load

Re: [Intel-gfx] [PATCH 05/15] drm/i915/guc: Log runtime should consist of both mapping and relay

[Sagar Arun Kamble]

On 3/5/2018 7:44 PM, Michał Winiarski wrote:

On Mon, Mar 05, 2018 at 04:01:18PM +0530, Sagar Arun Kamble wrote:


On 2/27/2018 6:22 PM, Michał Winiarski wrote:

Currently, we're treating relay and mapping of GuC log as a separate
concepts. We're also using inconsistent locking, sometimes using
relay_lock, sometimes using struct mutex.
Let's correct that. Anything touching the runtime is now serialized
using runtime.lock, while we're still using struct mutex as inner lock
for mapping.
We're still racy in setting the log level - but we'll take care of that
in the following patches.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
   drivers/gpu/drm/i915/intel_guc_log.c | 110 
++-
   drivers/gpu/drm/i915/intel_guc_log.h |   3 +-
   drivers/gpu/drm/i915/intel_uc.c  |  14 +++--
   3 files changed, 42 insertions(+), 85 deletions(-)


[SNIP]



How strongly do you feel about this one?
I wanted to tidy first (decouple things), rename later.

fine. it's ok.

INIT_WORK(>log.runtime.flush_work, capture_logs_work);
   }
@@ -448,12 +418,7 @@ int guc_log_relay_create(struct intel_guc *guc)
size_t n_subbufs, subbuf_size;
int ret;
-   if (!i915_modparams.guc_log_level)
-   return 0;
-
-   mutex_lock(>log.runtime.relay_lock);
-
-   GEM_BUG_ON(guc_log_has_relay(guc));
+   lockdep_assert_held(>log.runtime.lock);
 /* Keep the size of sub buffers same as shared log buffer */
subbuf_size = GUC_LOG_SIZE;
@@ -483,12 +448,9 @@ int guc_log_relay_create(struct intel_guc *guc)
GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
guc->log.runtime.relay_chan = guc_log_relay_chan;
-   mutex_unlock(>log.runtime.relay_lock);
-
return 0;
   err:
-   mutex_unlock(>log.runtime.relay_lock);
/* logging will be off */
i915_modparams.guc_log_level = 0;

This log_level decoupling is not taken care

Yup, though it belongs in "drm/i915/guc: Split relay control and GuC log level",
I'll add it there.


return ret;
@@ -496,20 +458,10 @@ int guc_log_relay_create(struct intel_guc *guc)
   void guc_log_relay_destroy(struct intel_guc *guc)
   {
-   mutex_lock(>log.runtime.relay_lock);
-
-   /*
-* It's possible that the relay was never allocated because
-* GuC log was disabled at the boot time.
-*/
-   if (!guc_log_has_relay(guc))
-   goto out_unlock;
+   lockdep_assert_held(>log.runtime.lock);
relay_close(guc->log.runtime.relay_chan);
guc->log.runtime.relay_chan = NULL;
-
-out_unlock:
-   mutex_unlock(>log.runtime.relay_lock);
   }
   static void guc_log_capture_logs(struct intel_guc *guc)
@@ -608,7 +560,6 @@ static void guc_log_flush_irq_disable(struct intel_guc *guc)
   void intel_guc_log_destroy(struct intel_guc *guc)
   {
-   guc_log_runtime_destroy(guc);
i915_vma_unpin_and_release(>log.vma);
   }
@@ -678,9 +629,10 @@ int intel_guc_log_control_set(struct intel_guc *guc, u64 
val)
   int intel_guc_log_register(struct intel_guc *guc)
   {
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
int ret;
+   mutex_lock(>log.runtime.lock);
+
GEM_BUG_ON(guc_log_has_runtime(guc));
/*
@@ -692,35 +644,33 @@ int intel_guc_log_register(struct intel_guc *guc)
if (ret)
goto err;
-   mutex_lock(_priv->drm.struct_mutex);
-   ret = guc_log_runtime_create(guc);
-   mutex_unlock(_priv->drm.struct_mutex);
-
+   ret = guc_log_map(guc);
if (ret)
goto err_relay;
ret = guc_log_relay_file_create(guc);
if (ret)
-   goto err_runtime;
+   goto err_unmap;
guc_log_flush_irq_enable(guc);
+   mutex_unlock(>log.runtime.lock);
+
return 0;
-err_runtime:
-   mutex_lock(_priv->drm.struct_mutex);
-   guc_log_runtime_destroy(guc);
-   mutex_unlock(_priv->drm.struct_mutex);
+err_unmap:
+   guc_log_unmap(guc);
   err_relay:
guc_log_relay_destroy(guc);
   err:
+   mutex_unlock(>log.runtime.lock);
+
return ret;
   }
   void intel_guc_log_unregister(struct intel_guc *guc)
   {
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
+   guc_log_flush_irq_disable(guc);

This move could be part of earlier patch.

/*
 * Once logging is disabled, GuC won't generate logs & send an
 * interrupt. But there could be some data in the log buffer
@@ -728,11 +678,13 @@ void intel_guc_log_unregister(struct intel_guc *guc)
 * buffer state and then collect the left over logs.
 */

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Create common entry points for log register/unregister

[Sagar Arun Kamble]

On 3/5/2018 7:08 PM, Michał Winiarski wrote:

On Mon, Mar 05, 2018 at 12:39:58PM +0530, Sagar Arun Kamble wrote:

Overall change looks good. Could you please clarify on below:

intel_uc_log_register|unregister are removed in patch later in the series.
Should we just stay with inner functions then to minimize changes?

I've done this to move (USES_GUC/guc_log_level) checks to the callers. Otherwise
it would need to stay in intel_guc_log_register, which would cause us to do more
changes in intel_guc_log_control_set later in the series (when we're actually
doing the decoupling).
But AFAIU change in that patch (8/15) will be decoupling 
guc_log_register from USES_GUC/guc_log_level which would be fine I guess.

Your call :)

-Michał



Thanks
Sagar

On 2/27/2018 6:22 PM, Michał Winiarski wrote:

We have many functions responsible for allocating different parts of
runtime called from multiple places. Let's stick with keeping
everything in guc_log_register instead.

Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
   drivers/gpu/drm/i915/i915_drv.c  |   6 +-
   drivers/gpu/drm/i915/i915_gem.c  |   4 +-
   drivers/gpu/drm/i915/intel_guc_log.c | 148 
++-
   drivers/gpu/drm/i915/intel_guc_log.h |   6 +-
   drivers/gpu/drm/i915/intel_uc.c  |  39 -
   drivers/gpu/drm/i915/intel_uc.h  |   6 +-
   6 files changed, 91 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b51024..719b2be73292 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -636,7 +636,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_contexts_fini(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
-   intel_uc_fini_misc(dev_priv);
+   intel_uc_fini_wq(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
i915_gem_drain_freed_objects(dev_priv);
@@ -1237,7 +1237,7 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
i915_debugfs_register(dev_priv);
-   i915_guc_log_register(dev_priv);
+   intel_uc_log_register(dev_priv);
i915_setup_sysfs(dev_priv);
/* Depends on sysfs having been initialized */
@@ -1297,7 +1297,7 @@ static void i915_driver_unregister(struct 
drm_i915_private *dev_priv)
i915_pmu_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
-   i915_guc_log_unregister(dev_priv);
+   intel_uc_log_unregister(dev_priv);
drm_dev_unregister(_priv->drm);
i915_gem_shrinker_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b1a3a4..4bf5f25b29e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5279,7 +5279,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
return ret;
-   ret = intel_uc_init_misc(dev_priv);
+   ret = intel_uc_init_wq(dev_priv);
if (ret)
return ret;
@@ -5375,7 +5375,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-   intel_uc_fini_misc(dev_priv);
+   intel_uc_fini_wq(dev_priv);
if (ret != -EIO)
i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 22a05320817b..f1cab43d334e 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -441,7 +441,7 @@ void intel_guc_log_init_early(struct intel_guc *guc)
INIT_WORK(>log.runtime.flush_work, capture_logs_work);
   }
-int intel_guc_log_relay_create(struct intel_guc *guc)
+int guc_log_relay_create(struct intel_guc *guc)
   {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct rchan *guc_log_relay_chan;
@@ -494,7 +494,7 @@ int intel_guc_log_relay_create(struct intel_guc *guc)
return ret;
   }
-void intel_guc_log_relay_destroy(struct intel_guc *guc)
+void guc_log_relay_destroy(struct intel_guc *guc)
   {
mutex_lock(>log.runtime.relay_lock);
@@ -512,49 +512,6 @@ void intel_guc_log_relay_destroy(struct intel_guc *guc)
mutex_unlock(>log.runtime.relay_lock);
   }
-static int guc_log_late_setup(struct intel_guc *guc)
-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   int ret;
-
-   if (!guc_log_has_runtime(guc)) {
-   /*
-* If log was disabled at boot time, then setu