From: Tom O'Rourke Tom.O'rou...@intel.com
The efficient frequency (RPe) should stay in the range
RPn = RPe = RP0. The pcode clamps the returned value
internally on Broadwell but not on Haswell.
Fix for missing range check in
commit 93ee29203f506582cca2bcec5f05041526d9ab0a
Author: Tom O'Rourke
From: Tom O'Rourke Tom.O'rou...@intel.com
These patches update the turbo minimum frequency to
match the values used for Windows and Android.
v2: Updated patches 1 and 2 based on comments
from Daniel and Chris. Added 2 related patches.
Tom O'Rourke (4):
drm/i915: Use efficient frequency
From: Tom O'Rourke Tom.O'rou...@intel.com
Set the min_freq_softlimit to max(RPe, 450MHz).
Setting a floor can ensure a minimum experience
level. The 450MHz value came from a power and
performance study of various types of workloads
(3D, Media, GPGPU, idle, etc).
v2: rebased
Signed-off-by: Tom
From: Tom O'Rourke Tom.O'rou...@intel.com
In gen8_enable_rps, change the initial rps setting
to the min_freq_softlimit (same as gen6_enable_rps).
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion
From: Tom O'Rourke Tom.O'rou...@intel.com
In __gen6_update_ring_freq, use the full range of
possible gpu frequencies from max_freq to min_freq.
The actual gpu frequency could be outside the range
from max_freq_softlimit to min_freq_softlimit due
to power/thermal constraints.
Signed-off-by: Tom
From: Tom O'Rourke Tom.O'rou...@intel.com
Added gen6_init_rps_frequencies() to initialize
the rps frequency values. This function replaces
parse_rp_state_cap(). In addition to reading RPn,
RP0, and RP1 from RP_STATE_CAP register, the new
function reads efficient frequency (aka RPe) from
pcode
From: Tom O'Rourke Tom.O'rou...@intel.com
In sandybridge_pcode_read and sandybridge_pcode_write,
extend the mbox parameter from u8 to u32.
On Haswell and Sandybridge, bits 7:0 encode the mailbox
command and bits 28:8 are used for address control for
specific commands.
Based on suggestion from
From: Tom O'Rourke Tom.O'rou...@intel.com
Updated gen6|8_enable_rps() for Haswell and Broadwell
to use the efficient frequency read from pcode.
Added hsw_use_efficient_freq() to read efficient
frequency (aka RPe) from pcode. The efficiency is
based on the frequency/power ratio (MHz/W
From: Tom O'Rourke Tom.O'rou...@intel.com
Set the min_freq_softlimit to max(RPe, 450MHz).
Setting a floor can ensure a minimum experience
level. The 450MHz value came from a power and
performance study of various types of workloads
(3D, Media, GPGPU, idle, etc).
Signed-off-by: Tom O'Rourke
From: Tom O'Rourke Tom.O'rou...@intel.com
These patches update the turbo minimum frequency to
match the values used for Windows and Android. The
refactoring in Imre's recent series
[Intel-gfx] [PATCH 0/8] sanitize RPS interrupt enabling/disabling
conflicts with these changes. Those
From: Tom O'Rourke Tom.O'rou...@intel.com
Based on sandybridge_pcode_write, haswell_pcode_write has an
additional field for address control.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm
From: Tom O'Rourke Tom.O'rou...@intel.com
Correct a merge mishap in commit e4443e459ccf43f2c139358400365fd6a839d40d.
Wa*:chv belongs in cherryview_enable_rps, not gen8_enable_rps.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
1 file
From: Tom O'Rourke Tom.O'rou...@intel.com
In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIEW.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Tom O'Rourke Tom.O'rou...@intel.com
Add Broadwell support to i915_frequency_info
and extend i915_max|min_freq_get|set to (gen = 6).
v2: generalized support for i915_max|min_freq_get|set (Daniel).
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c
From: Tom O'Rourke Tom.O'rou...@intel.com
Add Broadwell support to i915_frequency_info and i915_max|min_freq_get|set.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git
Higher RC6 residency is observed using timeout mode
instead of EI mode. This applies to Broadwell only.
The difference is particularly noticeable with video
playback.
Issue: VIZ-3778
Change-Id: I62bb12e21caf19651034826b45cde7f73a80938d
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
From: Tom O'Rourke Tom.O'rou...@intel.com
Enabling rps (turbo setup) was put in a work queue because it may
take quite awhile. This change flushes the work queue to initialize
rps values before use by sysfs or debugfs. Specifically,
rps.delayed_resume_work is flushed before using rps.hw_max
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