On Fri, Nov 07, 2014 at 07:34:31AM -0800, Neil Roberts wrote:
The predicate source registers are needed to implement conditional
rendering without stalling. The two source registers are used to load
the previous values of the PS_DEPTH_COUNT register saved from
PIPE_CONTROL commands. These can
On Thu, Nov 06, 2014 at 05:56:36AM -0800, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 07:36:55AM +, Chris Wilson wrote:
On Wed, Nov 05, 2014 at 02:42:00PM -0800, Volkin, Bradley D wrote:
For this part, I've got an implementation that works ok but one
difference is
that if we stop
Ping on this series. They're related to the batch copy series, but
the changes are valid and tests should still pass even without the
kernel changes being merged.
On Mon, Nov 03, 2014 at 11:18:59AM -0800, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol...@intel.com
The size
[snip]
On Wed, Nov 05, 2014 at 01:50:24AM -0800, Daniel Vetter wrote:
On Tue, Nov 04, 2014 at 08:35:00AM -0800, Volkin, Bradley D wrote:
On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com
wrote:
diff
On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser
On Tue, Nov 04, 2014 at 02:30:14AM -0800, Daniel Vetter wrote:
On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
+ flags |= I915_DISPATCH_SECURE;
I've forgotten one: You must have a full ppgtt check here since the
binding for aliasing ppgtt is
On Mon, Nov 03, 2014 at 11:19:40AM -0800, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This is v3 of the series I sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-July/048705.html
Most of the previous commentary still applies. We've fixed the secure
On Thu, Oct 30, 2014 at 04:03:23PM -0700, armin.c.re...@intel.com wrote:
From: Armin Reese armin.c.re...@intel.com
The new 'i915_context_dump' file generates a hex dump of the
entire logical context DRM object. It is useful for
validating the contents of the default context set up by
the
On Thu, Oct 23, 2014 at 08:52:59AM -0700, Volkin, Bradley D wrote:
On Thu, Oct 23, 2014 at 05:31:12AM -0700, Daniel Vetter wrote:
On Wed, Oct 22, 2014 at 09:04:32AM -0700, Volkin, Bradley D wrote:
[snip]
On Tue, Oct 21, 2014 at 08:50:33AM -0700, Daniel Vetter wrote:
On Thu, Oct 16
On Thu, Oct 23, 2014 at 05:31:12AM -0700, Daniel Vetter wrote:
On Wed, Oct 22, 2014 at 09:04:32AM -0700, Volkin, Bradley D wrote:
[snip]
On Tue, Oct 21, 2014 at 08:50:33AM -0700, Daniel Vetter wrote:
On Thu, Oct 16, 2014 at 12:24:42PM -0700, bradley.d.vol...@intel.com
wrote
On Tue, Oct 21, 2014 at 08:26:05AM -0700, Daniel Vetter wrote:
On Wed, Oct 15, 2014 at 02:52:41PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
The size of the batch buffer passed to the kernel is significantly
larger than the size of the batch
[snip]
On Tue, Oct 21, 2014 at 08:50:33AM -0700, Daniel Vetter wrote:
On Thu, Oct 16, 2014 at 12:24:42PM -0700, bradley.d.vol...@intel.com wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1a0611b..1ed5702 100644
---
On Wed, Sep 24, 2014 at 05:50:30AM -0700, Mika Kuoppala wrote:
In null/golden context there are multiple state commands where
the actual state is always zero. For more compact batch representation
add a macro which just emits command and the rest of the state as zero.
Signed-off-by: Mika
I went through and compared this against both the spec (the state commands
listed in 3D-Media-GPGPU chapter 3D Pipeline Stages section) and the other
information I've seen on recommended setup, and as far as I can tell this
looks good. It still might be worth getting another set of eyes on this,
[snip]
On Thu, Sep 18, 2014 at 07:58:30AM -0700, Mika Kuoppala wrote:
@@ -577,7 +596,7 @@ static int do_switch(struct intel_engine_cs *ring,
vma-bind_vma(vma, to-legacy_hw_ctx.rcs_state-cache_level,
GLOBAL_BIND);
}
- if (!to-legacy_hw_ctx.initialized ||
On Fri, Sep 12, 2014 at 11:25:14AM -0700, armin.c.re...@intel.com wrote:
From: Armin Reese armin.c.re...@intel.com
This patch includes the Gen9 batch buffer to generate
a 'golden context' for that product family.
Also:
1) IS_GEN9 macro has been added to drivers/gpu/drm/i915/i915_drv.h
2)
On Fri, Jul 11, 2014 at 08:48:52AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
For a description of this patchset, please check the previous cover letters:
[1], [2] and [3].
The main changes introduced in this v4 are:
- Do not abstract __i915_add_request
On Wed, Jul 09, 2014 at 12:37:08AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the
On Wed, Jul 09, 2014 at 08:30:08AM -0700, Chris Wilson wrote:
On Wed, Jul 09, 2014 at 08:10:47AM -0700, Volkin, Bradley D wrote:
On Wed, Jul 09, 2014 at 12:37:08AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com
wrote:
From: Brad Volkin
On Wed, Jul 09, 2014 at 12:36:38AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:38PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
It provides some useful information about the buffers in
the global command parser batch pool.
v2:
On Thu, Jun 26, 2014 at 08:48:46AM -0700, Jesse Barnes wrote:
The command parser may be present, but not active, so check for PPGTT
before allowing this test to run.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
tests/gem_exec_parse.c | 7 ++-
1 file changed, 6
On Tue, Jun 24, 2014 at 04:45:05AM -0700, Mateo Lozano, Oscar wrote:
Ok, let´s try to extract something positive out of all this.
OPTION A (Ben´s proposal):
I think the only solution for what Chris is asking for is to implement this
as 1
context per engine, as opposed to 1 context
On Mon, Jun 23, 2014 at 05:42:50AM -0700, Mateo Lozano, Oscar wrote:
-Original Message-
From: Volkin, Bradley D
+ reg_state[CTX_RING_HEAD+1] = 0;
+ reg_state[CTX_RING_TAIL] = RING_TAIL(ring-mmio_base);
+ reg_state[CTX_RING_TAIL+1] = 0;
+ reg_state[CTX_RING_BUFFER_START
On Mon, Jun 23, 2014 at 07:35:38AM -0700, Mateo Lozano, Oscar wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Monday, June 23, 2014 2:42 PM
To: Mateo Lozano, Oscar
Cc: Volkin, Bradley D; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel
On Fri, Jun 20, 2014 at 06:25:56AM -0700, Tvrtko Ursulin wrote:
On 06/19/2014 06:35 PM, Volkin, Bradley D wrote:
On Thu, Jun 19, 2014 at 02:48:29AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 06/18/2014 05:36 PM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol
On Fri, Jun 20, 2014 at 08:41:08AM -0700, Tvrtko Ursulin wrote:
On 06/20/2014 04:30 PM, Volkin, Bradley D wrote:
On Fri, Jun 20, 2014 at 06:25:56AM -0700, Tvrtko Ursulin wrote:
On 06/19/2014 06:35 PM, Volkin, Bradley D wrote:
On Thu, Jun 19, 2014 at 02:48:29AM -0700, Tvrtko Ursulin
On Fri, Jun 13, 2014 at 08:37:41AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
Reusing stuff, a penny at a time.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h
On Fri, Jun 13, 2014 at 08:37:43AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
For the moment, just mark the place (we still need to do a lot of
preparation before execlists are ready to start submitting things).
Signed-off-by: Oscar Mateo
On Fri, Jun 13, 2014 at 08:37:46AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
Notice that the BSD invalidate bit is no longer present in GEN8, so
Hmm. As far as I can tell, it is still present for VCS on gen8. As to
whether we need to set it, I don't know.
On Thu, Jun 19, 2014 at 11:31:53AM +0100, Damien Lespiau wrote:
Cc: Bradley Volkin bradley.d.vol...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Thanks for taking care of this Damien.
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
---
include/drm/i915_drm.h | 1 +
On Thu, Jun 19, 2014 at 02:48:29AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 06/18/2014 05:36 PM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command
[snip]
On Mon, Jun 16, 2014 at 08:18:00AM -0700, Mateo Lozano, Oscar wrote:
+struct intel_context *
+i915_gem_context_validate(struct drm_device *dev, struct drm_file *file,
+ struct intel_engine_cs *ring, const u32 ctx_id) {
+ struct intel_context *ctx = NULL;
+
On Fri, Jun 13, 2014 at 08:37:22AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
We are going to start creating a lot of extra ringbuffers soon, so
these functions are handy.
No functional changes.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
On Fri, Jun 13, 2014 at 08:37:28AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
There are a few big differences between context init and fini with the
previous implementation of hardware contexts. One of them is
demonstrated in this patch: we must allocate a
On Fri, Jun 13, 2014 at 08:37:29AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
As we have said a couple of times by now, logical ring contexts have
their own ringbuffers: not only the backing pages, but the whole
management struct.
In a previous version of
On Fri, Jun 13, 2014 at 08:37:30AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
For the most part, logical ring context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke
On Fri, Jun 13, 2014 at 08:37:33AM -0700, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside
On Thu, Jun 12, 2014 at 06:36:04PM +0100, Chris Wilson wrote:
On Thu, Jun 12, 2014 at 10:10:58AM -0700, Volkin, Bradley D wrote:
On Thu, Jun 12, 2014 at 03:13:14PM +0100, Chris Wilson wrote:
+ /* Check if a second thread completed the prefaulting for us */
+ if (obj-fault_mappable
On Thu, Jun 12, 2014 at 03:13:14PM +0100, Chris Wilson wrote:
remap_pfn_range() has a nasty surprise if you try to handle two faults
from the same vma concurrently: that is the second thread hits a BUG()
to assert that the range is clear. As we hold our struct_mutex whilst
manipulating the
On Tue, Jun 10, 2014 at 04:14:40AM -0700, Chris Wilson wrote:
Inserting additional PTEs has no side-effect for us as the pfn are fixed
for the entire time the object is resident in the global GTT. The
downside is that we pay the entire cost of faulting the object upon the
first hit, for which
On Tue, Jun 10, 2014 at 04:14:41AM -0700, Chris Wilson wrote:
On an Ivybridge i7-3720qm with 1600MHz DDR3, with 32 fences,
Upload rate for 2 linear surfaces: 8134MiB/s - 8154MiB/s
Upload rate for 2 tiled surfaces: 8625MiB/s - 8632MiB/s
Upload rate for 4 linear surfaces: 8127MiB/s -
On Wed, May 28, 2014 at 03:02:24PM -0700, Jesse Barnes wrote:
Need testing and possibly disabling on earlier steppings, but looks ok
here on my B3.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1
On Wed, May 28, 2014 at 02:29:34PM -0700, Daniel Vetter wrote:
Jesse reportedly has a patch somewhere to (finally!) enable ppgtt on
vlv. Would we still need any part of this with ppgtt support on vlv?
-Daniel
Of course, as soon as I accept that it'll never happen... :)
Off the top of my head,
On Wed, May 21, 2014 at 07:02:56AM -0700, Mika Kuoppala wrote:
+ if (ring-id == RCS !to-is_initialized from == NULL) {
+ ret = i915_gem_render_state_init(ring);
+ if (ret)
+ DRM_ERROR(init render state: %d\n, ret);
+ }
Apologies if this
On Mon, May 19, 2014 at 09:12:26AM -0700, Mateo Lozano, Oscar wrote:
BTW: do you want me to kill private_default_ctx as well? It doesn´t look very
useful...
Isn't private_default_ctx the one that's actually used when userspace
specifies DEFAULT_CONTEXT_ID?
Brad
On Fri, May 09, 2014 at 05:08:32AM -0700, oscar.ma...@intel.com wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
for_each_ring() iterates over all rings supported by the hardware, not
just those which have been initialized as in for_each_active_ring()
I think we should give this a new
On Mon, May 19, 2014 at 09:33:37AM -0700, Mateo Lozano, Oscar wrote:
-Original Message-
From: Volkin, Bradley D
Sent: Monday, May 19, 2014 5:24 PM
To: Mateo Lozano, Oscar
Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 06/50] drm/i915:
s
On Mon, May 19, 2014 at 09:49:31AM -0700, Mateo Lozano, Oscar wrote:
-Original Message-
From: Volkin, Bradley D
Sent: Monday, May 19, 2014 5:41 PM
To: Mateo Lozano, Oscar
Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 06/50] drm/i915:
s
, and clean up comments based on
suggestions by Bradley.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Tvrtko Ursulin tvrtko.ursu...@linux.intel.com
Cc: Gong, Zhipeng zhipeng.g...@intel.com
Cc: Akash Goel akash.g...@intel.com
Cc: Volkin, Bradley D bradley.d.vol...@intel.com
Reviewed
On Fri, May 16, 2014 at 12:53:30PM -0700, Jesse Barnes wrote:
On Fri, 16 May 2014 12:34:08 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
On Fri, 16 May 2014 20:20:50 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
Yes, X only sets the secure bit when it pokes the display
On Sat, May 10, 2014 at 06:42:32AM -0700, Siluvery, Arun wrote:
On 09/05/2014 22:18, Volkin, Bradley D wrote:
On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com
wrote:
+ if (ret)
+ return ret;
+
+ if (!i915_gem_obj_bound(obj, vm)) {
+ ret
On Mon, May 12, 2014 at 09:24:06AM -0700, Daniel Vetter wrote:
On Thu, May 08, 2014 at 09:02:18AM -0700, Volkin, Bradley D wrote:
On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
On Thu, May 08, 2014 at 02
On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds support to have gem objects of variable size.
The size of the gem object obj-size is always constant and this fact
is tightly coupled in the driver;
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip]
- BUG_ON(!validate_cmds_sorted(ring));
+ BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
On Thu, May 08, 2014 at 06:42:16AM -0700, Tvrtko Ursulin wrote:
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT
On Thu, May 08, 2014 at 06:15:44AM -0700, Lespiau, Damien wrote:
On Thu, May 08, 2014 at 02:05:07PM +0100, Damien Lespiau wrote:
On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
+/*
+ * Different command ranges
On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip
On Thu, May 08, 2014 at 08:50:40AM -0700, Tvrtko Ursulin wrote:
On 05/08/2014 04:27 PM, Volkin, Bradley D wrote:
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
Hi Brad,
On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
[snip]
- BUG_ON(!validate_cmds_sorted
Could someone help to review this patch please? It provides a nice
improvement to the command parser's performance, so I'd like to get
this one in.
Thanks,
Brad
On Mon, Apr 28, 2014 at 08:22:08AM -0700, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol...@intel.com
For clients
On Mon, May 05, 2014 at 01:07:32AM -0700, Chris Wilson wrote:
A few improvements to the fallback method for waiting upon ring space:
1. Fix the start/end wait tracepoints to always be paired.
2. Increase responsiveness of checking
3. Mark the process as waiting upon io
4. Check for signal
On Mon, May 05, 2014 at 01:07:33AM -0700, Chris Wilson wrote:
During the review of
commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Mon Jan 27 22:43:07 2014 +
drm/i915: Prevent recursion by retiring requests when the ring is
On Mon, Apr 28, 2014 at 08:22:08AM -0700, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol...@intel.com
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT system performance
drops as much as ~20% on some tests. Most
On Mon, Apr 28, 2014 at 08:42:56AM -0700, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
For clients that submit large batch buffers the command parser has
a substantial impact on performance.
On Mon, Apr 28, 2014 at 08:53:30AM -0700, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
For clients that submit large batch buffers the command parser has
a substantial impact on performance.
On Fri, Apr 18, 2014 at 02:04:27PM -0700, Rodrigo Vivi wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
I don't have any insight on what parts can do what. The docs do seem to
suggest WT caching works in at least the same manner as it doesn't on
Haswell.
As Ben previously mentioned,
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Fri, Apr 18, 2014 at 02:04:28PM -0700, Rodrigo Vivi wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The same register exists for querying and programming eDRAM AKA eLLC. So
we can simply use it. For now, use all the same defaults
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Fri, Apr 18, 2014 at 02:04:29PM -0700, Rodrigo Vivi wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
It seems we need this at least for the current platforms we have, but
probably not later. In any event, it should cause too much
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Thu, Apr 24, 2014 at 10:07:32AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This adds a small benchmark for the new userptr functionality.
Apart from basic surface creation and destruction, also tested is
[snip]
On Wed, Apr 23, 2014 at 06:28:54AM -0700, Tvrtko Ursulin wrote:
On 04/18/2014 12:18 AM, Volkin, Bradley D wrote:
On Wed, Mar 19, 2014 at 04:13:06AM -0700, Tvrtko Ursulin wrote:
+static void **handle_ptr_map;
+static unsigned int num_handle_ptr_map;
I'd prefer that we explicitly
On Wed, Apr 23, 2014 at 06:33:40AM -0700, Tvrtko Ursulin wrote:
On 04/18/2014 06:10 PM, Volkin, Bradley D wrote:
On Wed, Mar 19, 2014 at 04:13:04AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A set of userptr test cases to support the new feature
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Wed, Apr 23, 2014 at 08:07:55AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Makes for a little bit less code duplication, especially since
it will be used from more callers in the future.
Signed-off-by:
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Wed, Apr 23, 2014 at 09:03:23AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
They build fine so give them some exposure.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
Android.mk
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Wed, Apr 23, 2014 at 05:38:34PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
No need for the old test case once the new one was added.
v2:
* Just rebase for lib/ reorganization.
Signed-off-by:
On Wed, Apr 23, 2014 at 05:38:35PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This adds a small benchmark for the new userptr functionality.
Apart from basic surface creation and destruction, also tested is the
impact of having userptr surfaces in the
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Wed, Apr 23, 2014 at 05:38:33PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A set of userptr test cases to support the new feature.
For the eviction and swapping stress testing I have extracted
some
On Wed, Apr 09, 2014 at 09:47:57AM -0700, Daniel Vetter wrote:
On Wed, Apr 09, 2014 at 08:12:28AM -0700, Volkin, Bradley D wrote:
On Tue, Apr 08, 2014 at 11:20:30PM -0700, Chris Wilson wrote:
On Tue, Apr 08, 2014 at 02:22:16PM -0700, bradley.d.vol...@intel.com
wrote:
From: Brad
On Wed, Mar 19, 2014 at 04:13:04AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A set of userptr test cases to support the new feature.
For the eviction and swapping stress testing I have extracted
some common behaviour from gem_evict_everything and made both
to fix up the kernel thread's current-mm for use with
copy_user().
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Tvrtko Ursulin tvrtko.ursu...@linux.intel.com
Cc: Gong, Zhipeng zhipeng.g...@intel.com
Cc: Akash Goel akash.g...@intel.com
Cc: Volkin, Bradley D bradley.d.vol
Hi Chris, just want to bring this one back to your attention while
I'm going through the rest of the series.
Thanks,
Brad
On Fri, Mar 28, 2014 at 03:58:25PM -0700, Volkin, Bradley D wrote:
On Mon, Mar 17, 2014 at 05:21:55AM -0700, Chris Wilson wrote:
A common issue we have is that retiring
On Wed, Mar 19, 2014 at 04:13:06AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This adds a small benchmark for the new userptr functionality.
Apart from basic surface creation and destruction, also tested is the
impact of having userptr surfaces in the
On Wed, Mar 19, 2014 at 04:13:05AM -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
No need for the old test case once the new one was added.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
---
On Tue, Apr 08, 2014 at 11:20:30PM -0700, Chris Wilson wrote:
On Tue, Apr 08, 2014 at 02:22:16PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
The command parser in newer kernels will reject it and setting this
bit is not required for the actual
Hi Daniel, we've merged the kernel change for this but not the test. I'm
assuming we still want the test case.
Brad
On Thu, Mar 27, 2014 at 11:44:45AM -0700, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
On Mon, Mar 17, 2014 at 05:21:55AM -0700, Chris Wilson wrote:
A common issue we have is that retiring requests causes recursion
through GTT manipulation or page table manipulation which we can only
handle at very specific points. However, to maintain internal
consistency (enforced through our
[snip]
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
an issue with the test or the checker:
https://bugs.freedesktop.org/show_bug.cgi?id=76670
For this one, the parser rejects an
On Thu, Mar 27, 2014 at 01:16:26PM -0700, Daniel Vetter wrote:
On Thu, Mar 27, 2014 at 4:57 PM, Volkin, Bradley D
bradley.d.vol...@intel.com wrote:
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
On Thu, Mar 27, 2014 at 02:47:03PM -0700, Kenneth Graunke wrote:
Does any code actually rely on the tables being sorted?
Not today. The idea was to make it easier to move to an algorithm that does
in the future. For example, I thought binary search might be an easy win.
I didn't see any
On Thu, Mar 27, 2014 at 02:58:01PM -0700, Kenneth Graunke wrote:
On 03/27/2014 11:43 AM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
There is some thought that the data from the performance counters enabled
via OACONTROL should only be available to the
On Tue, Mar 25, 2014 at 11:21:23PM -0700, Daniel Vetter wrote:
On Tue, Mar 25, 2014 at 10:52:03PM -0700, Kenneth Graunke wrote:
Mesa needs to be able to write OACONTROL in order to expose the
Observability Architecture's performance counters via OpenGL.
Signed-off-by: Kenneth Graunke
On Wed, Mar 26, 2014 at 10:37:44AM -0700, Kenneth Graunke wrote:
On 03/26/2014 09:38 AM, Daniel Vetter wrote:
On Wed, Mar 26, 2014 at 09:03:58AM -0700, Volkin, Bradley D wrote:
On Tue, Mar 25, 2014 at 11:21:23PM -0700, Daniel Vetter wrote:
On Tue, Mar 25, 2014 at 10:52:03PM -0700, Kenneth
On Tue, Mar 25, 2014 at 06:15:36AM -0700, Daniel Vetter wrote:
On Thu, Mar 20, 2014 at 04:43:05PM +0200, Jani Nikula wrote:
Hi Bradley -
Apologies for my procrastination with the review; I don't easily recall
as tedious a review as the command and register tables. And I sure have
On Tue, Mar 25, 2014 at 06:17:55AM -0700, Daniel Vetter wrote:
On Thu, Jan 30, 2014 at 11:46:15AM +, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 10:10:47PM +, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:58:29PM -0800, bradley.d.vol...@intel.com
wrote:
From: Brad Volkin
Thanks for fixing this Damien.
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Tue, Mar 18, 2014 at 05:43:08PM +, Damien Lespiau wrote:
When compiling on 32bits, I have the following warning:
drivers/gpu/drm/i915/i915_cmd_parser.c:405:4: warning: format ‘%ld’
expects argument of
On Tue, Mar 11, 2014 at 05:41:06AM -0700, Jani Nikula wrote:
Hi Bradley -
I've now rather meticulously reviewed what *is* in the command and
register tables, and didn't spot any obvious errors.
Thanks Jani! I know it's a huge pain, so I appreciate you taking the
time for it.
There is
Reviewed-by: Brad Volkin bradley.d.vol...@intel.com
On Fri, Mar 07, 2014 at 12:30:36AM -0800, Chris Wilson wrote:
We used to lock individual pages inside the buffer object and so needed
to update the page flags every time. However, we now pin the pages into
the object for the duration of the
On Thu, Mar 06, 2014 at 05:17:59AM -0800, Jani Nikula wrote:
On Tue, 18 Feb 2014, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the
On Thu, Mar 06, 2014 at 01:58:09PM -0800, Daniel Vetter wrote:
On Thu, Mar 06, 2014 at 01:32:48PM -0800, Volkin, Bradley D wrote:
On Thu, Mar 06, 2014 at 05:17:59AM -0800, Jani Nikula wrote:
On Tue, 18 Feb 2014, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol
On Wed, Mar 05, 2014 at 09:14:38AM -0800, Daniel Vetter wrote:
On Wed, Mar 05, 2014 at 08:59:56AM -0800, Volkin, Bradley D wrote:
On Wed, Mar 05, 2014 at 02:46:35AM -0800, Daniel Vetter wrote:
On Tue, Feb 18, 2014 at 10:15:44AM -0800, bradley.d.vol...@intel.com
wrote:
From: Brad
Daniel, Jani,
I think I managed to send this while you were both out and I'm sure it got
buried. Can you take a look? I think this rev addresses all of the current
comments.
Thanks,
Brad
On Tue, Feb 18, 2014 at 10:15:44AM -0800, Volkin, Bradley D wrote:
From: Brad Volkin bradley.d.vol
On Fri, Feb 07, 2014 at 06:45:48AM -0800, Daniel Vetter wrote:
On Fri, Feb 07, 2014 at 03:58:46PM +0200, Jani Nikula wrote:
On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
+static int valid_reg(const u32 *table, int count, u32 addr)
+{
+ if (table count != 0) {
+ int
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