On 21/09/2024 14:00, Winkler, Tomas wrote:
On Thu, Sep 19, 2024 at 09:54:24AM +, Winkler, Tomas wrote:
On Mon, Sep 16, 2024 at 04:49:17PM +0300, Alexander Usyskin wrote:
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rig
Hi Dave, Sima,
It is late in the cycle and luckily the fix in this weeks PR is just
something to satisfy static analyzers, nothing that can happen in reality,
so pulling it is even optional.
Regards,
Tvrtko
drm-intel-fixes-2024-09-12:
- Prevent a possible int overflow in wq offsets [guc] (Nik
Hi Dave, Sima,
Some fixes for the weekly cycle:
Avoid pointless attempts to reload GSC, fix for VBIOS/GOP LUT takeover on
ILK and SNB, eliminate regressions by limitting Fast Wake sync pulse
workaround to Dell Precision 5490 with AUO panels only and some clang
build fixes.
Regards,
Tvrtko
drm-
On 04/09/2024 15:34, Jani Nikula wrote:
On Wed, 04 Sep 2024, Andi Shyti wrote:
Hi Sima,
On Tue, Aug 27, 2024 at 07:05:05PM +0200, Daniel Vetter wrote:
On Mon, Aug 19, 2024 at 01:31:40PM +0200, Andi Shyti wrote:
The i915 driver generates sysfs entries for each engine of the
GPU in /sys/clas
On 26/08/2024 11:45, Nikita Zhandarovich wrote:
Hi,
On 7/25/24 08:59, Nikita Zhandarovich wrote:
It may be possible for the sum of the values derived from
i915_ggtt_offset() and __get_parent_scratch_offset()/
i915_ggtt_offset() to go over the u32 limit before being assigned
to wq offsets of u
Hi Dave, Sima,
A small bunch of fixes for the weekly cycle:
Fix for Meteorlake dual PPS, vma offset calculation and tidy when partial
mapping and unbreaking of eviction handling on DG2 small bar systems.
Regards,
Tvrtko
drm-intel-fixes-2024-08-08:
- correct dual pps handling for MTL_PCH+ [d
On 07/08/2024 12:40, Jani Nikula wrote:
On Wed, 07 Aug 2024, Tvrtko Ursulin wrote:
On 06/08/2024 14:38, Jani Nikula wrote:
With the previous cleanups, the last remaining user of __i915_printk()
is i915_probe_error(). Switch that to use drm_dbg() and drm_err()
instead, dropping the request
Hi,
On 05/08/2024 19:48, Kees Cook wrote:
This seems like some kind of pre-existing issue in the igt test, reachable
via eb_copy_relocations(). The only warning in kvmalloc_node_noprof() is:
/* Don't even allow crazy sizes */
if (unlikely(size > INT_MAX)) {
On 06/08/2024 14:38, Jani Nikula wrote:
With the previous cleanups, the last remaining user of __i915_printk()
is i915_probe_error(). Switch that to use drm_dbg() and drm_err()
instead, dropping the request to report bugs in the few remaining
specific cases.
Aren't those few cases legitimate
f IS_ENABLED(CONFIG_DRM_I915_DEBUG)
int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
On 06/08/2024 14:38, Jani Nikula wrote:
__i915_printk() does nothing for notice/info levels. Just use the
regular drm_notice() and drm_info() calls.
"does nothing"? You mean does nothing _special_?
The patch itself looks okay.
Regards,
Tvrtko
Signed-off-by: Jani Nikula
---
drivers/gpu
On 29/07/2024 15:59, Cavitt, Jonathan wrote:
-Original Message-
From: Tvrtko Ursulin
Sent: Monday, July 29, 2024 1:21 AM
To: Dan Carpenter
Cc: Cavitt, Jonathan ; intel-gfx@lists.freedesktop.org;
Gupta, saurabhg ; chris.p.wil...@linux.intel.com
Subject: Re: [PATCH] drm/i915: Allow
On 26/07/2024 18:00, Dan Carpenter wrote:
On Fri, Jul 26, 2024 at 09:17:20AM +0100, Tvrtko Ursulin wrote:
On 25/07/2024 16:58, Dan Carpenter wrote:
On Thu, Jul 25, 2024 at 08:48:35AM +0100, Tvrtko Ursulin wrote:
Hi,
On 12/07/2024 22:41, Jonathan Cavitt wrote:
Prevent a NULL pointer
On 25/07/2024 16:58, Dan Carpenter wrote:
On Thu, Jul 25, 2024 at 08:48:35AM +0100, Tvrtko Ursulin wrote:
Hi,
On 12/07/2024 22:41, Jonathan Cavitt wrote:
Prevent a NULL pointer access in intel_memory_regions_hw_probe.
For future reference please include some impact assessment in patches
Hi,
On 12/07/2024 22:41, Jonathan Cavitt wrote:
Prevent a NULL pointer access in intel_memory_regions_hw_probe.
For future reference please include some impact assessment in patches
tagged as fixes. Makes maintainers job, and even anyone's who tries to
backport stuff to stable at some futu
Hi Dave, Sima,
Two fixes for the merge window - turning off preemption on Gen8 since it
apparently just doesn't work reliably enough and a fix for potential NULL
pointer dereference when stolen memory probing failed.
Regards,
Tvrtko
drm-intel-next-fixes-2024-07-25:
- Do not consider preemptio
On 23/07/2024 16:30, Lucas De Marchi wrote:
On Tue, Jul 23, 2024 at 09:03:25AM GMT, Tvrtko Ursulin wrote:
On 22/07/2024 22:06, Lucas De Marchi wrote:
Instead of calling perf_pmu_unregister() when unbinding, defer that to
the destruction of i915 object. Since perf itself holds a reference in
On 22/07/2024 22:06, Lucas De Marchi wrote:
Instead of calling perf_pmu_unregister() when unbinding, defer that to
the destruction of i915 object. Since perf itself holds a reference in
the event, this only happens when all events are gone, which guarantees
i915 is not unregistering the pmu wit
On 22/07/2024 22:06, Lucas De Marchi wrote:
There's no need to free the resources during unbind. Since perf events
may still access them due to open events, it's safer to free them when
dropping the last i915 reference.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pmu.c | 21
ommit 05488673a4d41383f9dd537f298e525e6b00fb93
Author: Tvrtko Ursulin
AuthorDate: Wed Oct 16 10:38:02 2019 +0100
Commit: Tvrtko Ursulin
CommitDate: Thu Oct 17 10:50:47 2019 +0100
drm/i915/pmu: Support multiple GPUs
Added IS_DGFX:
commit dc90fe3fd219c7693617ba09a9467e4aadc2e039
Author: José Roberto de
Hi Dave, Sima,
One display fix for the merge window relating to DisplayPort LTTPR. It
fixes at least Dell UD22 dock when used on Intel N100 systems.
Regards,
Tvrtko
drm-intel-next-fixes-2024-07-18:
- Reset intel_dp->link_trained before retraining the link [dp] (Imre Deak)
- Don't switch the L
27; error and make can_preempt()
function param as const to resolve error: passing argument 1 of
‘can_preempt’ discards ‘const’ qualifier from the pointer target type.
v2: Simplify can_preemt() function (Tvrtko Ursulin)
Yeah sorry for that yesterday when I thought gen8 emit bb was dead code,
some
On 09/07/2024 15:02, Tvrtko Ursulin wrote:
On 09/07/2024 13:53, Nitin Gote wrote:
We're seeing a GPU HANG issue on a CHV platform, which was caused by
bac24f59f454 ("drm/i915/execlists: Enable coarse preemption boundaries
for gen8").
Gen8 platform has only timeslice and do
On 09/07/2024 13:53, Nitin Gote wrote:
We're seeing a GPU HANG issue on a CHV platform, which was caused by
bac24f59f454 ("drm/i915/execlists: Enable coarse preemption boundaries for
gen8").
Gen8 platform has only timeslice and doesn't support a preemption mechanism
as engines do not have a p
Hi Dave, Sima,
The final pull for 6.11 is quite small and only contains a handful of
fixes in areas such as stolen memory probing on ATS-M, GuC priority
handling, out of memory reporting noise downgrade and fence register
hanlding race condition reported by CI.
Regards,
Tvrtko
drm-intel-gt-ne
- depends on !PREEMPT_RT
select INTEL_GTT if X86
select INTERVAL_TREE
# we need shmfs for the swappable backing store, and in particular
Cool!
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
Q_TRACE(request, "\n");
- GEM_BUG_ON(!irqs_disabled());
lockdep_assert_held(&engine->sched_engine->lock);
/*
Maarten can you r-b since it seems this one originated from your
testing? Otherwise:
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
+#define NOTRACE
+#endif
+
#include
#include
#include
If tracing experts said this is the way then it is fine by me.
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
On 18/06/2024 13:54, Sebastian Andrzej Siewior wrote:
On 2024-06-18 10:00:09 [+0100], Tvrtko Ursulin wrote:
I did a re-test but am not 100% certain yet. CI looks frustratingly noisy at
the moment.
igt@debugfs_test@read_all_entries appears to be a fluke which is not new.
But igt
On 17/06/2024 11:07, Sebastian Andrzej Siewior wrote:
On 2024-06-14 13:19:25 [+0100], Tvrtko Ursulin wrote:
So the question is why do you need to know if the context is atomic?
The only impact is avoiding disabling preemption. Is it that important
to avoid it?
If so would cant_migrate() work
On 14/06/2024 12:05, Sebastian Andrzej Siewior wrote:
On 2024-06-14 09:32:07 [+0100], Tvrtko Ursulin wrote:
I think this could be okay-ish in principle, but the commit text is not
entirely accurate because there is no direct coupling between the wait
helpers and the uncore lock. They can be
On 13/06/2024 11:20, Sebastian Andrzej Siewior wrote:
The !in_atomic() check in _wait_for_atomic() triggers on PREEMPT_RT
because the uncore::lock is a spinlock_t and does not disable
preemption or interrupts.
Changing the uncore:lock to a raw_spinlock_t doubles the worst case
latency on an ot
the timeout used.
A couple tiny cleanups here and there and finally one back-merge which
was required to land some display code base refactoring.
Regards,
Tvrtko
drm-intel-gt-next-2024-06-12:
UAPI Changes:
- Support replaying GPU hangs with captured context image (Tvrtko Ursulin)
Driver
On 10/06/2024 10:24, Nirmoy Das wrote:
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section in the fw_domains_show()
debugfs interface.
Signe
Hi Sebastian,
On 05/06/2024 11:01, Sebastian Andrzej Siewior wrote:
On 2024-04-05 16:18:18 [+0200], To intel-gfx@lists.freedesktop.org wrote:
Hi,
The following patches are from the PREEMPT_RT queue. It is mostly about
disabling interrupts/preemption which leads to problems. Unfortunately
…
Hi Andi,
On 10/06/2024 13:10, Andi Shyti wrote:
Hi Tvrtko,
On Mon, Jun 10, 2024 at 12:42:31PM +0100, Tvrtko Ursulin wrote:
On 03/06/2024 17:20, Niemiec, Krzysztof wrote:
The test is trying to push the heartbeat frequency to the limit, which
might sometimes fail. Such a failure does not
On 03/06/2024 17:20, Niemiec, Krzysztof wrote:
The test is trying to push the heartbeat frequency to the limit, which
might sometimes fail. Such a failure does not provide valuable
information, because it does not indicate that there is something
necessarily wrong with either the driver or the
On 23/05/2024 13:24, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 01:07:24PM +0100, Tvrtko Ursulin wrote:
On 23/05/2024 12:19, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
On 22/05/2024 16:29, Vidya Srinivas wrote:
In some scenarios, the DPT object
On 23/05/2024 12:19, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
On 22/05/2024 16:29, Vidya Srinivas wrote:
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list.
On 22/05/2024 16:29, Vidya Srinivas wrote:
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Suggested-by: Ville Syrjala
Cc: sta..
From: Tvrtko Ursulin
Kernel test robot reports i915 can hit a warn in kvmalloc_node which has
a purpose of dissalowing crazy size kernel allocations. This was added in
7661809d493b ("mm: don't allow oversized kvmalloc() calls"):
/* Don't even allow crazy sizes */
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which prevent replicating all hangs, one step further is being
able to replay against a real GPU.
This is almost
From: Tvrtko Ursulin
To enable adding override of the default engine context image let us start
shadowing the per engine state in the context.
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: Carlos Santa
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin
To enable adding override of the default engine context image let us start
shadowing the per engine state in the context.
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: Carlos Santa
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which prevent replicating all hangs, one step further is being
able to replay against a real GPU.
This is almost
: Lucas De Marchi
Also Cc'ing maintainers
Thanks,
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d6327dc12cb1..fbf7371a0bb0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10
On 18/04/2024 10:49, Jani Nikula wrote:
On Wed, 17 Apr 2024, Lucas De Marchi wrote:
On Mon, Apr 08, 2024 at 03:54:44PM GMT, Jani Nikula wrote:
The raw register reads/writes are there as micro-optimizations to avoid
multiple pointer indirections on uncore->regs. Presumably this is useful
when
os of the 'dev_priv' name keep sneaking it
in.
Signed-off-by: Andi Shyti
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 +++---
drivers/gpu
On 20/03/2024 15:06, Andi Shyti wrote:
Ping! Any thoughts here?
I only casually observed the discussion after I saw Matt suggested
further simplifications. As I understood it, you will bring back the
uabi engine games when adding the dynamic behaviour and that is fine by me.
Regards,
Tvr
On 11/03/2024 19:27, Lucas De Marchi wrote:
On Mon, Mar 11, 2024 at 05:43:00PM +, Tvrtko Ursulin wrote:
On 06/03/2024 19:36, Lucas De Marchi wrote:
Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of
On 06/03/2024 19:36, Lucas De Marchi wrote:
Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of the
code for those platforms is actually used by subsequent ones, so it's
not a huge amount of code being removed.
From: Tvrtko Ursulin
I will lose access to my @.*intel.com e-mail addresses soon so let me
adjust the maintainers entry and update the mailmap too.
While at it consolidate a few other of my old emails to point to the
main one.
Signed-off-by: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: Dave Airlie
.
Regards,
Tvrtko
drm-intel-gt-next-2024-02-28:
Driver Changes:
Fixes:
- Add some boring kerneldoc (Tvrtko Ursulin)
- Check before removing mm notifier (Nirmoy
The following changes since commit eb927f01dfb6309c8a184593c2c0618c4000c481:
drm/i915/gt: Restart the heartbeat timer when forcing a
On 27/02/2024 09:26, Nirmoy Das wrote:
Hi Tvrtko,
On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to wo
/sushmave/mesa/-/commits/compute_hint
v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
Also, use flag bits in intel_context as it allows finer control for
toggling per engine if needed (Tvrtko).
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Sushma Venkatesh Reddy
Signed-off-by: Vinay Belgaumkar
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to worry about
obj->mm.lock, v7.")
Cc: # v5.13+
?
Regards,
Tvrtko
On 2/19/2024 1:50 PM, Nirmoy Das wrote:
E
On 22/02/2024 21:07, Rodrigo Vivi wrote:
On Wed, Feb 21, 2024 at 02:22:45PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which
On 26/02/2024 08:47, Tvrtko Ursulin wrote:
On 23/02/2024 19:25, Rodrigo Vivi wrote:
On Fri, Feb 23, 2024 at 10:31:41AM -0800, Belgaumkar, Vinay wrote:
On 2/23/2024 12:51 AM, Tvrtko Ursulin wrote:
On 22/02/2024 23:31, Belgaumkar, Vinay wrote:
On 2/22/2024 7:32 AM, Tvrtko Ursulin wrote
On 23/02/2024 19:25, Rodrigo Vivi wrote:
On Fri, Feb 23, 2024 at 10:31:41AM -0800, Belgaumkar, Vinay wrote:
On 2/23/2024 12:51 AM, Tvrtko Ursulin wrote:
On 22/02/2024 23:31, Belgaumkar, Vinay wrote:
On 2/22/2024 7:32 AM, Tvrtko Ursulin wrote:
On 21/02/2024 21:28, Rodrigo Vivi wrote
On 22/02/2024 23:31, Belgaumkar, Vinay wrote:
On 2/22/2024 7:32 AM, Tvrtko Ursulin wrote:
On 21/02/2024 21:28, Rodrigo Vivi wrote:
On Wed, Feb 21, 2024 at 09:42:34AM +, Tvrtko Ursulin wrote:
On 21/02/2024 00:14, Vinay Belgaumkar wrote:
Allow user to provide a context hint. When this
On 21/02/2024 21:28, Rodrigo Vivi wrote:
On Wed, Feb 21, 2024 at 09:42:34AM +, Tvrtko Ursulin wrote:
On 21/02/2024 00:14, Vinay Belgaumkar wrote:
Allow user to provide a context hint. When this is set, KMD will
send a hint to GuC which results in special handling for this
context. SLPC
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which prevent replicating all hangs, one step further is being
able to replay against a real GPU.
This is almost
From: Tvrtko Ursulin
Please see 2/2 for explanation and rationale.
v2:
* Extracted shadowing of default state into a leading patch.
Tvrtko Ursulin (2):
drm/i915: Shadow default engine context image in the context
drm/i915: Support replaying GPU hangs with captured context image
drivers
From: Tvrtko Ursulin
To enable adding override of the default engine context image let us start
shadowing the per engine state in the context.
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: Carlos Santa
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2
On 21/02/2024 12:08, Tvrtko Ursulin wrote:
On 21/02/2024 11:19, Andi Shyti wrote:
Hi Tvrtko,
On Wed, Feb 21, 2024 at 08:19:34AM +, Tvrtko Ursulin wrote:
On 21/02/2024 00:14, Andi Shyti wrote:
On Tue, Feb 20, 2024 at 02:48:31PM +, Tvrtko Ursulin wrote:
On 20/02/2024 14:35, Andi
On 21/02/2024 11:19, Andi Shyti wrote:
Hi Tvrtko,
On Wed, Feb 21, 2024 at 08:19:34AM +, Tvrtko Ursulin wrote:
On 21/02/2024 00:14, Andi Shyti wrote:
On Tue, Feb 20, 2024 at 02:48:31PM +, Tvrtko Ursulin wrote:
On 20/02/2024 14:35, Andi Shyti wrote:
Enable only one CCS engine by
On 21/02/2024 00:14, Vinay Belgaumkar wrote:
Allow user to provide a context hint. When this is set, KMD will
send a hint to GuC which results in special handling for this
context. SLPC will ramp the GT frequency aggressively every time
it switches to this context. The down freq threshold will
On 20/02/2024 22:50, Rodrigo Vivi wrote:
On Tue, Feb 13, 2024 at 01:14:34PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which
On 21/02/2024 00:14, Andi Shyti wrote:
Hi Tvrtko,
On Tue, Feb 20, 2024 at 02:48:31PM +, Tvrtko Ursulin wrote:
On 20/02/2024 14:35, Andi Shyti wrote:
Enable only one CCS engine by default with all the compute sices
slices
Thanks!
diff --git a/drivers/gpu/drm/i915/gt
On 20/02/2024 14:35, Andi Shyti wrote:
Enable only one CCS engine by default with all the compute sices
slices
allocated to it.
While generating the list of UABI engines to be exposed to the
user, exclude any additional CCS engines beyond the first
instance.
This change can be tested with
On 20/02/2024 14:20, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Erm *all* CSS engines work together..
Simultaneously, the user will see only 1 CCS rath
On 20/02/2024 10:36, Maxime Ripard wrote:
On Tue, Feb 20, 2024 at 09:16:43AM +, Tvrtko Ursulin wrote:
On 19/02/2024 20:02, Rodrigo Vivi wrote:
On Mon, Feb 19, 2024 at 01:14:23PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Request can be NULL if no guilty request was identified
On 20/02/2024 10:11, Andi Shyti wrote:
Hi Tvrtko,
On Mon, Feb 19, 2024 at 12:51:44PM +, Tvrtko Ursulin wrote:
On 19/02/2024 11:16, Tvrtko Ursulin wrote:
On 15/02/2024 13:59, Andi Shyti wrote:
...
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due
On 19/02/2024 20:02, Rodrigo Vivi wrote:
On Mon, Feb 19, 2024 at 01:14:23PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Request can be NULL if no guilty request was identified so simply use
engine->i915 instead.
Signed-off-by: Tvrtko Ursulin
Fixes: d50892a9554c ("drm/i915
From: Tvrtko Ursulin
Tooling appears very strict so lets pacify it by adding some comments,
even if fields are completely self-explanatory.
Signed-off-by: Tvrtko Ursulin
Fixes: b11236486749 ("drm/i915: Add GuC submission interface version query")
Reported-by: Stephen Rothwell
Cc:
From: Tvrtko Ursulin
Request can be NULL if no guilty request was identified so simply use
engine->i915 instead.
Signed-off-by: Tvrtko Ursulin
Fixes: d50892a9554c ("drm/i915: switch from drm_debug_printer() to device
specific drm_dbg_printer()")
Reported-by: Dan Carpenter
Cc: Ja
On 19/02/2024 11:16, Tvrtko Ursulin wrote:
On 15/02/2024 13:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS
On 15/02/2024 13:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the
actual number. As of now, thi
submission version query which Mesa
wants for implementing Vulkan async compute queues.
Regards,
Tvrtko
drm-intel-gt-next-2024-02-15:
UAPI Changes:
- Add GuC submission interface version query (Tvrtko Ursulin)
Driver Changes:
Fixes/improvements/new stuff:
- Atomically invalidate userptr on mmu
On 13/02/2024 18:03, Umesh Nerlige Ramappa wrote:
Once a user opens an fd for a perf event, if the driver undergoes a
function level reset (FLR), the resources are not cleaned up as
expected. For this discussion FLR is defined as a PCI unbind followed by
a bind. perf_pmu_unregister() would clea
From: Tvrtko Ursulin
When debugging GPU hangs Mesa developers are finding it useful to replay
the captured error state against the simulator. But due various simulator
limitations which prevent replicating all hangs, one step further is being
able to replay against a real GPU.
This is almost
On 08/02/2024 18:13, Erick Archer wrote:
The "struct i915_syncmap" uses a dynamically sized set of trailing
elements. It can use an "u32" array or a "struct i915_syncmap *"
array.
So, use the preferred way in the kernel declaring flexible arrays [1].
Because there are two possibilities for the
On 08/02/2024 17:55, Souza, Jose wrote:
On Thu, 2024-02-08 at 07:19 -0800, José Roberto de Souza wrote:
On Thu, 2024-02-08 at 14:59 +, Tvrtko Ursulin wrote:
On 08/02/2024 14:30, Souza, Jose wrote:
On Thu, 2024-02-08 at 08:25 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new
On 08/02/2024 14:30, Souza, Jose wrote:
On Thu, 2024-02-08 at 08:25 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to check for old firmware versions
with a known bug where using the render and
On 07/02/2024 19:34, John Harrison wrote:
On 2/7/2024 10:49, Tvrtko Ursulin wrote:
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to check for old firmware versions
with a known bug where using the render and compute command streamers
simultaneously can cause GPU hangs due issues in firmware scheduling
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to check for old firmware versions
with a known bug where using the render and compute
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to check for old firmware versions
with a known bug where using the render and compute command streamers
simultaneously can cause GPU hangs due issues in firmware scheduling
Hi,
On 06/02/2024 16:45, Nikita Zhandarovich wrote:
After falling through the switch statement to default case 'repr' is
initialized with NULL, which will lead to incorrect dereference of
'!repr[n]' in the following loop.
Fix it with the help of an additional check for NULL.
Found by Linux V
On 06/02/2024 20:51, Souza, Jose wrote:
On Tue, 2024-02-06 at 12:42 -0800, John Harrison wrote:
On 2/6/2024 08:33, Tvrtko Ursulin wrote:
On 01/02/2024 18:25, Souza, Jose wrote:
On Wed, 2024-01-24 at 08:55 +, Tvrtko Ursulin wrote:
On 24/01/2024 08:19, Joonas Lahtinen wrote:
Add
On 01/02/2024 18:25, Souza, Jose wrote:
On Wed, 2024-01-24 at 08:55 +, Tvrtko Ursulin wrote:
On 24/01/2024 08:19, Joonas Lahtinen wrote:
Add reporting of the GuC submissio/VF interface version via GETPARAM
properties. Mesa intends to use this information to check for old
firmware
stats[id].shared += sz;
else
stats[id].private += sz;
Reviewed-by: Tvrtko Ursulin
Good that you remembered this story, I completely forgot!
Regards,
Tvrtko
/**
Not sure what the local view on static inlines, but fine nevertheless.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
ts(obj)) {
status.shared += obj->size;
} else {
status.private += obj->size;
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
-total-: [KiB|MiB]
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
case he remembers.
Signed-off-by: Joonas Lahtinen
Cc: Kenneth Graunke
Cc: Jose Souza
Cc: Sagar Ghuge
Cc: Paulo Zanoni
Cc: John Harrison
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_getparam.c | 12
include/uapi/drm/i915_drm.h
From: Tvrtko Ursulin
Fix a bug where 1) the end vertical separator element would not be printed
if the progress bar portion was all filled by the progress bar characters
(no trailing spaces), and 2) the numerical overlay would be skipped to.
The bug would also shift the layout of following UI
On 08/01/2024 15:13, Joonas Lahtinen wrote:
Quoting Tvrtko Ursulin (2024-01-05 12:39:31)
On 04/01/2024 21:23, Andi Shyti wrote:
+void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+{
+ mutex_lock(>->ccs.mutex);
+ __intel_gt_apply_ccs_mode(gt);
+ mutex_unlock(>-&
On 04/01/2024 21:23, Andi Shyti wrote:
Hi Tvrtko,
[1]
+ /*
+* Loop over all available slices and assign each a user engine.
+*
+* With 1 engine (ccs0):
+* slice 0, 1, 2, 3: ccs0
+*
+* With 2 engines (ccs0, ccs1):
+* slice 0, 2
On 04/01/2024 14:35, Andi Shyti wrote:
The CCS mode involves assigning CCS engines to slices depending
on the number of slices and the number of engines the user wishes
to set.
In this patch, the default CCS setting is established during the
initial GT settings. It involves assigning only one
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