Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions

2016-09-19 Thread Jani Nikula 
On Mon, 19 Sep 2016, Mika Kahola  wrote:
> On Fri, 2016-09-16 at 16:59 +0300, Jani Nikula wrote:
>> Pre-production hardware is not supported.
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c   |  4 
>>  drivers/gpu/drm/i915/intel_dp_link_training.c |  3 ---
>>  drivers/gpu/drm/i915/intel_guc_loader.c   |  5 ++---
>>  drivers/gpu/drm/i915/intel_lrc.c  |  8 +++-
>>  drivers/gpu/drm/i915/intel_ringbuffer.c   | 21 ++---
>> 
>>  5 files changed, 11 insertions(+), 30 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index acd0c51f74d5..b2a9eb82ac4b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct
>> intel_dp *intel_dp)
>>  struct intel_digital_port *dig_port =
>> dp_to_dig_port(intel_dp);
>>  struct drm_device *dev = dig_port->base.base.dev;
>>  
>> -/* WaDisableHBR2:skl */
>> -if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
>> -return false;
>> -
>>  if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>> IS_BROADWELL(dev) ||
>>  (INTEL_INFO(dev)->gen >= 9))
>>  return true;
>> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> index c438b02184cb..0048b520baf7 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> @@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct
>> intel_dp *intel_dp)
>>   * Intel platforms that support HBR2 also support TPS3. TPS3
>> support is
>>   * also mandatory for downstream devices that support HBR2.
>> However, not
>>   * all sinks follow the spec.
>> - *
>> - * Due to WaDisableHBR2 SKL < B0 is the only exception where
>> TPS3 is
>> - * supported in source but still not enabled.
>>   */
>>  source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
>>  sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 6fd39efb7894..acc1dbdd024e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private
>> *dev_priv)
>>  /* Enable MIA caching. GuC clock gating is disabled. */
>>  I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>>  
>> -/* WaDisableMinuteIaClockGating:skl,bxt */
>> -if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
>> -IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>> +/* WaDisableMinuteIaClockGating:bxt */
>> +if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>>  I915_WRITE(GUC_SHIM_CONTROL,
>> (I915_READ(GUC_SHIM_CONTROL) &
>>    ~GUC_ENABLE_MIA_CLOCK_
>> GATING));
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index 251143361f31..4bfa3c015e25 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct
>> intel_engine_cs *engine)
>>  struct drm_i915_private *dev_priv = engine->i915;
>>  
>>  engine->disable_lite_restore_wa =
>> -(IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
>> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
>> +IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
>>  (engine->id == VCS || engine->id == VCS2);
>>  
>>  engine->ctx_desc_template = GEN8_CTX_VALID;
>> @@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct
>> intel_engine_cs *engine,
>>  {
>>  uint32_t index = wa_ctx_start(wa_ctx, *offset,
>> CACHELINE_DWORDS);
>>  
>> -/*
>> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> -if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
>> -IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
>> +/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
>> */
>> +if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
>>  wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>>  wa_ctx_emit_reg(batch, index,
>> GEN9_SLICE_COMMON_ECO_CHICKEN0);
>>  wa_ctx_emit(batch, index,
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 7a74750076c5..2faf64f9f256 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct
>> intel_engine_cs *engine)
>>  WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>>    GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>>  
>> -/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
>> -if (IS_SKL_REVID(dev_priv, 0,

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions

2016-09-19 Thread Mika Kahola 
On Fri, 2016-09-16 at 16:59 +0300, Jani Nikula wrote:
> Pre-production hardware is not supported.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/intel_dp.c   |  4 
>  drivers/gpu/drm/i915/intel_dp_link_training.c |  3 ---
>  drivers/gpu/drm/i915/intel_guc_loader.c   |  5 ++---
>  drivers/gpu/drm/i915/intel_lrc.c  |  8 +++-
>  drivers/gpu/drm/i915/intel_ringbuffer.c   | 21 ++---
> 
>  5 files changed, 11 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index acd0c51f74d5..b2a9eb82ac4b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct
> intel_dp *intel_dp)
>   struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
>   struct drm_device *dev = dig_port->base.base.dev;
>  
> - /* WaDisableHBR2:skl */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
> - return false;
> -
>   if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
> IS_BROADWELL(dev) ||
>   (INTEL_INFO(dev)->gen >= 9))
>   return true;
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index c438b02184cb..0048b520baf7 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct
> intel_dp *intel_dp)
>    * Intel platforms that support HBR2 also support TPS3. TPS3
> support is
>    * also mandatory for downstream devices that support HBR2.
> However, not
>    * all sinks follow the spec.
> -  *
> -  * Due to WaDisableHBR2 SKL < B0 is the only exception where
> TPS3 is
> -  * supported in source but still not enabled.
>    */
>   source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
>   sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 6fd39efb7894..acc1dbdd024e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private
> *dev_priv)
>   /* Enable MIA caching. GuC clock gating is disabled. */
>   I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>  
> - /* WaDisableMinuteIaClockGating:skl,bxt */
> - if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + /* WaDisableMinuteIaClockGating:bxt */
> + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>   I915_WRITE(GUC_SHIM_CONTROL,
> (I915_READ(GUC_SHIM_CONTROL) &
>     ~GUC_ENABLE_MIA_CLOCK_
> GATING));
>   }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 251143361f31..4bfa3c015e25 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct
> intel_engine_cs *engine)
>   struct drm_i915_private *dev_priv = engine->i915;
>  
>   engine->disable_lite_restore_wa =
> - (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> -  IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
> + IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
>   (engine->id == VCS || engine->id == VCS2);
>  
>   engine->ctx_desc_template = GEN8_CTX_VALID;
> @@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct
> intel_engine_cs *engine,
>  {
>   uint32_t index = wa_ctx_start(wa_ctx, *offset,
> CACHELINE_DWORDS);
>  
> - /*
> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt
> */
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
>   wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>   wa_ctx_emit_reg(batch, index,
> GEN9_SLICE_COMMON_ECO_CHICKEN0);
>   wa_ctx_emit(batch, index,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 7a74750076c5..2faf64f9f256 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
>   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>     GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>  
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> - if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> +

[Intel-gfx] [PATCH 1/5] drm/i915/skl: drop workarounds for A0 and B0 revisions

2016-09-16 Thread Jani Nikula 
Pre-production hardware is not supported.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_dp.c   |  4 
 drivers/gpu/drm/i915/intel_dp_link_training.c |  3 ---
 drivers/gpu/drm/i915/intel_guc_loader.c   |  5 ++---
 drivers/gpu/drm/i915/intel_lrc.c  |  8 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.c   | 21 ++---
 5 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index acd0c51f74d5..b2a9eb82ac4b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp 
*intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
 
-   /* WaDisableHBR2:skl */
-   if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
-   return false;
-
if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
(INTEL_INFO(dev)->gen >= 9))
return true;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index c438b02184cb..0048b520baf7 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct intel_dp 
*intel_dp)
 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 * also mandatory for downstream devices that support HBR2. However, not
 * all sinks follow the spec.
-*
-* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
-* supported in source but still not enabled.
 */
source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6fd39efb7894..acc1dbdd024e 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
/* Enable MIA caching. GuC clock gating is disabled. */
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
-   /* WaDisableMinuteIaClockGating:skl,bxt */
-   if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-   IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+   /* WaDisableMinuteIaClockGating:bxt */
+   if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
  ~GUC_ENABLE_MIA_CLOCK_GATING));
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 251143361f31..4bfa3c015e25 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
 
engine->disable_lite_restore_wa =
-   (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
-IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
+   IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
(engine->id == VCS || engine->id == VCS2);
 
engine->ctx_desc_template = GEN8_CTX_VALID;
@@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs 
*engine,
 {
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-   if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
-   IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
+   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+   if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7a74750076c5..2faf64f9f256 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
-   /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
-   if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
-   IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+   /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
+   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
  GEN9_DG_MIRROR_FIX_ENABLE);
 
-   /*