Re: [Intel-gfx] [PATCH 19/19] drm/i915: Make IS_GEN macros only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:52PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1416 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

Do note though, that this is a *very* large patch, and I suspect that
you'll have trouble getting it merged...

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c|  4 +-
>  drivers/gpu/drm/i915/i915_drv.c|  6 +--
>  drivers/gpu/drm/i915/i915_drv.h| 16 +++---
>  drivers/gpu/drm/i915/i915_gem.c|  8 +--
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c  |  9 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++--
>  drivers/gpu/drm/i915/i915_gem_stolen.c |  4 +-
>  drivers/gpu/drm/i915/i915_gem_tiling.c |  4 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c  | 10 ++--
>  drivers/gpu/drm/i915/i915_irq.c|  4 +-
>  drivers/gpu/drm/i915/i915_suspend.c|  4 +-
>  drivers/gpu/drm/i915/intel_crt.c   |  6 +--
>  drivers/gpu/drm/i915/intel_display.c   | 41 ---
>  drivers/gpu/drm/i915/intel_dp.c| 20 +++
>  drivers/gpu/drm/i915/intel_drv.h   |  2 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +--
>  drivers/gpu/drm/i915/intel_guc_loader.c|  3 +-
>  drivers/gpu/drm/i915/intel_lvds.c  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c| 83 
> +++---
>  drivers/gpu/drm/i915/intel_sprite.c|  4 +-
>  21 files changed, 126 insertions(+), 124 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 20689f1cd719..3a42df3a29e5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const 
> uint16_t wm[8])
>   else if (IS_VALLEYVIEW(dev_priv))
>   num_levels = 1;
>   else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>   drm_modeset_lock_all(dev);
>  
> @@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, 
> const char __user *ubuf,
>   else if (IS_VALLEYVIEW(dev_priv))
>   num_levels = 1;
>   else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>   if (len >= sizeof(tmp))
>   return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5e7b6a1cb2c8..c1956855feb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
>   if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_IBX;
>   DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> - WARN_ON(!IS_GEN5(dev));
> + WARN_ON(!IS_GEN5(dev_priv));
>   } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_CPT;
>   DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> @@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
>   int mmio_bar;
>   int mmio_size;
>  
> - mmio_bar = IS_GEN2(dev) ? 1 : 0;
> + mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
>   /*
>* Before gen4, the registers and the GTT are behind different BARs.
>* However, from gen4 onwards, the registers and the GTT are shared
> @@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
> *dev_priv)
>   pci_set_master(pdev);
>  
>   /* overlay on gen2 is broken and can't address above 1G */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
>   ret = dma_set_coherent_mask(>dev, DMA_BIT_MASK(30));
>   if (ret) {
>   DRM_ERROR("failed to set DMA mask\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f38b9755763..a05665af31be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
>   * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
>   * chips, etc.).
>   */
> -#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
> -#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
> -#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
> -#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
> -#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
> -#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & 

[Intel-gfx] [PATCH 19/19] drm/i915: Make IS_GEN macros only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1416 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  4 +-
 drivers/gpu/drm/i915/i915_drv.c|  6 +--
 drivers/gpu/drm/i915/i915_drv.h| 16 +++---
 drivers/gpu/drm/i915/i915_gem.c|  8 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 +-
 drivers/gpu/drm/i915/i915_gem_fence.c  |  9 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++--
 drivers/gpu/drm/i915/i915_gem_stolen.c |  4 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c |  4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c  | 10 ++--
 drivers/gpu/drm/i915/i915_irq.c|  4 +-
 drivers/gpu/drm/i915/i915_suspend.c|  4 +-
 drivers/gpu/drm/i915/intel_crt.c   |  6 +--
 drivers/gpu/drm/i915/intel_display.c   | 41 ---
 drivers/gpu/drm/i915/intel_dp.c| 20 +++
 drivers/gpu/drm/i915/intel_drv.h   |  2 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +--
 drivers/gpu/drm/i915/intel_guc_loader.c|  3 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  2 +-
 drivers/gpu/drm/i915/intel_pm.c| 83 +++---
 drivers/gpu/drm/i915/intel_sprite.c|  4 +-
 21 files changed, 126 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 20689f1cd719..3a42df3a29e5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const 
uint16_t wm[8])
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
-   num_levels = ilk_wm_max_level(dev) + 1;
+   num_levels = ilk_wm_max_level(dev_priv) + 1;
 
drm_modeset_lock_all(dev);
 
@@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, const 
char __user *ubuf,
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
-   num_levels = ilk_wm_max_level(dev) + 1;
+   num_levels = ilk_wm_max_level(dev_priv) + 1;
 
if (len >= sizeof(tmp))
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5e7b6a1cb2c8..c1956855feb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
-   WARN_ON(!IS_GEN5(dev));
+   WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
@@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
int mmio_bar;
int mmio_size;
 
-   mmio_bar = IS_GEN2(dev) ? 1 : 0;
+   mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
/*
 * Before gen4, the registers and the GTT are behind different BARs.
 * However, from gen4 onwards, the registers and the GTT are shared
@@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
*dev_priv)
pci_set_master(pdev);
 
/* overlay on gen2 is broken and can't address above 1G */
-   if (IS_GEN2(dev)) {
+   if (IS_GEN2(dev_priv)) {
ret = dma_set_coherent_mask(>dev, DMA_BIT_MASK(30));
if (ret) {
DRM_ERROR("failed to set DMA mask\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f38b9755763..a05665af31be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
-#define IS_GEN3(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
-#define IS_GEN4(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
-#define IS_GEN5(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
-#define IS_GEN6(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
-#define IS_GEN7(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
-#define IS_GEN8(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
-#define IS_GEN9(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
+#define IS_GEN2(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(3)))
+#define