On Fri, Feb 14, 2020 at 09:10:38AM -0800, Matt Roper wrote:
> On Wed, Feb 12, 2020 at 11:17:28AM -0800, Rafael Antognolli wrote:
> > It's not clear whether this workaround is final yet, but the BSpec
> > indicates that userspace needs to set bit 9 of this register on demand:
> >
> >"To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
> >Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"
> >
> > BugLink: https://gitlab.freedesktop.org/mesa/mesa/issues/2501
> > Signed-off-by: Rafael Antognolli
>
> Seems like the right register to whitelist to allow userspace to apply
> the workaround.
>
> Reviewed-by: Matt Roper
>
> I think we can drop the "Allow userpace to implement this workaround"
> part of the comment; that part is self-explanatory given that it's a
> whitelist entry. Do you mind if we just tweak the comment while
> applying? It looks like the CI shards queue is massive right now so
> it's already going to take a long time to get the full results back for
> this patch; no need to make it even longer by resubmitting for a trivial
> comment shortening.
I don't mind it at all, feel free to change it however you want.
Thanks!
Rafael
>
> Matt
>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 62b43f538a56..57b9685d9347 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1264,6 +1264,12 @@ static void tgl_whitelist_build(struct
> > intel_engine_cs *engine)
> > whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> > RING_FORCE_TO_NONPRIV_ACCESS_RD |
> > RING_FORCE_TO_NONPRIV_RANGE_4);
> > +
> > + /* Wa_1808121037:tgl
> > +*
> > +* Allow userpace to implement this workaround.
> > +*/
> > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
> > break;
> > default:
> > break;
> > --
> > 2.25.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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