Re: [Intel-gfx] [CI RESEND] drm/i915: convert device info num_pipes to pipe_mask
On Wed, 11 Sep 2019, Jani Nikula wrote:
> Replace device info number of pipes with a bit mask of available
> pipes. This will prove handy in the future. There's still a bunch of
> future work to do to actually allow a non-consecutive mask of pipes, but
> it's a start. No functional changes.
>
> Cc: Chris Wilson
> Cc: José Roberto de Souza
> Cc: Ville Syrjälä
> Reviewed-by: José Roberto de Souza
> Acked-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
And pushed, thanks for the review, on to the next one...
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 24
> drivers/gpu/drm/i915/intel_device_info.c | 10 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 84fb0245cf62..bf600888b3f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2188,9 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define GT_FREQUENCY_MULTIPLIER 50
> #define GEN9_FREQ_SCALER 3
>
> -#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
> +#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
>
> -#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
> +#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
>
> static inline bool intel_vtd_active(void)
> {
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b3cc8560696b..698116276441 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -147,7 +147,7 @@
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_overlay = 1, \
> .display.cursor_needs_physical = 1, \
> .display.overlay_needs_physical = 1, \
> @@ -165,7 +165,7 @@
>
> #define I845_FEATURES \
> GEN(2), \
> - .num_pipes = 1, \
> + .pipe_mask = BIT(PIPE_A), \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> .display.has_gmch = 1, \
> @@ -203,7 +203,7 @@ static const struct intel_device_info intel_i865g_info = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .engine_mask = BIT(RCS0), \
> @@ -287,7 +287,7 @@ static const struct intel_device_info
> intel_pineview_m_info = {
>
> #define GEN4_FEATURES \
> GEN(4), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> @@ -337,7 +337,7 @@ static const struct intel_device_info intel_gm45_info = {
>
> #define GEN5_FEATURES \
> GEN(5), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> @@ -363,7 +363,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
>
> #define GEN6_FEATURES \
> GEN(6), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -411,7 +411,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> - .num_pipes = 3, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -462,7 +462,7 @@ static const struct intel_device_info
> intel_ivybridge_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> .gt = 2,
> - .num_pipes = 0, /* legal, last one wins */
> + .pipe_mask = 0, /* legal, last one wins */
> .has_l3_dpf = 1,
> };
>
> @@ -470,7 +470,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .num_pipes = 2,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_rps = true,
> @@ -560,7 +560,7 @@ static const struct intel_device_info
> intel_broadwell_gt3_info = {
> static const struct intel_device_info intel_cherryview_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .num_pipes = 3,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .display.has_hotplug = 1,
> .is_lp = 1,
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@
[Intel-gfx] [CI RESEND] drm/i915: convert device info num_pipes to pipe_mask
Replace device info number of pipes with a bit mask of available
pipes. This will prove handy in the future. There's still a bunch of
future work to do to actually allow a non-consecutive mask of pipes, but
it's a start. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 24
drivers/gpu/drm/i915/intel_device_info.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84fb0245cf62..bf600888b3f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2188,9 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define GT_FREQUENCY_MULTIPLIER 50
#define GEN9_FREQ_SCALER 3
-#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
+#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
-#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
static inline bool intel_vtd_active(void)
{
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..698116276441 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -147,7 +147,7 @@
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_overlay = 1, \
.display.cursor_needs_physical = 1, \
.display.overlay_needs_physical = 1, \
@@ -165,7 +165,7 @@
#define I845_FEATURES \
GEN(2), \
- .num_pipes = 1, \
+ .pipe_mask = BIT(PIPE_A), \
.display.has_overlay = 1, \
.display.overlay_needs_physical = 1, \
.display.has_gmch = 1, \
@@ -203,7 +203,7 @@ static const struct intel_device_info intel_i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.engine_mask = BIT(RCS0), \
@@ -287,7 +287,7 @@ static const struct intel_device_info intel_pineview_m_info
= {
#define GEN4_FEATURES \
GEN(4), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
@@ -337,7 +337,7 @@ static const struct intel_device_info intel_gm45_info = {
#define GEN5_FEATURES \
GEN(5), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_snoop = true, \
@@ -363,7 +363,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
#define GEN6_FEATURES \
GEN(6), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -411,7 +411,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .num_pipes = 3, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -462,7 +462,7 @@ static const struct intel_device_info
intel_ivybridge_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .num_pipes = 0, /* legal, last one wins */
+ .pipe_mask = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -470,7 +470,7 @@ static const struct intel_device_info intel_valleyview_info
= {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .num_pipes = 2,
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_rps = true,
@@ -560,7 +560,7 @@ static const struct intel_device_info
intel_broadwell_gt3_info = {
static const struct intel_device_info intel_cherryview_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .num_pipes = 3,
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
.display.has_hotplug = 1,
.is_lp = 1,
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -631,7 +631,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.is_lp = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .num_pipes = 3, \
+
