[Intel-gfx] [PATCH] drm/i915/dp: Allow for 5.4Gbps for Haswell.
With Haswell, 5.4Gbps is supported. And almost all of the code was
already in place already. All that was missing was this tiny bit of
additional wiring.
Signed-off-by: Carl Worth cwo...@cworth.org
Reviewed-by: Keith Packard kei...@keithp.com
---
drivers/gpu/drm/i915/intel_dp.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 57552eb..ce9739e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -101,7 +101,11 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
case DP_LINK_BW_1_62:
case DP_LINK_BW_2_7:
break;
- case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
+ case DP_LINK_BW_5_4:
+ /* XXX: But not HASWELL ULX. */
+ if (IS_HASWELL(intel_dp_to_dev(intel_dp)))
+ break;
+ /* Prior to HASWELL, maximum support is for 2.7 Gbps */
max_link_bw = DP_LINK_BW_2_7;
break;
default:
@@ -810,12 +814,24 @@ intel_dp_compute_config(struct intel_encoder *encoder,
enum port port = dp_to_dig_port(intel_dp)-port;
struct intel_crtc *intel_crtc = encoder-new_crtc;
struct intel_connector *intel_connector = intel_dp-attached_connector;
- int lane_count, clock;
+ int lane_count;
int max_lane_count = drm_dp_max_lane_count(intel_dp-dpcd);
- int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 :
0;
int bpp, mode_rate;
- static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
int link_avail, link_clock;
+ int max_link_bw;
+ /* The clock and max_clock values are an index into bws. */
+ int clock, max_clock = 0;
+ static int bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4};
+
+ max_link_bw = intel_dp_max_link_bw(intel_dp);
+
+ for (clock = 0; clock ARRAY_SIZE(bws); clock++) {
+ if (bws[clock] == max_link_bw) {
+ max_clock = clock;
+ break;
+ }
+ }
+
if (HAS_PCH_SPLIT(dev) !HAS_DDI(dev) port != PORT_A)
pipe_config-has_pch_encoder = true;
--
1.9.0
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Re: [Intel-gfx] [PATCH] drm/i915/dp: Allow for 5.4Gbps for Haswell.
On Thu, Feb 27, 2014 at 12:11:39AM -0800, Carl Worth wrote: With Haswell, 5.4Gbps is supported. And almost all of the code was already in place already. All that was missing was this tiny bit of additional wiring. Todd already implemented 5.4Gbps support a while back. So it seems your tree is a bit out of date. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dp: Allow for 5.4Gbps for Haswell.
Ville Syrjälä ville.syrj...@linux.intel.com writes: Todd already implemented 5.4Gbps support a while back. So it seems your tree is a bit out of date. I didn't find it on drm-intel-fixes-2014-02-14; can you explain which tree it is present in? -- keith.pack...@intel.com pgpDBs_8j9uhj.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dp: Allow for 5.4Gbps for Haswell.
2014-02-27 15:21 GMT-03:00 Keith Packard kei...@keithp.com: Ville Syrjälä ville.syrj...@linux.intel.com writes: Todd already implemented 5.4Gbps support a while back. So it seems your tree is a bit out of date. I didn't find it on drm-intel-fixes-2014-02-14; can you explain which tree it is present in? It's on the drm-intel-next-queued branch. Please notice we recently moved the tree from freedesktop.org/~danvet/drm-intel to freedesktop.org/drm-intel. http://cgit.freedesktop.org/drm-intel/commit/?h=drm-intel-next-queuedid=06ea66b6bb445043dc25a9626254d5c130093199 -- keith.pack...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
