[Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-20 Thread Madhav Chauhan 
As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values(HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption for some scenarios.

v2: Rebased to new CDLCK code framework
v3: Addressed review comments from Ander/Jani
- Add comment in code about 99% usage of CDCLK
- Calculate max dot clock as well with 99% limit

Signed-off-by: Madhav Chauhan 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index c2cc33f..a661c7e 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,13 @@ static int bxt_calc_cdclk(int max_pixclk)
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-   if (max_pixclk > 2 * 158400)
+   /*
+* For GLK platform 316.8, 158.4, 79.2 MHz are the CDCLK values
+* as per BSPEC. But practically we can only achieve 99% of these.
+*/
+   if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
return 316800;
-   else if (max_pixclk > 2 * 79200)
+   else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
return 158400;
else
return 79200;
@@ -1613,7 +1617,6 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state 
*state)
cdclk = bxt_calc_cdclk(max_pixclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
-
if (cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
  cdclk, dev_priv->max_cdclk_freq);
@@ -1647,7 +1650,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
if (IS_GEMINILAKE(dev_priv))
-   return 2 * max_cdclk_freq;
+   return 2 * max_cdclk_freq * 99/100;
else if (INTEL_INFO(dev_priv)->gen >= 9 ||
 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return max_cdclk_freq;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-20 Thread Chauhan, Madhav 
> -Original Message-
> From: Chauhan, Madhav
> Sent: Friday, March 17, 2017 7:11 PM
> To: Nikula, Jani <jani.nik...@intel.com>; Ander Conselvan De Oliveira
> <conselv...@gmail.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for
> glk
> 
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Thursday, March 16, 2017 7:00 PM
> > To: Ander Conselvan De Oliveira <conselv...@gmail.com>; Chauhan,
> > Madhav <madhav.chau...@intel.com>; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation
> > changes for glk
> >
> > On Thu, 16 Mar 2017, Ander Conselvan De Oliveira
> > <conselv...@gmail.com> wrote:
> > > On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> > >> On Thu, 16 Mar 2017, "Chauhan, Madhav"
> > <madhav.chau...@intel.com> wrote:
> > >> > > -Original Message-
> > >> > > From: Nikula, Jani
> > >> > > Sent: Thursday, February 16, 2017 9:03 PM
> > >> > > To: Chauhan, Madhav <madhav.chau...@intel.com>; intel-
> > >> > > g...@lists.freedesktop.org
> > >> > > Cc: Conselvan De Oliveira, Ander
> > >> > > <ander.conselvan.de.olive...@intel.com>;
> > >> > > Shankar, Uma <uma.shan...@intel.com>; Mukherjee, Indranil
> > >> > > <indranil.mukher...@intel.com>; Sharma, Shashank
> > >> > > <shashank.sha...@intel.com>; Chauhan, Madhav
> > >> > > <madhav.chau...@intel.com>; ville.syrj...@linux.intel.com
> > >> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes
> > >> > > for glk
> > >> > >
> > >> > > On Thu, 16 Feb 2017, Madhav Chauhan
> > <madhav.chau...@intel.com>
> > >> > > wrote:
> > >> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 
> > >> > > > Mhz.
> > >> > > > Practically we can achive only 99% of these cdclk values(HW
> > >> > > > team checking on this). So cdclk should be calculated for the
> > >> > > > given pixclk as per that otherwise it may lead to screen
> > >> > > > corruption
> > for some scenarios.
> > >> > > >
> > >> > > > v2: Rebased to new CDLCK code framework
> > >> > > >
> > >> > > > Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
> > >> > > > ---
> > >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> > >> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >> > > >
> > >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > index d643c0c..834df68 100644
> > >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int
> > >> > > > max_pixclk)
> > >> > > >
> > >> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> > >> > > > -  if (max_pixclk > 2 * 158400)
> > >> > > > +  if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> > >> > >
> > >> > > Where do we ensure we don't use pixel clock 312841..316800?
> > >> > > Clearly we shouldn't use that because we can't guarantee it
> > >> > > works,
> > right?
> > >> >
> > >> > Why do we need to ensure that ?? Can you please elaborate more on
> > this?
> > >> > Here we are finding one of  the defined CDCLK value for a pixel
> > >> > clock
> > >>
> > >> I probably had some great idea a month ago when I wrote that, but I
> > >> can no longer remember what it was. :(
> > >
> > > I'm not sure if that is what you meant, but if the hardware can't
> > > handle it,
> > > intel_compute_max_dotclk() needs to take the 99% limitation into
> > > account
> > too.
> > > I.e., max dot clock would be .99 * 2 *  316800 = 627264.
> >
> > Yes, thank you!

Tested this change on drm-tip. Found that 1-2

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-17 Thread Chauhan, Madhav 
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, March 16, 2017 7:00 PM
> To: Ander Conselvan De Oliveira <conselv...@gmail.com>; Chauhan,
> Madhav <madhav.chau...@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for
> glk
> 
> On Thu, 16 Mar 2017, Ander Conselvan De Oliveira
> <conselv...@gmail.com> wrote:
> > On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> >> On Thu, 16 Mar 2017, "Chauhan, Madhav"
> <madhav.chau...@intel.com> wrote:
> >> > > -Original Message-
> >> > > From: Nikula, Jani
> >> > > Sent: Thursday, February 16, 2017 9:03 PM
> >> > > To: Chauhan, Madhav <madhav.chau...@intel.com>; intel-
> >> > > g...@lists.freedesktop.org
> >> > > Cc: Conselvan De Oliveira, Ander
> >> > > <ander.conselvan.de.olive...@intel.com>;
> >> > > Shankar, Uma <uma.shan...@intel.com>; Mukherjee, Indranil
> >> > > <indranil.mukher...@intel.com>; Sharma, Shashank
> >> > > <shashank.sha...@intel.com>; Chauhan, Madhav
> >> > > <madhav.chau...@intel.com>; ville.syrj...@linux.intel.com
> >> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for
> >> > > glk
> >> > >
> >> > > On Thu, 16 Feb 2017, Madhav Chauhan
> <madhav.chau...@intel.com>
> >> > > wrote:
> >> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> >> > > > Practically we can achive only 99% of these cdclk values(HW
> >> > > > team checking on this). So cdclk should be calculated for the
> >> > > > given pixclk as per that otherwise it may lead to screen corruption
> for some scenarios.
> >> > > >
> >> > > > v2: Rebased to new CDLCK code framework
> >> > > >
> >> > > > Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
> >> > > > ---
> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> >> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> >> > > >
> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > index d643c0c..834df68 100644
> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> >> > > >
> >> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> >> > > > -if (max_pixclk > 2 * 158400)
> >> > > > +if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> >> > >
> >> > > Where do we ensure we don't use pixel clock 312841..316800?
> >> > > Clearly we shouldn't use that because we can't guarantee it works,
> right?
> >> >
> >> > Why do we need to ensure that ?? Can you please elaborate more on
> this?
> >> > Here we are finding one of  the defined CDCLK value for a pixel
> >> > clock
> >>
> >> I probably had some great idea a month ago when I wrote that, but I
> >> can no longer remember what it was. :(
> >
> > I'm not sure if that is what you meant, but if the hardware can't
> > handle it,
> > intel_compute_max_dotclk() needs to take the 99% limitation into account
> too.
> > I.e., max dot clock would be .99 * 2 *  316800 = 627264.
> 
> Yes, thank you!

Ok. Will include this change as well along with additional comments
for explaining 99% usage of cdclk inside glk_calc_cdclk.
Thanks for review.

> 
> Jani.
> 
> >
> > Ander
> >
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> > >
> >> > > Before we get the spec update to confirm what to do, I think we
> >> > > need a comment here explaining what's going on.
> >> >
> >> > Will add the following comment, if that's fine, will send the rebased
> patch:
> >> > "For GLK platform, only 99% of the defined CDCLK value can be achieved
> >> >   So calculate pixel clock on that basis"
> >> >
> >> > Regards,
> >> > Madhav
> >> > >
> >> > > BR,
> >> > > Jani.
> >> > >
> >> > > >  return 316800;
> >> > > > -else if (max_pixclk > 2 * 79200)
> >> > > > +else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> >> > > >  return 158400;
> >> > > >  else
> >> > > >  return 79200;
> >> > >
> >> > > --
> >> > > Jani Nikula, Intel Open Source Technology Center
> >>
> >>
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-16 Thread Jani Nikula 
On Thu, 16 Mar 2017, Ander Conselvan De Oliveira  wrote:
> On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
>> On Thu, 16 Mar 2017, "Chauhan, Madhav"  wrote:
>> > > -Original Message-
>> > > From: Nikula, Jani
>> > > Sent: Thursday, February 16, 2017 9:03 PM
>> > > To: Chauhan, Madhav ; intel-
>> > > g...@lists.freedesktop.org
>> > > Cc: Conselvan De Oliveira, Ander ;
>> > > Shankar, Uma ; Mukherjee, Indranil
>> > > ; Sharma, Shashank
>> > > ; Chauhan, Madhav
>> > > ; ville.syrj...@linux.intel.com
>> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
>> > > 
>> > > On Thu, 16 Feb 2017, Madhav Chauhan 
>> > > wrote:
>> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> > > > Practically we can achive only 99% of these cdclk values(HW team
>> > > > checking on this). So cdclk should be calculated for the given pixclk
>> > > > as per that otherwise it may lead to screen corruption for some 
>> > > > scenarios.
>> > > > 
>> > > > v2: Rebased to new CDLCK code framework
>> > > > 
>> > > > Signed-off-by: Madhav Chauhan 
>> > > > ---
>> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
>> > > > 
>> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > index d643c0c..834df68 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>> > > > 
>> > > >  static int glk_calc_cdclk(int max_pixclk)  {
>> > > > -  if (max_pixclk > 2 * 158400)
>> > > > +  if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>> > > 
>> > > Where do we ensure we don't use pixel clock 312841..316800? Clearly we
>> > > shouldn't use that because we can't guarantee it works, right?
>> > 
>> > Why do we need to ensure that ?? Can you please elaborate more on this?  
>> > Here we are finding one of  the defined CDCLK value for a pixel clock
>> 
>> I probably had some great idea a month ago when I wrote that, but I can
>> no longer remember what it was. :(
>
> I'm not sure if that is what you meant, but if the hardware can't handle it,
> intel_compute_max_dotclk() needs to take the 99% limitation into account too.
> I.e., max dot clock would be .99 * 2 *  316800 = 627264.

Yes, thank you!

Jani.

>
> Ander
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> > > 
>> > > Before we get the spec update to confirm what to do, I think we need a
>> > > comment here explaining what's going on.
>> > 
>> > Will add the following comment, if that's fine, will send the rebased 
>> > patch:
>> > "For GLK platform, only 99% of the defined CDCLK value can be achieved 
>> >   So calculate pixel clock on that basis"
>> > 
>> > Regards,
>> > Madhav
>> > > 
>> > > BR,
>> > > Jani.
>> > > 
>> > > >return 316800;
>> > > > -  else if (max_pixclk > 2 * 79200)
>> > > > +  else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>> > > >return 158400;
>> > > >else
>> > > >return 79200;
>> > > 
>> > > --
>> > > Jani Nikula, Intel Open Source Technology Center
>> 
>> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-16 Thread Ander Conselvan De Oliveira 
On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> On Thu, 16 Mar 2017, "Chauhan, Madhav"  wrote:
> > > -Original Message-
> > > From: Nikula, Jani
> > > Sent: Thursday, February 16, 2017 9:03 PM
> > > To: Chauhan, Madhav ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: Conselvan De Oliveira, Ander ;
> > > Shankar, Uma ; Mukherjee, Indranil
> > > ; Sharma, Shashank
> > > ; Chauhan, Madhav
> > > ; ville.syrj...@linux.intel.com
> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
> > > 
> > > On Thu, 16 Feb 2017, Madhav Chauhan 
> > > wrote:
> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> > > > Practically we can achive only 99% of these cdclk values(HW team
> > > > checking on this). So cdclk should be calculated for the given pixclk
> > > > as per that otherwise it may lead to screen corruption for some 
> > > > scenarios.
> > > > 
> > > > v2: Rebased to new CDLCK code framework
> > > > 
> > > > Signed-off-by: Madhav Chauhan 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > index d643c0c..834df68 100644
> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> > > > 
> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> > > > -   if (max_pixclk > 2 * 158400)
> > > > +   if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> > > 
> > > Where do we ensure we don't use pixel clock 312841..316800? Clearly we
> > > shouldn't use that because we can't guarantee it works, right?
> > 
> > Why do we need to ensure that ?? Can you please elaborate more on this?  
> > Here we are finding one of  the defined CDCLK value for a pixel clock
> 
> I probably had some great idea a month ago when I wrote that, but I can
> no longer remember what it was. :(

I'm not sure if that is what you meant, but if the hardware can't handle it,
intel_compute_max_dotclk() needs to take the 99% limitation into account too.
I.e., max dot clock would be .99 * 2 *  316800 = 627264.

Ander

> 
> BR,
> Jani.
> 
> 
> > > 
> > > Before we get the spec update to confirm what to do, I think we need a
> > > comment here explaining what's going on.
> > 
> > Will add the following comment, if that's fine, will send the rebased patch:
> > "For GLK platform, only 99% of the defined CDCLK value can be achieved 
> >   So calculate pixel clock on that basis"
> > 
> > Regards,
> > Madhav
> > > 
> > > BR,
> > > Jani.
> > > 
> > > > return 316800;
> > > > -   else if (max_pixclk > 2 * 79200)
> > > > +   else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> > > > return 158400;
> > > > else
> > > > return 79200;
> > > 
> > > --
> > > Jani Nikula, Intel Open Source Technology Center
> 
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-16 Thread Jani Nikula 
On Thu, 16 Mar 2017, "Chauhan, Madhav"  wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, February 16, 2017 9:03 PM
>> To: Chauhan, Madhav ; intel-
>> g...@lists.freedesktop.org
>> Cc: Conselvan De Oliveira, Ander ;
>> Shankar, Uma ; Mukherjee, Indranil
>> ; Sharma, Shashank
>> ; Chauhan, Madhav
>> ; ville.syrj...@linux.intel.com
>> Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
>> 
>> On Thu, 16 Feb 2017, Madhav Chauhan 
>> wrote:
>> > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> > Practically we can achive only 99% of these cdclk values(HW team
>> > checking on this). So cdclk should be calculated for the given pixclk
>> > as per that otherwise it may lead to screen corruption for some scenarios.
>> >
>> > v2: Rebased to new CDLCK code framework
>> >
>> > Signed-off-by: Madhav Chauhan 
>> > ---
>> >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>> >  1 file changed, 2 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>> > b/drivers/gpu/drm/i915/intel_cdclk.c
>> > index d643c0c..834df68 100644
>> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>> >
>> >  static int glk_calc_cdclk(int max_pixclk)  {
>> > -  if (max_pixclk > 2 * 158400)
>> > +  if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>> 
>> Where do we ensure we don't use pixel clock 312841..316800? Clearly we
>> shouldn't use that because we can't guarantee it works, right?
> Why do we need to ensure that ?? Can you please elaborate more on this?  
> Here we are finding one of  the defined CDCLK value for a pixel clock

I probably had some great idea a month ago when I wrote that, but I can
no longer remember what it was. :(

BR,
Jani.


>> 
>> Before we get the spec update to confirm what to do, I think we need a
>> comment here explaining what's going on.
> Will add the following comment, if that's fine, will send the rebased patch:
> "For GLK platform, only 99% of the defined CDCLK value can be achieved 
>   So calculate pixel clock on that basis"
>
> Regards,
> Madhav
>> 
>> BR,
>> Jani.
>> 
>> >return 316800;
>> > -  else if (max_pixclk > 2 * 79200)
>> > +  else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>> >return 158400;
>> >else
>> >return 79200;
>> 
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-03-16 Thread Chauhan, Madhav 
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, February 16, 2017 9:03 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander ;
> Shankar, Uma ; Mukherjee, Indranil
> ; Sharma, Shashank
> ; Chauhan, Madhav
> ; ville.syrj...@linux.intel.com
> Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
> 
> On Thu, 16 Feb 2017, Madhav Chauhan 
> wrote:
> > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> > Practically we can achive only 99% of these cdclk values(HW team
> > checking on this). So cdclk should be calculated for the given pixclk
> > as per that otherwise it may lead to screen corruption for some scenarios.
> >
> > v2: Rebased to new CDLCK code framework
> >
> > Signed-off-by: Madhav Chauhan 
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index d643c0c..834df68 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> >
> >  static int glk_calc_cdclk(int max_pixclk)  {
> > -   if (max_pixclk > 2 * 158400)
> > +   if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> 
> Where do we ensure we don't use pixel clock 312841..316800? Clearly we
> shouldn't use that because we can't guarantee it works, right?
Why do we need to ensure that ?? Can you please elaborate more on this?  
Here we are finding one of  the defined CDCLK value for a pixel clock
> 
> Before we get the spec update to confirm what to do, I think we need a
> comment here explaining what's going on.
Will add the following comment, if that's fine, will send the rebased patch:
"For GLK platform, only 99% of the defined CDCLK value can be achieved 
  So calculate pixel clock on that basis"

Regards,
Madhav
> 
> BR,
> Jani.
> 
> > return 316800;
> > -   else if (max_pixclk > 2 * 79200)
> > +   else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> > return 158400;
> > else
> > return 79200;
> 
> --
> Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-02-16 Thread Jani Nikula 
On Thu, 16 Feb 2017, Madhav Chauhan  wrote:
> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> Practically we can achive only 99% of these cdclk values(HW team
> checking on this). So cdclk should be calculated for the given pixclk as
> per that otherwise it may lead to screen corruption for some scenarios.
>
> v2: Rebased to new CDLCK code framework
>
> Signed-off-by: Madhav Chauhan 
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index d643c0c..834df68 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>  
>  static int glk_calc_cdclk(int max_pixclk)
>  {
> - if (max_pixclk > 2 * 158400)
> + if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))

Where do we ensure we don't use pixel clock 312841..316800? Clearly we
shouldn't use that because we can't guarantee it works, right?

Before we get the spec update to confirm what to do, I think we need a
comment here explaining what's going on.

BR,
Jani.

>   return 316800;
> - else if (max_pixclk > 2 * 79200)
> + else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>   return 158400;
>   else
>   return 79200;

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-02-15 Thread Madhav Chauhan 
As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values(HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption for some scenarios.

v2: Rebased to new CDLCK code framework

Signed-off-by: Madhav Chauhan 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index d643c0c..834df68 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-   if (max_pixclk > 2 * 158400)
+   if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
return 316800;
-   else if (max_pixclk > 2 * 79200)
+   else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
return 158400;
else
return 79200;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-02-07 Thread Jani Nikula 
On Tue, 07 Feb 2017, Ville Syrjälä  wrote:
> On Tue, Feb 07, 2017 at 05:48:46AM -0500, Madhav Chauhan wrote:
>> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> Practically we can achive only 99% of these cdclk values. So cdclk
>> should be calculated for the given pixclk as per that otherwise it may
>> lead to screen corruption for some scenarios.
>
> I this caused by the hw actually requiring some guardband or simply
> because of our sucky DPLL code not updating the dotclock with the actual
> value the hw is going to produce?
>
> If it's a genuine hw limitation is it documented? And if not has
> someone filed a spec issue for it? And what about other platforms
> (GLK isn't the only one without a guardband in our code after all)?

Indeed. What's the 99% based on? Where is it documented?

BR,
Jani.

>
>> 
>> Signed-off-by: Madhav Chauhan 
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 45e5874..2e1bfe9 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>  
>>  static int glk_calc_cdclk(int max_pixclk)
>>  {
>> -if (max_pixclk > 2 * 158400)
>> +if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>>  return 316800;
>> -else if (max_pixclk > 2 * 79200)
>> +else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>>  return 158400;
>>  else
>>  return 79200;
>> -- 
>> 1.9.1
>> 
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-02-07 Thread Ville Syrjälä 
On Tue, Feb 07, 2017 at 05:48:46AM -0500, Madhav Chauhan wrote:
> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> Practically we can achive only 99% of these cdclk values. So cdclk
> should be calculated for the given pixclk as per that otherwise it may
> lead to screen corruption for some scenarios.

I this caused by the hw actually requiring some guardband or simply
because of our sucky DPLL code not updating the dotclock with the actual
value the hw is going to produce?

If it's a genuine hw limitation is it documented? And if not has
someone filed a spec issue for it? And what about other platforms
(GLK isn't the only one without a guardband in our code after all)?

> 
> Signed-off-by: Madhav Chauhan 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 45e5874..2e1bfe9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct 
> drm_i915_private *dev_priv,
>  
>  static int glk_calc_cdclk(int max_pixclk)
>  {
> - if (max_pixclk > 2 * 158400)
> + if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>   return 316800;
> - else if (max_pixclk > 2 * 79200)
> + else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>   return 158400;
>   else
>   return 79200;
> -- 
> 1.9.1
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for glk

2017-02-07 Thread Madhav Chauhan 
As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values. So cdclk
should be calculated for the given pixclk as per that otherwise it may
lead to screen corruption for some scenarios.

Signed-off-by: Madhav Chauhan 
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 45e5874..2e1bfe9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private 
*dev_priv,
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-   if (max_pixclk > 2 * 158400)
+   if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
return 316800;
-   else if (max_pixclk > 2 * 79200)
+   else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
return 158400;
else
return 79200;
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx