Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
Hi Shawn,
> -Original Message-
> From: Lee, Shawn C
> Sent: Tuesday, June 6, 2023 3:43 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lee, Shawn C ; Kahola, Mika
> ; Taylor, Clinton A ;
> Sripada, Radhakrishna ; Shankar, Uma
>
> Subject: [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP
> 1.4
>
> Add vswing table to support DP 1.4 for C20 phy.
>
> Bspec: 74104
> Signed-off-by: Lee Shawn C
> Cc: Mika Kahola
> Cc: Clint Taylor
> Cc: Radhakrishna Sripada
> Cc: Uma Shankar
> ---
> .../drm/i915/display/intel_ddi_buf_trans.c| 21 +++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index b7d20485bde5..6a1507515119 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1055,6 +1055,20 @@ static const struct intel_ddi_buf_trans mtl_cx0_trans
> = {
> .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
> };
>
> +/* DP1.4 */
> +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = {
> + { .snps = { 20, 0, 0 } }, /* preset 0 */
> + { .snps = { 24, 0, 4 } }, /* preset 1 */
> + { .snps = { 30, 0, 9 } }, /* preset 2 */
> + { .snps = { 34, 0, 14 } }, /* preset 3 */
> + { .snps = { 29, 0, 0 } }, /* preset 4 */
> + { .snps = { 34, 0, 5 } }, /* preset 5 */
> + { .snps = { 38, 0, 10 } }, /* preset 6 */
> + { .snps = { 36, 0, 0 } }, /* preset 7 */
> + { .snps = { 40, 0, 6 } }, /* preset 8 */
> + { .snps = { 48, 0, 0 } }, /* preset 9 */
> +};
> +
> /* DP2.0 */
> static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
> { .snps = { 48, 0, 0 } }, /* preset 0 */
> @@ -1090,6 +1104,11 @@ static const struct intel_ddi_buf_trans
> mtl_c20_trans_hdmi = {
> .hdmi_default_entry = 0,
> };
>
> +static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = {
> + .entries = _mtl_c20_trans_dp14,
> + .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14),
> +};
> +
> static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
> .entries = _mtl_c20_trans_uhbr,
> .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
> @@ -1678,6 +1697,8 @@ mtl_get_cx0_buf_trans(struct intel_encoder
> *encoder,
> return intel_get_buf_trans(_c20_trans_uhbr, n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_is_c10phy(i915, phy)))
> return intel_get_buf_trans(_c20_trans_hdmi, n_entries);
> + else if (!intel_is_c10phy(i915, phy))
> + return intel_get_buf_trans(_c20_trans_dp14, n_entries);
> else
> return intel_get_buf_trans(_cx0_trans, n_entries);
Nit: With mtl_c20_trans_dp14, mtl_cx0_trans looses its meaning and needs to be
renamed
As mtl_c10_trans or even better mtl_trans_dp14 for the sake of consistency.
With that,
Reviewed-by: Radhakrishna Sripada
--Radhakrishna(RK) Sripada
> }
> --
> 2.31.1
Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
> -Original Message-
> From: Lee, Shawn C
> Sent: Tuesday, June 6, 2023 1:43 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lee, Shawn C ; Kahola, Mika
> ; Taylor, Clinton A
> ; Sripada, Radhakrishna
> ; Shankar, Uma
>
> Subject: [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP
> 1.4
>
> Add vswing table to support DP 1.4 for C20 phy.
>
> Bspec: 74104
Reviewed-by: Mika Kahola
> Signed-off-by: Lee Shawn C
> Cc: Mika Kahola
> Cc: Clint Taylor
> Cc: Radhakrishna Sripada
> Cc: Uma Shankar
> ---
> .../drm/i915/display/intel_ddi_buf_trans.c| 21 +++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index b7d20485bde5..6a1507515119 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1055,6 +1055,20 @@ static const struct intel_ddi_buf_trans mtl_cx0_trans
> = {
> .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1, };
>
> +/* DP1.4 */
> +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = {
> + { .snps = { 20, 0, 0 } }, /* preset 0 */
> + { .snps = { 24, 0, 4 } }, /* preset 1 */
> + { .snps = { 30, 0, 9 } }, /* preset 2 */
> + { .snps = { 34, 0, 14 } }, /* preset 3 */
> + { .snps = { 29, 0, 0 } }, /* preset 4 */
> + { .snps = { 34, 0, 5 } }, /* preset 5 */
> + { .snps = { 38, 0, 10 } }, /* preset 6 */
> + { .snps = { 36, 0, 0 } }, /* preset 7 */
> + { .snps = { 40, 0, 6 } }, /* preset 8 */
> + { .snps = { 48, 0, 0 } }, /* preset 9 */
> +};
> +
> /* DP2.0 */
> static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
> { .snps = { 48, 0, 0 } }, /* preset 0 */
> @@ -1090,6 +1104,11 @@ static const struct intel_ddi_buf_trans
> mtl_c20_trans_hdmi = {
> .hdmi_default_entry = 0,
> };
>
> +static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = {
> + .entries = _mtl_c20_trans_dp14,
> + .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14), };
> +
> static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
> .entries = _mtl_c20_trans_uhbr,
> .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), @@ -1678,6 +1697,8 @@
> mtl_get_cx0_buf_trans(struct
> intel_encoder *encoder,
> return intel_get_buf_trans(_c20_trans_uhbr, n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_is_c10phy(i915, phy)))
> return intel_get_buf_trans(_c20_trans_hdmi, n_entries);
> + else if (!intel_is_c10phy(i915, phy))
> + return intel_get_buf_trans(_c20_trans_dp14, n_entries);
> else
> return intel_get_buf_trans(_cx0_trans, n_entries); }
> --
> 2.31.1
[Intel-gfx] [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
Add vswing table to support DP 1.4 for C20 phy.
Bspec: 74104
Signed-off-by: Lee Shawn C
Cc: Mika Kahola
Cc: Clint Taylor
Cc: Radhakrishna Sripada
Cc: Uma Shankar
---
.../drm/i915/display/intel_ddi_buf_trans.c| 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index b7d20485bde5..6a1507515119 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1055,6 +1055,20 @@ static const struct intel_ddi_buf_trans mtl_cx0_trans = {
.hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
};
+/* DP1.4 */
+static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = {
+ { .snps = { 20, 0, 0 } }, /* preset 0 */
+ { .snps = { 24, 0, 4 } }, /* preset 1 */
+ { .snps = { 30, 0, 9 } }, /* preset 2 */
+ { .snps = { 34, 0, 14 } }, /* preset 3 */
+ { .snps = { 29, 0, 0 } }, /* preset 4 */
+ { .snps = { 34, 0, 5 } }, /* preset 5 */
+ { .snps = { 38, 0, 10 } }, /* preset 6 */
+ { .snps = { 36, 0, 0 } }, /* preset 7 */
+ { .snps = { 40, 0, 6 } }, /* preset 8 */
+ { .snps = { 48, 0, 0 } }, /* preset 9 */
+};
+
/* DP2.0 */
static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
{ .snps = { 48, 0, 0 } }, /* preset 0 */
@@ -1090,6 +1104,11 @@ static const struct intel_ddi_buf_trans
mtl_c20_trans_hdmi = {
.hdmi_default_entry = 0,
};
+static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = {
+ .entries = _mtl_c20_trans_dp14,
+ .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14),
+};
+
static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
.entries = _mtl_c20_trans_uhbr,
.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
@@ -1678,6 +1697,8 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(_c20_trans_uhbr, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
!(intel_is_c10phy(i915, phy)))
return intel_get_buf_trans(_c20_trans_hdmi, n_entries);
+ else if (!intel_is_c10phy(i915, phy))
+ return intel_get_buf_trans(_c20_trans_dp14, n_entries);
else
return intel_get_buf_trans(_cx0_trans, n_entries);
}
--
2.31.1
