Re: [Intel-gfx] [PATCH] drm/i915/mtl: Cleanup usage of phy lane reset

2023-06-15 Thread Hogander, Jouni
On Tue, 2023-06-13 at 14:25 -0300, Gustavo Sousa wrote: > Quoting Mika Kahola (2023-06-09 09:21:30-03:00) > > From PICA message bus we wait for acknowledgment from > > read/write commands. In case of an error, we reset the > > bus for the next command. > > > > Current implementation ends up

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Cleanup usage of phy lane reset

2023-06-13 Thread Gustavo Sousa
Quoting Mika Kahola (2023-06-09 09:21:30-03:00) >From PICA message bus we wait for acknowledgment from >read/write commands. In case of an error, we reset the >bus for the next command. > >Current implementation ends up resetting message bus twice >in cases where error is not the timeout. Since,

[Intel-gfx] [PATCH] drm/i915/mtl: Cleanup usage of phy lane reset

2023-06-09 Thread Mika Kahola
>From PICA message bus we wait for acknowledgment from read/write commands. In case of an error, we reset the bus for the next command. Current implementation ends up resetting message bus twice in cases where error is not the timeout. Since, we only need to reset message bus once, let's move