On Wed, May 06, 2015 at 03:05:04PM +0300, Imre Deak wrote:
On ke, 2015-05-06 at 14:28 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6328
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On ke, 2015-05-06 at 14:28 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing
From: Ville Syrjälä ville.syrj...@linux.intel.com
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.
Cc: Imre Deak
