> -Original Message-
> From: Andi Shyti
> Sent: Friday, April 28, 2023 12:07 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> > +static
Hi Mika,
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state =
>
> -Original Message-
> From: Kahola, Mika
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Souza, Jose
> ; Modem, Bhanuprakash
> ; Deak, Imre ;
> Murthy, Arun R
> Subject: [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> C20 phy PLL
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Saturday, April 22, 2023 2:24 AM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> On Thu, Ap
Hi Mika,
On Thu, Apr 20, 2023 at 03:40:38PM +0300, Mika Kahola wrote:
> C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
> 4 lane support for c20.
>
> Signed-off-by: José Roberto de Souza
>
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
