Hi Mika,
[...]
> +static int intel_c20_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> +
> -Original Message-
> From: Kahola, Mika
> Sent: Wednesday, April 26, 2023 4:43 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -Original Message-
>
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, April 27, 2023 6:31 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: RE: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -Original Message-
> > From: Kahola, Mika
> > Sent:
> -Original Message-
> From: Kahola, Mika
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Murthy, Arun R
> ; Nautiyal, Ankit K
> Subject: [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Monday, April 24, 2023 11:56 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> On Thu, Apr 20, 2023 at 03:40:39PM
On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
>
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
