And put it to use in the gtt configuration code that writes
the scratch page addr in all gtt ptes. This makes intel_i830_configure
generic, hence rename it to intel_fake_agp_configure.
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
drivers/char/agp/intel-gtt.c | 41 ++++++++++++++++++++++++++++++++---------
1 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index af920b5..59fad22 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -90,6 +90,10 @@ struct intel_gtt_driver {
unsigned int is_ironlake : 1;
/* Chipset specific GTT setup */
int (*setup)(void);
+ void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int
flags);
+ /* Flags is a more or less chipset specific opaque value.
+ * For chipsets that need to support old ums (non-gem) code, this
+ * needs to be identical to the various supported agp memory types! */
};
static struct _intel_private {
@@ -956,6 +960,23 @@ static void intel_i830_chipset_flush(struct
agp_bridge_data *bridge)
printk(KERN_ERR "Timed out waiting for cache flush.\n");
}
+static void i830_write_entry(dma_addr_t addr, unsigned int entry,
+ unsigned int flags)
+{
+ u32 pte_flags = I810_PTE_VALID;
+
+ switch (flags) {
+ case AGP_DCACHE_MEMORY:
+ pte_flags |= I810_PTE_LOCAL;
+ break;
+ case AGP_USER_CACHED_MEMORY:
+ pte_flags |= I830_PTE_SYSTEM_CACHED;
+ break;
+ }
+
+ writel(addr | pte_flags, intel_private.gtt + entry);
+}
+
static void intel_enable_gtt(void)
{
u32 ptetbl_addr, gma_addr;
@@ -1012,7 +1033,7 @@ static int intel_fake_agp_free_gatt_table(struct
agp_bridge_data *bridge)
return 0;
}
-static int intel_i830_configure(void)
+static int intel_fake_agp_configure(void)
{
int i;
@@ -1020,13 +1041,12 @@ static int intel_i830_configure(void)
agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
- if (agp_bridge->driver->needs_scratch_page) {
- for (i = intel_private.base.gtt_stolen_entries;
- i < intel_private.base.gtt_total_entries; i++) {
- writel(agp_bridge->scratch_page, intel_private.gtt+i);
- }
- readl(intel_private.gtt+i-1); /* PCI Posting. */
+ for (i = intel_private.base.gtt_stolen_entries;
+ i < intel_private.base.gtt_total_entries; i++) {
+
intel_private.driver->write_entry(intel_private.scratch_page_dma,
+ i, 0);
}
+ readl(intel_private.gtt+i-1); /* PCI Posting. */
global_cache_flush();
@@ -1414,7 +1434,7 @@ static const struct agp_bridge_driver intel_830_driver = {
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 4,
.needs_scratch_page = true,
- .configure = intel_i830_configure,
+ .configure = intel_fake_agp_configure,
.fetch_size = intel_fake_agp_fetch_size,
.cleanup = intel_gtt_cleanup,
.mask_memory = intel_i810_mask_memory,
@@ -1441,7 +1461,7 @@ static const struct agp_bridge_driver intel_915_driver = {
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 4,
.needs_scratch_page = true,
- .configure = intel_i9xx_configure,
+ .configure = intel_fake_agp_configure,
.fetch_size = intel_fake_agp_fetch_size,
.cleanup = intel_gtt_cleanup,
.mask_memory = intel_i810_mask_memory,
@@ -1570,10 +1590,13 @@ static const struct agp_bridge_driver intel_g33_driver
= {
static const struct intel_gtt_driver i8xx_gtt_driver = {
.gen = 2,
.setup = i830_setup,
+ .write_entry = i830_write_entry,
};
static const struct intel_gtt_driver i915_gtt_driver = {
.gen = 3,
.setup = i9xx_setup,
+ /* i945 is the last gpu to need phys mem (for overlay and cursors). */
+ .write_entry = i830_write_entry,
};
static const struct intel_gtt_driver g33_gtt_driver = {
.gen = 3,
--
1.7.1
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