[Intel-gfx] [PATCH 03/10] drm/i915/bdw: implement semaphore signal
From: Ben Widawsky b...@bwidawsk.net
Semaphore signalling works similarly to previous GENs with the exception
that the per ring mailboxes no longer exist. Instead you must define
your own space, somewhere in the GTT.
The comments in the code define the layout I've opted for, which should
be fairly future proof. Ie. I tried to define offsets in abstract terms
(NUM_RINGS, seqno size, etc).
NOTE: If one wanted to move this to the HWSP they could. I've decided
one 4k object would be easier to deal with, and provide potential wins
with cache locality, but that's all speculative.
v2: Update the macro to not need the other ring's ring-id (Chris)
Update the comment to use the correct formula (Chris)
v3: Move the macros the ringbuffer.h to prevent churn in next patch
(Ville)
v4: Fixed compilation rebase conflict
commit 1ec9e26ddab06459e89a890431b2de064c5d1056
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Feb 14 14:01:11 2014 +0100
drm/i915: Consolidate binding parameters into flags
v5: VCS2 rebase
Replace hweight_long with hweight32
v6 (Rodrigo): * Add missed VC2 gen8 ring signal init
* fixing conflicst on rebase
* minor fixes on address table
* remove WARN_ON
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 185 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 78 --
4 files changed, 189 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..61e43fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1374,6 +1374,7 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct intel_engine_cs ring[I915_NUM_RINGS];
+ struct drm_i915_gem_object *semaphore_obj;
uint32_t last_seqno, next_seqno;
drm_dma_handle_t *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3488567..2130d07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -240,7 +240,7 @@
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 19)
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 19)
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 19)
-#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
+#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
#define MI_SEMAPHORE_GLOBAL_GTT(122)
#define MI_SEMAPHORE_UPDATE (121)
#define MI_SEMAPHORE_COMPARE (120)
@@ -266,6 +266,8 @@
#define MI_RESTORE_EXT_STATE_EN (12)
#define MI_FORCE_RESTORE (11)
#define MI_RESTORE_INHIBIT (10)
+#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
+#define MI_SEMAPHORE_TARGET(engine) ((engine)15)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_MEM_VIRTUAL (1 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
@@ -360,6 +362,7 @@
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(110) /*
GM45+ only */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (19)
#define PIPE_CONTROL_NOTIFY (18)
+#define PIPE_CONTROL_FLUSH_ENABLE(17) /* gen7+ */
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (14)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (13)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (12)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e8be49b..a215ab4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -660,6 +660,13 @@ static int init_render_ring(struct intel_engine_cs *ring)
static void render_ring_cleanup(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-semaphore_obj) {
+ i915_gem_object_ggtt_unpin(dev_priv-semaphore_obj);
+ drm_gem_object_unreference(dev_priv-semaphore_obj-base);
+ dev_priv-semaphore_obj = NULL;
+ }
if (ring-scratch.obj == NULL)
return;
@@ -673,6 +680,80 @@ static void render_ring_cleanup(struct intel_engine_cs
*ring)
ring-scratch.obj = NULL;
}
+static int gen8_rcs_signal(struct intel_engine_cs *signaller,
+ unsigned int num_dwords)
+{
+#define MBOX_UPDATE_DWORDS 8
+ struct drm_device *dev = signaller-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *waiter;
+ int i, ret, num_rings;
+
+ num_rings = hweight32(INTEL_INFO(dev)-ring_mask);
+ num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
[Intel-gfx] [PATCH 03/10] drm/i915/bdw: implement semaphore signal
Semaphore signalling works similarly to previous GENs with the exception
that the per ring mailboxes no longer exist. Instead you must define
your own space, somewhere in the GTT.
The comments in the code define the layout I've opted for, which should
be fairly future proof. Ie. I tried to define offsets in abstract terms
(NUM_RINGS, seqno size, etc).
NOTE: If one wanted to move this to the HWSP they could. I've decided
one 4k object would be easier to deal with, and provide potential wins
with cache locality, but that's all speculative.
v2: Update the macro to not need the other ring's ring-id (Chris)
Update the comment to use the correct formula (Chris)
v3: Move the macros the ringbuffer.h to prevent churn in next patch
(Ville)
v4: Fixed compilation rebase conflict
commit 1ec9e26ddab06459e89a890431b2de064c5d1056
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Feb 14 14:01:11 2014 +0100
drm/i915: Consolidate binding parameters into flags
v5: VCS2 rebase
Replace hweight_long with hweight32
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 166 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 78 +--
4 files changed, 190 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26253c0..1ede818 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1355,6 +1355,7 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct intel_ring_buffer ring[I915_NUM_RINGS];
+ struct drm_i915_gem_object *semaphore_obj;
uint32_t last_seqno, next_seqno;
drm_dma_handle_t *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03ffc57..dc25084 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -232,7 +232,7 @@
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 19)
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 19)
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 19)
-#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
+#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
#define MI_SEMAPHORE_GLOBAL_GTT(122)
#define MI_SEMAPHORE_UPDATE (121)
#define MI_SEMAPHORE_COMPARE (120)
@@ -258,6 +258,8 @@
#define MI_RESTORE_EXT_STATE_EN (12)
#define MI_FORCE_RESTORE (11)
#define MI_RESTORE_INHIBIT (10)
+#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
+#define MI_SEMAPHORE_TARGET(engine) ((engine)15)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_MEM_VIRTUAL (1 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
@@ -352,6 +354,7 @@
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(110) /*
GM45+ only */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (19)
#define PIPE_CONTROL_NOTIFY (18)
+#define PIPE_CONTROL_FLUSH_ENABLE(17) /* gen7+ */
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (14)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (13)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (12)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d52c8a..b69eceb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -650,6 +650,13 @@ static int init_render_ring(struct intel_ring_buffer *ring)
static void render_ring_cleanup(struct intel_ring_buffer *ring)
{
struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (dev_priv-semaphore_obj) {
+ i915_gem_object_ggtt_unpin(dev_priv-semaphore_obj);
+ drm_gem_object_unreference(dev_priv-semaphore_obj-base);
+ dev_priv-semaphore_obj = NULL;
+ }
if (ring-scratch.obj == NULL)
return;
@@ -663,6 +670,85 @@ static void render_ring_cleanup(struct intel_ring_buffer
*ring)
ring-scratch.obj = NULL;
}
+static int gen8_rcs_signal(struct intel_ring_buffer *signaller,
+ unsigned int num_dwords)
+{
+#define MBOX_UPDATE_DWORDS 8
+ struct drm_device *dev = signaller-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *waiter;
+ int i, ret, num_rings;
+
+ num_rings = hweight32(INTEL_INFO(dev)-ring_mask);
+ num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
+#undef MBOX_UPDATE_DWORDS
+
+ ret = intel_ring_begin(signaller, num_dwords);
+ if (ret)
+ return ret;
+
+ for_each_ring(waiter, dev_priv, i) {
+ u64 gtt_offset = signaller-semaphore.signal_ggtt[i];
+ if (gtt_offset ==
