Hi Mika,
> +
> + if (intel_c20_use_mplla(hw_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> + drm_dbg_kms(>drm, "mplla[%d] = 0x%.4x\n", i,
> hw_state->mplla[i]);
> + } else {
> + for (i = 0; i <
> -Original Message-
> From: Intel-gfx On Behalf Of Mika
> Kahola
> Sent: Thursday, April 20, 2023 6:11 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state
>
> As we already do with C10 chip, let
On Thu, Apr 20, 2023 at 03:40:40PM +0300, Mika Kahola wrote:
> As we already do with C10 chip, let's dump the pll
> hw state for C20 as well.
>
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
>
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
