On Mon, 2 Jul 2012 11:51:05 -0300, Eugeni Dodonov eugeni.dodo...@intel.com
wrote:
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
@@ -2444,7 +2457,7 @@ static void gen6_enable_rps(struct drm_device *dev)
Most of the RPS and RC6 enabling functionality is similar to what we had
on Gen6/Gen7, so we preserve most of the registers.
Note that Haswell only has RC6, so account for that as well. As suggested
by Daniel Vetter, to reduce the amount of changes in the patch, we still
write the RC6p/RC6pp
On Mon, 2 Jul 2012 11:51:05 -0300
Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Most of the RPS and RC6 enabling functionality is similar to what we had
on Gen6/Gen7, so we preserve most of the registers.
Note that Haswell only has RC6, so account for that as well. As suggested
by Daniel
On 07/02/2012 02:49 PM, Ben Widawsky wrote:
On Mon, 2 Jul 2012 11:51:05 -0300
Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Most of the RPS and RC6 enabling functionality is similar to what we had
on Gen6/Gen7, so we preserve most of the registers.
Note that Haswell only has RC6, so
On Mon, 02 Jul 2012 17:02:59 -0300
Eugeni Dodonov eugeni.dodo...@linux.intel.com wrote:
On 07/02/2012 02:49 PM, Ben Widawsky wrote:
On Mon, 2 Jul 2012 11:51:05 -0300
Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Most of the RPS and RC6 enabling functionality is similar to what we had
