Re: [Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8
On Mon, Jun 30, 2014 at 09:53:39AM -0700, Rodrigo Vivi wrote:
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 42
++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0217a41..66e2481 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2784,12 +2784,7 @@ static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
if (INTEL_INFO(dev)-gen = 8) {
- /*
- * FIXME: gen8 semaphore support - currently we don't emit
- * semaphores on bdw anyway, but this needs to be addressed when
- * we merge that code.
- */
- return false;
+ return (ipehr 23) == 0x1c;
} else {
ipehr = ~MI_SEMAPHORE_SYNC_MASK;
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
@@ -2798,19 +2793,20 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32
ipehr)
}
static struct intel_engine_cs *
-semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
+semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr,
u64 offset)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct intel_engine_cs *signaller;
int i;
if (INTEL_INFO(dev_priv-dev)-gen = 8) {
- /*
- * FIXME: gen8 semaphore support - currently we don't emit
- * semaphores on bdw anyway, but this needs to be addressed when
- * we merge that code.
- */
- return NULL;
+ for_each_ring(signaller, dev_priv, i) {
+ if (ring == signaller)
+ continue;
+
+ if (offset ==
signaller-semaphore.signal_ggtt[ring-id])
+ return signaller;
+ }
} else {
u32 sync_bits = ipehr MI_SEMAPHORE_SYNC_MASK;
@@ -2823,8 +2819,8 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring, u32 ipehr)
}
}
- DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x\n,
- ring-id, ipehr);
+ DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x, offset
0x%0%016llx\n,
The format string has a spurious 0% here. I've dropped it.
-Daniel
+ ring-id, ipehr, offset);
return NULL;
}
@@ -2834,7 +2830,8 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
u32 cmd, ipehr, head;
- int i;
+ u64 offset = 0;
+ int i, backwards;
ipehr = I915_READ(RING_IPEHR(ring-mmio_base));
if (!ipehr_is_semaphore_wait(ring-dev, ipehr))
@@ -2843,13 +2840,15 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
/*
* HEAD is likely pointing to the dword after the actual command,
* so scan backwards until we find the MBOX. But limit it to just 3
- * dwords. Note that we don't care about ACTHD here since that might
+ * or 4 dwords depending on the semaphore wait command size.
+ * Note that we don't care about ACTHD here since that might
* point at at batch, and semaphores are always emitted into the
* ringbuffer itself.
*/
head = I915_READ_HEAD(ring) HEAD_ADDR;
+ backwards = (INTEL_INFO(ring-dev)-gen = 8) ? 5 : 4;
- for (i = 4; i; --i) {
+ for (i = backwards; i; --i) {
/*
* Be paranoid and presume the hw has gone off into the wild -
* our ring is smaller than what the hardware (and hence
@@ -2869,7 +2868,12 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
return NULL;
*seqno = ioread32(ring-buffer-virtual_start + head + 4) + 1;
- return semaphore_wait_to_signaller_ring(ring, ipehr);
+ if (INTEL_INFO(ring-dev)-gen = 8) {
+ offset = ioread32(ring-buffer-virtual_start + head + 12);
+ offset = 32;
+ offset = ioread32(ring-buffer-virtual_start + head + 8);
+ }
+ return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
}
static int semaphore_passed(struct intel_engine_cs *ring)
--
1.9.3
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 -
[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8
Ipehr just carries Dword 0 and on Gen 8, offsets are located
on Dword 2 and 3 of MI_SEMAPHORE_WAIT.
This implementation was based on Ben's work and on Ville's suggestion for Ben
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 42 ++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0217a41..66e2481 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2784,12 +2784,7 @@ static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
if (INTEL_INFO(dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return false;
+ return (ipehr 23) == 0x1c;
} else {
ipehr = ~MI_SEMAPHORE_SYNC_MASK;
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
@@ -2798,19 +2793,20 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32
ipehr)
}
static struct intel_engine_cs *
-semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
+semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64
offset)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct intel_engine_cs *signaller;
int i;
if (INTEL_INFO(dev_priv-dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return NULL;
+ for_each_ring(signaller, dev_priv, i) {
+ if (ring == signaller)
+ continue;
+
+ if (offset ==
signaller-semaphore.signal_ggtt[ring-id])
+ return signaller;
+ }
} else {
u32 sync_bits = ipehr MI_SEMAPHORE_SYNC_MASK;
@@ -2823,8 +2819,8 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring, u32 ipehr)
}
}
- DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x\n,
- ring-id, ipehr);
+ DRM_ERROR(No signaller ring found for ring %i, ipehr 0x%08x, offset
0x%0%016llx\n,
+ ring-id, ipehr, offset);
return NULL;
}
@@ -2834,7 +2830,8 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
{
struct drm_i915_private *dev_priv = ring-dev-dev_private;
u32 cmd, ipehr, head;
- int i;
+ u64 offset = 0;
+ int i, backwards;
ipehr = I915_READ(RING_IPEHR(ring-mmio_base));
if (!ipehr_is_semaphore_wait(ring-dev, ipehr))
@@ -2843,13 +2840,15 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
/*
* HEAD is likely pointing to the dword after the actual command,
* so scan backwards until we find the MBOX. But limit it to just 3
-* dwords. Note that we don't care about ACTHD here since that might
+* or 4 dwords depending on the semaphore wait command size.
+* Note that we don't care about ACTHD here since that might
* point at at batch, and semaphores are always emitted into the
* ringbuffer itself.
*/
head = I915_READ_HEAD(ring) HEAD_ADDR;
+ backwards = (INTEL_INFO(ring-dev)-gen = 8) ? 5 : 4;
- for (i = 4; i; --i) {
+ for (i = backwards; i; --i) {
/*
* Be paranoid and presume the hw has gone off into the wild -
* our ring is smaller than what the hardware (and hence
@@ -2869,7 +2868,12 @@ semaphore_waits_for(struct intel_engine_cs *ring, u32
*seqno)
return NULL;
*seqno = ioread32(ring-buffer-virtual_start + head + 4) + 1;
- return semaphore_wait_to_signaller_ring(ring, ipehr);
+ if (INTEL_INFO(ring-dev)-gen = 8) {
+ offset = ioread32(ring-buffer-virtual_start + head + 12);
+ offset = 32;
+ offset = ioread32(ring-buffer-virtual_start + head + 8);
+ }
+ return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
}
static int semaphore_passed(struct intel_engine_cs *ring)
--
1.9.3
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Re: [Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8
On Mon, Jun 30, 2014 at 09:53:39AM -0700, Rodrigo Vivi wrote: Ipehr just carries Dword 0 and on Gen 8, offsets are located on Dword 2 and 3 of MI_SEMAPHORE_WAIT. This implementation was based on Ben's work and on Ville's suggestion for Ben Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Ben Widawsky b...@bwidawsk.net Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com Reviewed-by: Ben Widawsky b...@bwidawsk.net -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8
From: Ben Widawsky benjamin.widaw...@linux.intel.com
This is needed to implement ipehr_is_semaphore_wait
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_irq.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2d76183..bfd21c7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2561,12 +2561,9 @@ static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
if (INTEL_INFO(dev)-gen = 8) {
- /*
-* FIXME: gen8 semaphore support - currently we don't emit
-* semaphores on bdw anyway, but this needs to be addressed when
-* we merge that code.
-*/
- return false;
+ /* Broadwell's semaphore wait is 3 dwords. We hope IPEHR is the
+* first dword. */
+ return (ipehr 23) == 0x1c;
} else {
ipehr = ~MI_SEMAPHORE_SYNC_MASK;
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
@@ -2586,6 +2583,8 @@ semaphore_wait_to_signaller_ring(struct intel_ring_buffer
*ring, u32 ipehr)
* FIXME: gen8 semaphore support - currently we don't emit
* semaphores on bdw anyway, but this needs to be addressed when
* we merge that code.
+*
+* XXX: Gen8 needs more than just IPEHR.
*/
return NULL;
} else {
--
1.9.2
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